/[gxemul]/trunk/src/devices/dev_openpic.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Annotation of /trunk/src/devices/dev_openpic.c

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Revision 73 - (hide annotations)
Sun Oct 14 18:35:57 2007 UTC (11 years, 8 months ago) by dpavlin
File MIME type: text/plain
File size: 9466 byte(s)
try to decode vector from offset... doesn't work for external irqs
1 dpavlin 22 /*
2 dpavlin 34 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 dpavlin 22 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27 dpavlin 63 * $Id: dev_openpic.c,v 1.14 2007/09/11 21:42:52 debug Exp $
28 dpavlin 22 *
29 dpavlin 63 * COMMENT: OpenPIC Interrupt controller (used by sandpoint ppc)
30 dpavlin 64 * based on dev_gc.c
31 dpavlin 22 */
32    
33     #include <stdio.h>
34     #include <stdlib.h>
35     #include <string.h>
36    
37     #include "cpu.h"
38     #include "device.h"
39     #include "machine.h"
40     #include "memory.h"
41     #include "misc.h"
42    
43    
44 dpavlin 63 #define DEV_OPENPIC_LENGTH 0x40000
45 dpavlin 34
46 dpavlin 63 struct openpic_data {
47 dpavlin 34 struct interrupt cpu_irq;
48    
49     uint32_t status_hi;
50     uint32_t status_lo;
51     uint32_t enable_hi;
52     uint32_t enable_lo;
53     };
54    
55    
56 dpavlin 63 void openpic_hi_interrupt_assert(struct interrupt *interrupt)
57 dpavlin 34 {
58 dpavlin 63 struct openpic_data *d = interrupt->extra;
59 dpavlin 34 d->status_hi |= interrupt->line;
60     if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)
61     INTERRUPT_ASSERT(d->cpu_irq);
62     }
63 dpavlin 63 void openpic_hi_interrupt_deassert(struct interrupt *interrupt)
64 dpavlin 34 {
65 dpavlin 63 struct openpic_data *d = interrupt->extra;
66 dpavlin 34 d->status_hi &= ~interrupt->line;
67     if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi))
68     INTERRUPT_DEASSERT(d->cpu_irq);
69     }
70 dpavlin 63 void openpic_lo_interrupt_assert(struct interrupt *interrupt)
71 dpavlin 34 {
72 dpavlin 63 struct openpic_data *d = interrupt->extra;
73 dpavlin 34 d->status_lo |= interrupt->line;
74     if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)
75     INTERRUPT_ASSERT(d->cpu_irq);
76     }
77 dpavlin 63 void openpic_lo_interrupt_deassert(struct interrupt *interrupt)
78 dpavlin 34 {
79 dpavlin 63 struct openpic_data *d = interrupt->extra;
80 dpavlin 34 d->status_lo &= ~interrupt->line;
81     if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi))
82     INTERRUPT_DEASSERT(d->cpu_irq);
83     }
84    
85 dpavlin 68 /*
86     * FIXME acitvity is never sat
87     */
88    
89 dpavlin 66 #define OPENPIC_MASK 0x80000000
90     #define OPENPIC_ACTIVITY 0x40000000 /* Read Only */
91     #define OPENPIC_PRIORITY_MASK 0x000f0000
92     #define OPENPIC_PRIORITY_SHIFT 16
93     #define OPENPIC_VECTOR_MASK 0x000000ff
94 dpavlin 34
95 dpavlin 66 #define OPENPIC_VEC_TIMER 64 /* and up */
96     #define OPENPIC_VEC_IPI 72 /* and up */
97     #define OPENPIC_VEC_SPURIOUS 127
98    
99 dpavlin 67 #define OPENPIC_NUM_TIMERS 4
100     #define OPENPIC_NUM_IPI 4
101     #define OPENPIC_NUM_PRI 16
102     #define OPENPIC_NUM_VECTORS 256
103    
104 dpavlin 63 DEVICE_ACCESS(openpic)
105 dpavlin 22 {
106 dpavlin 64 // struct openpic_data *d = extra;
107 dpavlin 68 uint64_t idata = 0, odata = 0;
108 dpavlin 22
109 dpavlin 67 if (writeflag == MEM_WRITE) {
110 dpavlin 22 idata = memory_readmax64(cpu, data, len);
111 dpavlin 68 // shuffle byte order
112     idata =
113 dpavlin 67 ( idata & 0x000000ff ) << 24 |
114     ( idata & 0x0000ff00 ) << 8 |
115     ( idata & 0x00ff0000 ) >> 8 |
116     ( idata & 0xff000000 ) >> 24 ;
117 dpavlin 22
118 dpavlin 67 uint64_t priority,vector, active;
119 dpavlin 68 priority = ( idata & OPENPIC_PRIORITY_MASK ) >> OPENPIC_PRIORITY_SHIFT;
120     vector = ( idata & OPENPIC_VECTOR_MASK );
121     active = ( idata & OPENPIC_ACTIVITY );
122 dpavlin 66
123 dpavlin 68 debug("[ openpic: WRITE %05x | %08x | priority: %x vector: 0x%02x %d active: %x ]\n",
124     (int)relative_addr, (int)idata, (int)priority, (int)vector, (int)vector, (int)active );
125 dpavlin 67 }
126 dpavlin 66
127 dpavlin 22 switch (relative_addr) {
128    
129 dpavlin 68 // version
130 dpavlin 65 case 0x00:
131 dpavlin 66 if (writeflag == MEM_READ) {
132 dpavlin 69 // version 1.x, so 2 -> 1.2
133     odata = 2;
134 dpavlin 73 debug("[ openpic: read version "
135     "offset 0x%x = 1.%d]\n", (int)
136     relative_addr, (int)odata);
137     odata |= 0x00190000; // FIXME ?
138    
139 dpavlin 66 }
140     fatal("[ openpic: unimplemented write to "
141     "offset 0x%x: data=0x%x (OpenPIC version) ]\n", (int)
142     relative_addr, (int)idata);
143 dpavlin 65 break;
144    
145 dpavlin 68 // global timer frequency
146     case 0xf0:
147     if (writeflag == MEM_READ) {
148 dpavlin 73 // this would be correct, but real DSM-G600 isn't
149     // returning it!
150     //odata = 170 * 1000000; // MHz
151     odata = 0;
152     debug("[ openpic: read global timer frequency "
153 dpavlin 68 "offset 0x%x = %x]\n", (int)
154     relative_addr, (int)odata);
155     }
156     fatal("[ openpic: unimplemented write to "
157     "offset 0x%x: data=0x%x ]\n", (int)
158     relative_addr, (int)idata);
159     break;
160    
161 dpavlin 22 #if 0
162     #define INT_STATE_REG_H (interrupt_reg + 0x00)
163     #define INT_ENABLE_REG_H (interrupt_reg + 0x04)
164     #define INT_CLEAR_REG_H (interrupt_reg + 0x08)
165     #define INT_LEVEL_REG_H (interrupt_reg + 0x0c)
166     #define INT_STATE_REG_L (interrupt_reg + 0x10)
167     #define INT_ENABLE_REG_L (interrupt_reg + 0x14)
168     #define INT_CLEAR_REG_L (interrupt_reg + 0x18)
169     #define INT_LEVEL_REG_L (interrupt_reg + 0x1c)
170    
171     case 0x10:
172     if (writeflag == MEM_READ)
173 dpavlin 24 odata = d->status_hi & d->enable_hi;
174 dpavlin 22 break;
175    
176     case 0x14:
177     if (writeflag == MEM_READ)
178     odata = d->enable_hi;
179     else {
180 dpavlin 34 int old_assert = (d->status_lo & d->enable_lo
181     || d->status_hi & d->enable_hi);
182     int new_assert;
183 dpavlin 22 d->enable_hi = idata;
184 dpavlin 34
185     new_assert = (d->status_lo & d->enable_lo ||
186     d->status_hi & d->enable_hi);
187    
188     if (old_assert && !new_assert)
189     INTERRUPT_DEASSERT(d->cpu_irq);
190     else if (!old_assert && new_assert)
191     INTERRUPT_ASSERT(d->cpu_irq);
192 dpavlin 22 }
193     break;
194    
195     case 0x18:
196     if (writeflag == MEM_WRITE) {
197 dpavlin 34 int old_assert = (d->status_lo & d->enable_lo
198     || d->status_hi & d->enable_hi);
199     int new_assert;
200 dpavlin 22 d->status_hi &= ~idata;
201 dpavlin 34
202     new_assert = (d->status_lo & d->enable_lo ||
203     d->status_hi & d->enable_hi);
204    
205     if (old_assert && !new_assert)
206     INTERRUPT_DEASSERT(d->cpu_irq);
207     else if (!old_assert && new_assert)
208     INTERRUPT_ASSERT(d->cpu_irq);
209 dpavlin 22 }
210     break;
211    
212     case 0x20:
213     if (writeflag == MEM_READ)
214 dpavlin 24 odata = d->status_lo & d->enable_lo;
215 dpavlin 22 break;
216    
217     case 0x24:
218     if (writeflag == MEM_READ)
219     odata = d->enable_lo;
220     else {
221 dpavlin 34 int old_assert = (d->status_lo & d->enable_lo
222     || d->status_hi & d->enable_hi);
223     int new_assert;
224 dpavlin 22 d->enable_lo = idata;
225 dpavlin 34
226     new_assert = (d->status_lo & d->enable_lo ||
227     d->status_hi & d->enable_hi);
228    
229     if (old_assert && !new_assert)
230     INTERRUPT_DEASSERT(d->cpu_irq);
231     else if (!old_assert && new_assert)
232     INTERRUPT_ASSERT(d->cpu_irq);
233 dpavlin 22 }
234     break;
235    
236     case 0x28:
237     if (writeflag == MEM_WRITE) {
238 dpavlin 34 int old_assert = (d->status_lo & d->enable_lo
239     || d->status_hi & d->enable_hi);
240     int new_assert;
241 dpavlin 22 d->status_lo &= ~idata;
242 dpavlin 34
243     new_assert = (d->status_lo & d->enable_lo ||
244     d->status_hi & d->enable_hi);
245    
246     if (old_assert && !new_assert)
247     INTERRUPT_DEASSERT(d->cpu_irq);
248     else if (!old_assert && new_assert)
249     INTERRUPT_ASSERT(d->cpu_irq);
250 dpavlin 22 }
251     break;
252    
253 dpavlin 44 case 0x1c:
254 dpavlin 24 case 0x2c:
255 dpavlin 34 /* Avoid a debug message. */
256 dpavlin 24 break;
257 dpavlin 64 #endif
258 dpavlin 68 default:
259     if (writeflag == MEM_WRITE) {
260 dpavlin 63 fatal("[ openpic: unimplemented write to "
261 dpavlin 68 "offset 0x%x idata = %x ]\n",
262     (int)relative_addr, (int)idata
263     );
264 dpavlin 22 } else {
265 dpavlin 73 // decoded from real device
266     odata |= OPENPIC_MASK;
267    
268     int vec =
269     (
270     (
271     (
272     (
273     ( relative_addr - 0x120 ) & 0xfff
274     ) / 0x40
275     )
276     ) & 0xff
277     ) + 0x40;
278    
279     odata |= vec;
280    
281     debug("[ openpic: unimplemented read from "
282     "offset 0x%x decoded vec = 0x%02x %d odata = %x ]\n",
283     (int)relative_addr, vec, vec, (int)odata
284 dpavlin 68 );
285 dpavlin 22 }
286     }
287    
288 dpavlin 68 if (writeflag == MEM_READ) {
289 dpavlin 73
290     debug("[ openpic: READ %05x | %08x ]\n",
291     (int)relative_addr, (int)odata
292     );
293    
294 dpavlin 68 // shuffle byte order
295     odata =
296     ( odata & 0x000000ff ) << 24 |
297     ( odata & 0x0000ff00 ) << 8 |
298     ( odata & 0x00ff0000 ) >> 8 |
299     ( odata & 0xff000000 ) >> 24 ;
300 dpavlin 22 memory_writemax64(cpu, data, len, odata);
301 dpavlin 68 }
302 dpavlin 22
303     return 1;
304     }
305    
306    
307 dpavlin 63 DEVINIT(openpic)
308 dpavlin 22 {
309 dpavlin 63 struct openpic_data *d;
310 dpavlin 34 int i;
311 dpavlin 22
312 dpavlin 63 CHECK_ALLOCATION(d = malloc(sizeof(struct openpic_data)));
313     memset(d, 0, sizeof(struct openpic_data));
314 dpavlin 22
315 dpavlin 42 /* Connect to the CPU interrupt pin: */
316 dpavlin 34 INTERRUPT_CONNECT(devinit->interrupt_path, d->cpu_irq);
317 dpavlin 22
318 dpavlin 34 /*
319 dpavlin 64 * Register the 126 OpenPIC interrupts
320 dpavlin 34 */
321 dpavlin 64 for (i=0; i<126; i++) {
322 dpavlin 34 struct interrupt template;
323     char n[300];
324 dpavlin 64 snprintf(n, sizeof(n), "%s.openpic.%i",
325 dpavlin 34 devinit->interrupt_path, i);
326     memset(&template, 0, sizeof(template));
327     template.line = 1 << i;
328     template.name = n;
329     template.extra = d;
330 dpavlin 63 template.interrupt_assert = openpic_lo_interrupt_assert;
331     template.interrupt_deassert = openpic_lo_interrupt_deassert;
332 dpavlin 34 interrupt_handler_register(&template);
333 dpavlin 71 // debug("[ openpic: added interrupt %s ]\n", n);
334 dpavlin 34 }
335    
336 dpavlin 63 memory_device_register(devinit->machine->memory, "openpic",
337     devinit->addr, DEV_OPENPIC_LENGTH, dev_openpic_access, d, DM_DEFAULT, NULL);
338 dpavlin 34
339     return 1;
340 dpavlin 22 }
341    

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