src/devices/dev_openpic.c

/*
 *  Copyright (C) 2005-2007  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *   
 *  $Id: dev_openpic.c,v 1.14 2007/09/11 21:42:52 debug Exp $
 *  
 *  COMMENT: OpenPIC Interrupt controller (used by sandpoint ppc)
 *  based on dev_gc.c
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "cpu.h"
#include "device.h"
#include "machine.h"
#include "memory.h"
#include "misc.h"


#define DEV_OPENPIC_LENGTH              0x40000

struct openpic_data {
        struct interrupt cpu_irq;

        uint32_t        status_hi;
        uint32_t        status_lo;
        uint32_t        enable_hi;
        uint32_t        enable_lo;
};


void openpic_hi_interrupt_assert(struct interrupt *interrupt)
{
        struct openpic_data *d = interrupt->extra;
        d->status_hi |= interrupt->line;
        if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)
                INTERRUPT_ASSERT(d->cpu_irq);
}
void openpic_hi_interrupt_deassert(struct interrupt *interrupt)
{
        struct openpic_data *d = interrupt->extra;
        d->status_hi &= ~interrupt->line;
        if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi))
                INTERRUPT_DEASSERT(d->cpu_irq);
}
void openpic_lo_interrupt_assert(struct interrupt *interrupt)
{
        struct openpic_data *d = interrupt->extra;
        d->status_lo |= interrupt->line;
        if (d->status_lo & d->enable_lo || d->status_hi & d->enable_hi)
                INTERRUPT_ASSERT(d->cpu_irq);
}
void openpic_lo_interrupt_deassert(struct interrupt *interrupt)
{
        struct openpic_data *d = interrupt->extra;
        d->status_lo &= ~interrupt->line;
        if (!(d->status_lo & d->enable_lo || d->status_hi & d->enable_hi))
                INTERRUPT_DEASSERT(d->cpu_irq);
}


DEVICE_ACCESS(openpic)
{
//      struct openpic_data *d = extra;
        uint64_t idata = 0, odata = 0;

        if (writeflag == MEM_WRITE)
                idata = memory_readmax64(cpu, data, len);

        switch (relative_addr) {

        case 0x00:
                if (writeflag == MEM_READ)
                        // version 1.2
                        odata = 0x02000000;
                break;

#if 0
#define INT_STATE_REG_H  (interrupt_reg + 0x00)
#define INT_ENABLE_REG_H (interrupt_reg + 0x04)
#define INT_CLEAR_REG_H  (interrupt_reg + 0x08)
#define INT_LEVEL_REG_H  (interrupt_reg + 0x0c)
#define INT_STATE_REG_L  (interrupt_reg + 0x10)
#define INT_ENABLE_REG_L (interrupt_reg + 0x14)
#define INT_CLEAR_REG_L  (interrupt_reg + 0x18)
#define INT_LEVEL_REG_L  (interrupt_reg + 0x1c)
#endif

#if 0
        case 0x10:
                if (writeflag == MEM_READ)
                        odata = d->status_hi & d->enable_hi;
                break;

        case 0x14:
                if (writeflag == MEM_READ)
                        odata = d->enable_hi;
                else {
                        int old_assert = (d->status_lo & d->enable_lo
                            || d->status_hi & d->enable_hi);
                        int new_assert;
                        d->enable_hi = idata;

                        new_assert = (d->status_lo & d->enable_lo ||
                            d->status_hi & d->enable_hi);

                        if (old_assert && !new_assert)
                                INTERRUPT_DEASSERT(d->cpu_irq);
                        else if (!old_assert && new_assert)
                                INTERRUPT_ASSERT(d->cpu_irq);
                }
                break;

        case 0x18:
                if (writeflag == MEM_WRITE) {
                        int old_assert = (d->status_lo & d->enable_lo
                            || d->status_hi & d->enable_hi);
                        int new_assert;
                        d->status_hi &= ~idata;

                        new_assert = (d->status_lo & d->enable_lo ||
                            d->status_hi & d->enable_hi);

                        if (old_assert && !new_assert)
                                INTERRUPT_DEASSERT(d->cpu_irq);
                        else if (!old_assert && new_assert)
                                INTERRUPT_ASSERT(d->cpu_irq);
                }
                break;

        case 0x20:
                if (writeflag == MEM_READ)
                        odata = d->status_lo & d->enable_lo;
                break;

        case 0x24:
                if (writeflag == MEM_READ)
                        odata = d->enable_lo;
                else {
                        int old_assert = (d->status_lo & d->enable_lo
                            || d->status_hi & d->enable_hi);
                        int new_assert;
                        d->enable_lo = idata;

                        new_assert = (d->status_lo & d->enable_lo ||
                            d->status_hi & d->enable_hi);

                        if (old_assert && !new_assert)
                                INTERRUPT_DEASSERT(d->cpu_irq);
                        else if (!old_assert && new_assert)
                                INTERRUPT_ASSERT(d->cpu_irq);
                }
                break;

        case 0x28:
                if (writeflag == MEM_WRITE) {
                        int old_assert = (d->status_lo & d->enable_lo
                            || d->status_hi & d->enable_hi);
                        int new_assert;
                        d->status_lo &= ~idata;

                        new_assert = (d->status_lo & d->enable_lo ||
                            d->status_hi & d->enable_hi);

                        if (old_assert && !new_assert)
                                INTERRUPT_DEASSERT(d->cpu_irq);
                        else if (!old_assert && new_assert)
                                INTERRUPT_ASSERT(d->cpu_irq);
                }
                break;

        case 0x1c:
        case 0x2c:
                /*  Avoid a debug message.  */
                break;
#endif
        default:if (writeflag == MEM_WRITE) {
                        fatal("[ openpic: unimplemented write to "
                            "offset 0x%x: data=0x%x ]\n", (int)
                            relative_addr, (int)idata);
                } else {
                        fatal("[ openpic: unimplemented read from "
                            "offset 0x%x ]\n", (int)relative_addr);
                }
        }

        if (writeflag == MEM_READ)
                memory_writemax64(cpu, data, len, odata);

        return 1;
}


DEVINIT(openpic)
{
        struct openpic_data *d;
        int i;

        CHECK_ALLOCATION(d = malloc(sizeof(struct openpic_data)));
        memset(d, 0, sizeof(struct openpic_data));

        /*  Connect to the CPU interrupt pin:  */
        INTERRUPT_CONNECT(devinit->interrupt_path, d->cpu_irq);

        /*
         *  Register the 126 OpenPIC interrupts
         */
        for (i=0; i<126; i++) {
                struct interrupt template;
                char n[300];
                snprintf(n, sizeof(n), "%s.openpic.%i",
                    devinit->interrupt_path, i);
                memset(&template, 0, sizeof(template));
                template.line = 1 << i;
                template.name = n;
                template.extra = d;
                template.interrupt_assert = openpic_lo_interrupt_assert;
                template.interrupt_deassert = openpic_lo_interrupt_deassert;
                interrupt_handler_register(&template);
        }

        memory_device_register(devinit->machine->memory, "openpic",
            devinit->addr, DEV_OPENPIC_LENGTH, dev_openpic_access, d, DM_DEFAULT, NULL);

        return 1;
}

1	dpavlin	22	/*
2	dpavlin	34	* Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3	dpavlin	22	*
4			* Redistribution and use in source and binary forms, with or without
5			* modification, are permitted provided that the following conditions are met:
6			*
7			* 1. Redistributions of source code must retain the above copyright
8			* notice, this list of conditions and the following disclaimer.
9			* 2. Redistributions in binary form must reproduce the above copyright
10			* notice, this list of conditions and the following disclaimer in the
11			* documentation and/or other materials provided with the distribution.
12			* 3. The name of the author may not be used to endorse or promote products
13			* derived from this software without specific prior written permission.
14			*
15			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25			* SUCH DAMAGE.
26			*
27	dpavlin	63	* $Id: dev_openpic.c,v 1.14 2007/09/11 21:42:52 debug Exp $
28	dpavlin	22	*
29	dpavlin	63	* COMMENT: OpenPIC Interrupt controller (used by sandpoint ppc)
30	dpavlin	64	* based on dev_gc.c
31	dpavlin	22	*/
32
33			#include <stdio.h>
34			#include <stdlib.h>
35			#include <string.h>
36
37			#include "cpu.h"
38			#include "device.h"
39			#include "machine.h"
40			#include "memory.h"
41			#include "misc.h"
42
43
44	dpavlin	63	#define DEV_OPENPIC_LENGTH 0x40000
45	dpavlin	34
46	dpavlin	63	struct openpic_data {
47	dpavlin	34	struct interrupt cpu_irq;
48
49			uint32_t status_hi;
50			uint32_t status_lo;
51			uint32_t enable_hi;
52			uint32_t enable_lo;
53			};
54
55
56	dpavlin	63	void openpic_hi_interrupt_assert(struct interrupt *interrupt)
57	dpavlin	34	{
58	dpavlin	63	struct openpic_data *d = interrupt->extra;
59	dpavlin	34	d->status_hi \|= interrupt->line;
60			if (d->status_lo & d->enable_lo \|\| d->status_hi & d->enable_hi)
61			INTERRUPT_ASSERT(d->cpu_irq);
62			}
63	dpavlin	63	void openpic_hi_interrupt_deassert(struct interrupt *interrupt)
64	dpavlin	34	{
65	dpavlin	63	struct openpic_data *d = interrupt->extra;
66	dpavlin	34	d->status_hi &= ~interrupt->line;
67			if (!(d->status_lo & d->enable_lo \|\| d->status_hi & d->enable_hi))
68			INTERRUPT_DEASSERT(d->cpu_irq);
69			}
70	dpavlin	63	void openpic_lo_interrupt_assert(struct interrupt *interrupt)
71	dpavlin	34	{
72	dpavlin	63	struct openpic_data *d = interrupt->extra;
73	dpavlin	34	d->status_lo \|= interrupt->line;
74			if (d->status_lo & d->enable_lo \|\| d->status_hi & d->enable_hi)
75			INTERRUPT_ASSERT(d->cpu_irq);
76			}
77	dpavlin	63	void openpic_lo_interrupt_deassert(struct interrupt *interrupt)
78	dpavlin	34	{
79	dpavlin	63	struct openpic_data *d = interrupt->extra;
80	dpavlin	34	d->status_lo &= ~interrupt->line;
81			if (!(d->status_lo & d->enable_lo \|\| d->status_hi & d->enable_hi))
82			INTERRUPT_DEASSERT(d->cpu_irq);
83			}
84
85
86	dpavlin	63	DEVICE_ACCESS(openpic)
87	dpavlin	22	{
88	dpavlin	64	// struct openpic_data *d = extra;
89	dpavlin	22	uint64_t idata = 0, odata = 0;
90
91			if (writeflag == MEM_WRITE)
92			idata = memory_readmax64(cpu, data, len);
93
94			switch (relative_addr) {
95
96	dpavlin	65	case 0x00:
97			if (writeflag == MEM_READ)
98			// version 1.2
99			odata = 0x02000000;
100			break;
101
102	dpavlin	22	#if 0
103			#define INT_STATE_REG_H (interrupt_reg + 0x00)
104			#define INT_ENABLE_REG_H (interrupt_reg + 0x04)
105			#define INT_CLEAR_REG_H (interrupt_reg + 0x08)
106			#define INT_LEVEL_REG_H (interrupt_reg + 0x0c)
107			#define INT_STATE_REG_L (interrupt_reg + 0x10)
108			#define INT_ENABLE_REG_L (interrupt_reg + 0x14)
109			#define INT_CLEAR_REG_L (interrupt_reg + 0x18)
110			#define INT_LEVEL_REG_L (interrupt_reg + 0x1c)
111			#endif
112
113	dpavlin	64	#if 0
114	dpavlin	22	case 0x10:
115			if (writeflag == MEM_READ)
116	dpavlin	24	odata = d->status_hi & d->enable_hi;
117	dpavlin	22	break;
118
119			case 0x14:
120			if (writeflag == MEM_READ)
121			odata = d->enable_hi;
122			else {
123	dpavlin	34	int old_assert = (d->status_lo & d->enable_lo
124			\|\| d->status_hi & d->enable_hi);
125			int new_assert;
126	dpavlin	22	d->enable_hi = idata;
127	dpavlin	34
128			new_assert = (d->status_lo & d->enable_lo \|\|
129			d->status_hi & d->enable_hi);
130
131			if (old_assert && !new_assert)
132			INTERRUPT_DEASSERT(d->cpu_irq);
133			else if (!old_assert && new_assert)
134			INTERRUPT_ASSERT(d->cpu_irq);
135	dpavlin	22	}
136			break;
137
138			case 0x18:
139			if (writeflag == MEM_WRITE) {
140	dpavlin	34	int old_assert = (d->status_lo & d->enable_lo
141			\|\| d->status_hi & d->enable_hi);
142			int new_assert;
143	dpavlin	22	d->status_hi &= ~idata;
144	dpavlin	34
145			new_assert = (d->status_lo & d->enable_lo \|\|
146			d->status_hi & d->enable_hi);
147
148			if (old_assert && !new_assert)
149			INTERRUPT_DEASSERT(d->cpu_irq);
150			else if (!old_assert && new_assert)
151			INTERRUPT_ASSERT(d->cpu_irq);
152	dpavlin	22	}
153			break;
154
155			case 0x20:
156			if (writeflag == MEM_READ)
157	dpavlin	24	odata = d->status_lo & d->enable_lo;
158	dpavlin	22	break;
159
160			case 0x24:
161			if (writeflag == MEM_READ)
162			odata = d->enable_lo;
163			else {
164	dpavlin	34	int old_assert = (d->status_lo & d->enable_lo
165			\|\| d->status_hi & d->enable_hi);
166			int new_assert;
167	dpavlin	22	d->enable_lo = idata;
168	dpavlin	34
169			new_assert = (d->status_lo & d->enable_lo \|\|
170			d->status_hi & d->enable_hi);
171
172			if (old_assert && !new_assert)
173			INTERRUPT_DEASSERT(d->cpu_irq);
174			else if (!old_assert && new_assert)
175			INTERRUPT_ASSERT(d->cpu_irq);
176	dpavlin	22	}
177			break;
178
179			case 0x28:
180			if (writeflag == MEM_WRITE) {
181	dpavlin	34	int old_assert = (d->status_lo & d->enable_lo
182			\|\| d->status_hi & d->enable_hi);
183			int new_assert;
184	dpavlin	22	d->status_lo &= ~idata;
185	dpavlin	34
186			new_assert = (d->status_lo & d->enable_lo \|\|
187			d->status_hi & d->enable_hi);
188
189			if (old_assert && !new_assert)
190			INTERRUPT_DEASSERT(d->cpu_irq);
191			else if (!old_assert && new_assert)
192			INTERRUPT_ASSERT(d->cpu_irq);
193	dpavlin	22	}
194			break;
195
196	dpavlin	44	case 0x1c:
197	dpavlin	24	case 0x2c:
198	dpavlin	34	/* Avoid a debug message. */
199	dpavlin	24	break;
200	dpavlin	64	#endif
201	dpavlin	22	default:if (writeflag == MEM_WRITE) {
202	dpavlin	63	fatal("[ openpic: unimplemented write to "
203	dpavlin	22	"offset 0x%x: data=0x%x ]\n", (int)
204			relative_addr, (int)idata);
205			} else {
206	dpavlin	63	fatal("[ openpic: unimplemented read from "
207	dpavlin	22	"offset 0x%x ]\n", (int)relative_addr);
208			}
209			}
210
211			if (writeflag == MEM_READ)
212			memory_writemax64(cpu, data, len, odata);
213
214			return 1;
215			}
216
217
218	dpavlin	63	DEVINIT(openpic)
219	dpavlin	22	{
220	dpavlin	63	struct openpic_data *d;
221	dpavlin	34	int i;
222	dpavlin	22
223	dpavlin	63	CHECK_ALLOCATION(d = malloc(sizeof(struct openpic_data)));
224			memset(d, 0, sizeof(struct openpic_data));
225	dpavlin	22
226	dpavlin	42	/* Connect to the CPU interrupt pin: */
227	dpavlin	34	INTERRUPT_CONNECT(devinit->interrupt_path, d->cpu_irq);
228	dpavlin	22
229	dpavlin	34	/*
230	dpavlin	64	* Register the 126 OpenPIC interrupts
231	dpavlin	34	*/
232	dpavlin	64	for (i=0; i<126; i++) {
233	dpavlin	34	struct interrupt template;
234			char n[300];
235	dpavlin	64	snprintf(n, sizeof(n), "%s.openpic.%i",
236	dpavlin	34	devinit->interrupt_path, i);
237			memset(&template, 0, sizeof(template));
238			template.line = 1 << i;
239			template.name = n;
240			template.extra = d;
241	dpavlin	63	template.interrupt_assert = openpic_lo_interrupt_assert;
242			template.interrupt_deassert = openpic_lo_interrupt_deassert;
243	dpavlin	34	interrupt_handler_register(&template);
244			}
245
246	dpavlin	63	memory_device_register(devinit->machine->memory, "openpic",
247			devinit->addr, DEV_OPENPIC_LENGTH, dev_openpic_access, d, DM_DEFAULT, NULL);
248	dpavlin	34
249			return 1;
250	dpavlin	22	}
251