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/* |
/* |
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* Copyright (C) 2004-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2004-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: dev_ohci.c,v 1.8 2006/02/09 20:02:59 debug Exp $ |
* $Id: dev_ohci.c,v 1.10 2007/01/28 00:41:17 debug Exp $ |
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* |
* |
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* USB OHCI (Open Host Controller Interface). |
* USB OHCI (Open Host Controller Interface). |
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* |
* |
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#include "cpu.h" |
#include "cpu.h" |
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#include "device.h" |
#include "device.h" |
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#include "interrupt.h" |
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#include "machine.h" |
#include "machine.h" |
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#include "memory.h" |
#include "memory.h" |
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#include "misc.h" |
#include "misc.h" |
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struct ohci_data { |
struct ohci_data { |
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int irq_nr; |
struct interrupt irq; |
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int port1reset; |
int port1reset; |
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}; |
}; |
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name = "COMMAND_STATUS"; |
name = "COMMAND_STATUS"; |
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if (idata == 0x2) { |
if (idata == 0x2) { |
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fatal("URK\n"); |
fatal("URK\n"); |
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cpu_interrupt(cpu, d->irq_nr); |
INTERRUPT_ASSERT(d->irq); |
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} |
} |
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break; |
break; |
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case OHCI_INTERRUPT_STATUS: |
case OHCI_INTERRUPT_STATUS: |
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exit(1); |
exit(1); |
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} |
} |
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memset(d, 0, sizeof(struct ohci_data)); |
memset(d, 0, sizeof(struct ohci_data)); |
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d->irq_nr = devinit->irq_nr; |
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INTERRUPT_CONNECT(devinit->interrupt_path, d->irq); |
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memory_device_register(devinit->machine->memory, |
memory_device_register(devinit->machine->memory, |
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devinit->name, devinit->addr, |
devinit->name, devinit->addr, |