/[gxemul]/trunk/src/devices/dev_ns16550.c
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Contents of /trunk/src/devices/dev_ns16550.c

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Revision 32 - (show annotations)
Mon Oct 8 16:20:58 2007 UTC (11 years, 11 months ago) by dpavlin
File MIME type: text/plain
File size: 10480 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1421 2006/11/06 05:32:37 debug Exp $
20060816	Adding a framework for emulated/virtual timers (src/timer.c),
		using only setitimer().
		Rewriting the mc146818 to use the new timer framework.
20060817	Adding a call to gettimeofday() every now and then (once every
		second, at the moment) to resynch the timer if it drifts.
		Beginning to convert the ISA timer interrupt mechanism (8253
		and 8259) to use the new timer framework.
		Removing the -I command line option.
20060819	Adding the -I command line option again, with new semantics.
		Working on Footbridge timer interrupts; NetBSD/NetWinder and
		NetBSD/CATS now run at correct speed, but unfortunately with
		HUGE delays during bootup.
20060821	Some minor m68k updates. Adding the first instruction: nop. :)
		Minor Alpha emulation updates.
20060822	Adding a FreeBSD development specific YAMON environment
		variable ("khz") (as suggested by Bruce M. Simpson).
		Moving YAMON environment variable initialization from
		machine_evbmips.c into promemul/yamon.c, and adding some more
		variables.
		Continuing on the LCA PCI bus controller (for Alpha machines).
20060823	Continuing on the timer stuff: experimenting with MIPS count/
		compare interrupts connected to the timer framework.
20060825	Adding bogus SCSI commands 0x51 (SCSICDROM_READ_DISCINFO) and
		0x52 (SCSICDROM_READ_TRACKINFO) to the SCSI emulation layer,
		to allow NetBSD/pmax 4.0_BETA to be installed from CDROM.
		Minor updates to the LCA PCI controller.
20060827	Implementing a CHIP8 cpu mode, and a corresponding CHIP8
		machine, for fun. Disassembly support for all instructions,
		and most of the common instructions have been implemented: mvi,
		mov_imm, add_imm, jmp, rand, cls, sprite, skeq_imm, jsr,
		skne_imm, bcd, rts, ldr, str, mov, or, and, xor, add, sub,
		font, ssound, sdelay, gdelay, bogus skup/skpr, skeq, skne.
20060828	Beginning to convert the CHIP8 cpu in the CHIP8 machine to a
		(more correct) RCA 180x cpu. (Disassembly for all 1802
		instructions has been implemented, but no execution yet, and
		no 1805 extended instructions.)
20060829	Minor Alpha emulation updates.
20060830	Beginning to experiment a little with PCI IDE for SGI O2.
		Fixing the cursor key mappings for MobilePro 770 emulation.
		Fixing the LK201 warning caused by recent NetBSD/pmax.
		The MIPS R41xx standby, suspend, and hibernate instructions now
		behave like the RM52xx/MIPS32/MIPS64 wait instruction.
		Fixing dev_wdc so it calculates correct (64-bit) offsets before
		giving them to diskimage_access().
20060831	Continuing on Alpha emulation (OSF1 PALcode).
20060901	Minor Alpha updates; beginning on virtual memory pagetables.
		Removed the limit for max nr of devices (in preparation for
		allowing devices' base addresses to be changed during runtime).
		Adding a hack for MIPS [d]mfc0 select 0 (except the count
		register), so that the coproc register is simply copied.
		The MIPS suspend instruction now exits the emulator, instead
		of being treated as a wait instruction (this causes NetBSD/
		hpcmips to get correct 'halt' behavior).
		The VR41xx RTC now returns correct time.
		Connecting the VR41xx timer to the timer framework (fixed at
		128 Hz, for now).
		Continuing on SPARC emulation, adding more instructions:
		restore, ba_xcc, ble. The rectangle drawing demo works :)
		Removing the last traces of the old ENABLE_CACHE_EMULATION
		MIPS stuff (not usable with dyntrans anyway).
20060902	Splitting up src/net.c into several smaller files in its own
		subdirectory (src/net/).
20060903	Cleanup of the files in src/net/, to make them less ugly.
20060904	Continuing on the 'settings' subsystem.
		Minor progress on the SPARC emulation mode.
20060905	Cleanup of various things, and connecting the settings
		infrastructure to various subsystems (emul, machine, cpu, etc).
		Changing the lk201 mouse update routine to not rely on any
		emulated hardware framebuffer cursor coordinates, but instead
		always do (semi-usable) relative movements.
20060906	Continuing on the lk201 mouse stuff. Mouse behaviour with
		multiple framebuffers (which was working in Ultrix) is now
		semi-broken (but it still works, in a way).
		Moving the documentation about networking into its own file
		(networking.html), and refreshing it a bit. Adding an example
		of how to use ethernet frame direct-access (udp_snoop).
20060907	Continuing on the settings infrastructure.
20060908	Minor updates to SH emulation: for 32-bit emulation: delay
		slots and the 'jsr @Rn' instruction. I'm putting 64-bit SH5 on
		ice, for now.
20060909-10	Implementing some more 32-bit SH instructions. Removing the
		64-bit mode completely. Enough has now been implemented to run
		the rectangle drawing demo. :-)
20060912	Adding more SH instructions.
20060916	Continuing on SH emulation (some more instructions: div0u,
		div1, rotcl/rotcr, more mov instructions, dt, braf, sets, sett,
		tst_imm, dmuls.l, subc, ldc_rm_vbr, movt, clrt, clrs, clrmac).
		Continuing on the settings subsystem (beginning on reading/
		writing settings, removing bugs, and connecting more cpus to
		the framework).
20060919	More work on SH emulation; adding an ldc banked instruction,
		and attaching a 640x480 framebuffer to the Dreamcast machine
		mode (NetBSD/dreamcast prints the NetBSD copyright banner :-),
		and then panics).
20060920	Continuing on the settings subsystem.
20060921	Fixing the Footbridge timer stuff so that NetBSD/cats and
		NetBSD/netwinder boot up without the delays.
20060922	Temporarily hardcoding MIPS timer interrupt to 100 Hz. With
		'wait' support disabled, NetBSD/malta and Linux/malta run at
		correct speed.
20060923	Connecting dev_gt to the timer framework, so that NetBSD/cobalt
		runs at correct speed.
		Moving SH4-specific memory mapped registers into its own
		device (dev_sh4.c).
		Running with -N now prints "idling" instead of bogus nr of
		instrs/second (which isn't valid anyway) while idling.
20060924	Algor emulation should now run at correct speed.
		Adding disassembly support for some MIPS64 revision 2
		instructions: ext, dext, dextm, dextu.
20060926	The timer framework now works also when the MIPS wait
		instruction is used.
20060928	Re-implementing checks for coprocessor availability for MIPS
		cop0 instructions. (Thanks to Carl van Schaik for noticing the
		lack of cop0 availability checks.)
20060929	Implementing an instruction combination hack which treats
		NetBSD/pmax' idle loop as a wait-like instruction.
20060930	The ENTRYHI_R_MASK was missing in (at least) memory_mips_v2p.c,
		causing TLB lookups to sometimes succeed when they should have
		failed. (A big thank you to Juli Mallett for noticing the
		problem.)
		Adding disassembly support for more MIPS64 revision 2 opcodes
		(seb, seh, wsbh, jalr.hb, jr.hb, synci, ins, dins, dinsu,
		dinsm, dsbh, dshd, ror, dror, rorv, drorv, dror32). Also
		implementing seb, seh, dsbh, dshd, and wsbh.
		Implementing an instruction combination hack for Linux/pmax'
		idle loop, similar to the NetBSD/pmax case.
20061001	Changing the NetBSD/sgimips install instructions to extract
		files from an iso image, instead of downloading them via ftp.
20061002	More-than-31-bit userland addresses in memory_mips_v2p.c were
		not actually working; applying a fix from Carl van Schaik to
		enable them to work + making some other updates (adding kuseg
		support).
		Fixing hpcmips (vr41xx) timer initialization.
		Experimenting with O(n)->O(1) reduction in the MIPS TLB lookup
		loop. Seems to work both for R3000 and non-R3000.
20061003	Continuing a little on SH emulation (adding more control
		registers; mini-cleanup of memory_sh.c).
20061004	Beginning on a dev_rtc, a clock/timer device for the test
		machines; also adding a demo, and some documentation.
		Fixing a bug in SH "mov.w @(disp,pc),Rn" (the result wasn't
		sign-extended), and adding the addc and ldtlb instructions.
20061005	Contining on SH emulation: virtual to physical address
		translation, and a skeleton exception mechanism.
20061006	Adding more SH instructions (various loads and stores, rte,
		negc, muls.w, various privileged register-move instructions).
20061007	More SH instructions: various move instructions, trapa, div0s,
		float, fdiv, ftrc.
		Continuing on dev_rtc; removing the rtc demo.
20061008	Adding a dummy Dreamcast PROM module. (Homebrew Dreamcast
		programs using KOS libs need this.)
		Adding more SH instructions: "stc vbr,rn", rotl, rotr, fsca,
		fmul, fadd, various floating-point moves, etc. A 256-byte
		demo for Dreamcast runs :-)
20061012	Adding the SH "lds Rm,pr" and bsr instructions.
20061013	More SH instructions: "sts fpscr,rn", tas.b, and some more
		floating point instructions, cmp/str, and more moves.
		Adding a dummy dev_pvr (Dreamcast graphics controller).
20061014	Generalizing the expression evaluator (used in the built-in
		debugger) to support parentheses and +-*/%^&|.
20061015	Removing the experimental tlb index hint code in
		mips_memory_v2p.c, since it didn't really have any effect.
20061017	Minor SH updates; adding the "sts pr,Rn", fcmp/gt, fneg,
		frchg, and some other instructions. Fixing missing sign-
		extension in an 8-bit load instruction.
20061019	Adding a simple dev_dreamcast_rtc.
		Implementing memory-mapped access to the SH ITLB/UTLB arrays.
20061021	Continuing on various SH and Dreamcast things: sh4 timers,
		debug messages for dev_pvr, fixing some virtual address
		translation bugs, adding the bsrf instruction.
		The NetBSD/dreamcast GENERIC_MD kernel now reaches userland :)
		Adding a dummy dev_dreamcast_asic.c (not really useful yet).
		Implementing simple support for Store Queues.
		Beginning on the PVR Tile Accelerator.
20061022	Generalizing the PVR framebuffer to support off-screen drawing,
		multiple bit-depths, etc. (A small speed penalty, but most
		likely worth it.)
		Adding more SH instructions (mulu.w, fcmp/eq, fsub, fmac,
		fschg, and some more); correcting bugs in "fsca" and "float".
20061024	Adding the SH ftrv (matrix * vector) instruction. Marcus
		Comstedt's "tatest" example runs :) (wireframe only).
		Correcting disassembly for SH floating point instructions that
		use the xd* registers.
		Adding the SH fsts instruction.
		In memory_device_dyntrans_access(), only the currently used
		range is now invalidated, and not the entire device range.
20061025	Adding a dummy AVR32 cpu mode skeleton.
20061026	Various Dreamcast updates; beginning on a Maple bus controller.
20061027	Continuing on the Maple bus. A bogus Controller, Keyboard, and
		Mouse can now be detected by NetBSD and KOS homebrew programs.
		Cleaning up the SH4 Timer Management Unit, and beginning on
		SH4 interrupts.
		Implementing the Dreamcast SYSASIC.
20061028	Continuing on the SYSASIC.
		Adding the SH fsqrt instruction.
		memory_sh.c now actually scans the ITLB.
		Fixing a bug in dev_sh4.c, related to associative writes into
		the memory-mapped UTLB array. NetBSD/dreamcast now reaches
		userland stably, and prints the "Terminal type?" message :-]
		Implementing enough of the Dreamcast keyboard to make NetBSD
		accept it for input.
		Enabling SuperH for stable (non-development) builds.
		Adding NetBSD/dreamcast to the documentation, although it
		doesn't support root-on-nfs yet.
20061029	Changing usleep(1) calls in the debugger to to usleep(10000)
		(according to Brian Foley, this makes GXemul run better on
		MacOS X).
		Making the Maple "Controller" do something (enough to barely
		interact with dcircus.elf).
20061030-31	Some progress on the PVR. More test programs start running (but
		with strange output).
		Various other SH4-related updates.
20061102	Various Dreamcast and SH4 updates; more KOS demos run now.
20061104	Adding a skeleton dev_mb8696x.c (the Dreamcast's LAN adapter).
20061105	Continuing on the MB8696x; NetBSD/dreamcast detects it as mbe0.
		Testing for the release.

==============  RELEASE 0.4.3  ==============


1 /*
2 * Copyright (C) 2003-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_ns16550.c,v 1.55 2006/10/27 13:12:21 debug Exp $
29 *
30 * NS16550 serial controller.
31 *
32 *
33 * TODO: Implement the FIFO.
34 */
35
36 #include <stdio.h>
37 #include <stdlib.h>
38 #include <string.h>
39
40 #include "console.h"
41 #include "cpu.h"
42 #include "device.h"
43 #include "machine.h"
44 #include "memory.h"
45 #include "misc.h"
46
47 #include "comreg.h"
48
49
50 /* #define debug fatal */
51
52 #define TICK_SHIFT 14
53 #define DEV_NS16550_LENGTH 8
54
55 struct ns_data {
56 int addrmult;
57 int in_use;
58 int irqnr;
59 char *name;
60 int console_handle;
61 int enable_fifo;
62
63 unsigned char reg[DEV_NS16550_LENGTH];
64 unsigned char fcr; /* FIFO control register */
65 int int_asserted;
66 int dlab; /* Divisor Latch Access bit */
67 int divisor;
68
69 int databits;
70 char parity;
71 const char *stopbits;
72 };
73
74
75 DEVICE_TICK(ns16550)
76 {
77 /*
78 * This function is called at regular intervals. An interrupt is
79 * asserted if there is a character available for reading, or if the
80 * transmitter slot is empty (i.e. the ns16550 is ready to transmit).
81 */
82 struct ns_data *d = extra;
83
84 d->reg[com_iir] &= ~IIR_RXRDY;
85 if (console_charavail(d->console_handle))
86 d->reg[com_iir] |= IIR_RXRDY;
87
88 /*
89 * If interrupts are enabled, and interrupts are pending, then
90 * cause a CPU interrupt.
91 */
92
93 if (((d->reg[com_ier] & IER_ETXRDY) && (d->reg[com_iir] & IIR_TXRDY)) ||
94 ((d->reg[com_ier] & IER_ERXRDY) && (d->reg[com_iir] & IIR_RXRDY))) {
95 d->reg[com_iir] &= ~IIR_NOPEND;
96 if (d->reg[com_mcr] & MCR_IENABLE) {
97 cpu_interrupt(cpu, d->irqnr);
98 d->int_asserted = 1;
99 }
100 } else {
101 d->reg[com_iir] |= IIR_NOPEND;
102 if (d->int_asserted)
103 cpu_interrupt_ack(cpu, d->irqnr);
104 d->int_asserted = 0;
105 }
106 }
107
108
109 /*
110 * dev_ns16550_access():
111 */
112 DEVICE_ACCESS(ns16550)
113 {
114 uint64_t idata = 0, odata=0;
115 size_t i;
116 struct ns_data *d = extra;
117
118 if (writeflag == MEM_WRITE)
119 idata = memory_readmax64(cpu, data, len);
120
121 #if 0
122 /* The NS16550 should be accessed using byte read/writes: */
123 if (len != 1)
124 fatal("[ ns16550 (%s): len=%i, idata=0x%16llx! ]\n",
125 d->name, len, (long long)idata);
126 #endif
127
128 /*
129 * Always ready to transmit:
130 */
131 d->reg[com_lsr] |= LSR_TXRDY | LSR_TSRE;
132 d->reg[com_msr] |= MSR_DCD | MSR_DSR | MSR_CTS;
133
134 d->reg[com_iir] &= ~0xf0;
135 if (d->enable_fifo)
136 d->reg[com_iir] |= ((d->fcr << 5) & 0xc0);
137
138 d->reg[com_lsr] &= ~LSR_RXRDY;
139 if (console_charavail(d->console_handle))
140 d->reg[com_lsr] |= LSR_RXRDY;
141
142 relative_addr /= d->addrmult;
143
144 if (relative_addr >= DEV_NS16550_LENGTH) {
145 fatal("[ ns16550 (%s): outside register space? relative_addr="
146 "0x%llx. bad addrmult? bad device length? ]\n", d->name,
147 (long long)relative_addr);
148 return 0;
149 }
150
151 switch (relative_addr) {
152
153 case com_data: /* data AND low byte of the divisor */
154 /* Read/write of the Divisor value: */
155 if (d->dlab) {
156 /* Write or read the low byte of the divisor: */
157 if (writeflag == MEM_WRITE)
158 d->divisor = (d->divisor & 0xff00) | idata;
159 else
160 odata = d->divisor & 0xff;
161 break;
162 }
163
164 /* Read/write of data: */
165 if (writeflag == MEM_WRITE) {
166 if (d->reg[com_mcr] & MCR_LOOPBACK)
167 console_makeavail(d->console_handle, idata);
168 else
169 console_putchar(d->console_handle, idata);
170 d->reg[com_iir] |= IIR_TXRDY;
171 } else {
172 int x = console_readchar(d->console_handle);
173 odata = x < 0? 0 : x;
174 }
175 dev_ns16550_tick(cpu, d);
176 break;
177
178 case com_ier: /* interrupt enable AND high byte of the divisor */
179 /* Read/write of the Divisor value: */
180 if (d->dlab) {
181 if (writeflag == MEM_WRITE) {
182 /* Set the high byte of the divisor: */
183 d->divisor = (d->divisor & 0xff) | (idata << 8);
184 debug("[ ns16550 (%s): speed set to %i bps ]\n",
185 d->name, (int)(115200 / d->divisor));
186 } else
187 odata = d->divisor >> 8;
188 break;
189 }
190
191 /* IER: */
192 if (writeflag == MEM_WRITE) {
193 /* This is to supress Linux' behaviour */
194 if (idata != 0)
195 debug("[ ns16550 (%s): write to ier: 0x%02x ]"
196 "\n", d->name, (int)idata);
197
198 /* Needed for NetBSD 2.0.x, but not 1.6.2? */
199 if (!(d->reg[com_ier] & IER_ETXRDY)
200 && (idata & IER_ETXRDY))
201 d->reg[com_iir] |= IIR_TXRDY;
202
203 d->reg[com_ier] = idata;
204 dev_ns16550_tick(cpu, d);
205 } else
206 odata = d->reg[com_ier];
207 break;
208
209 case com_iir: /* interrupt identification (r), fifo control (w) */
210 if (writeflag == MEM_WRITE) {
211 debug("[ ns16550 (%s): write to fifo control: 0x%02x ]"
212 "\n", d->name, (int)idata);
213 d->fcr = idata;
214 } else {
215 odata = d->reg[com_iir];
216 if (d->reg[com_iir] & IIR_TXRDY)
217 d->reg[com_iir] &= ~IIR_TXRDY;
218 debug("[ ns16550 (%s): read from iir: 0x%02x ]\n",
219 d->name, (int)odata);
220 dev_ns16550_tick(cpu, d);
221 }
222 break;
223
224 case com_lsr:
225 if (writeflag == MEM_WRITE) {
226 debug("[ ns16550 (%s): write to lsr: 0x%02x ]\n",
227 d->name, (int)idata);
228 d->reg[com_lsr] = idata;
229 } else {
230 odata = d->reg[com_lsr];
231 /* debug("[ ns16550 (%s): read from lsr: 0x%02x ]\n",
232 d->name, (int)odata); */
233 }
234 break;
235
236 case com_msr:
237 if (writeflag == MEM_WRITE) {
238 debug("[ ns16550 (%s): write to msr: 0x%02x ]\n",
239 d->name, (int)idata);
240 d->reg[com_msr] = idata;
241 } else {
242 odata = d->reg[com_msr];
243 debug("[ ns16550 (%s): read from msr: 0x%02x ]\n",
244 d->name, (int)odata);
245 }
246 break;
247
248 case com_lctl:
249 if (writeflag == MEM_WRITE) {
250 d->reg[com_lctl] = idata;
251 switch (idata & 0x7) {
252 case 0: d->databits = 5; d->stopbits = "1"; break;
253 case 1: d->databits = 6; d->stopbits = "1"; break;
254 case 2: d->databits = 7; d->stopbits = "1"; break;
255 case 3: d->databits = 8; d->stopbits = "1"; break;
256 case 4: d->databits = 5; d->stopbits = "1.5"; break;
257 case 5: d->databits = 6; d->stopbits = "2"; break;
258 case 6: d->databits = 7; d->stopbits = "2"; break;
259 case 7: d->databits = 8; d->stopbits = "2"; break;
260 }
261 switch ((idata & 0x38) / 0x8) {
262 case 0: d->parity = 'N'; break; /* none */
263 case 1: d->parity = 'O'; break; /* odd */
264 case 2: d->parity = '?'; break;
265 case 3: d->parity = 'E'; break; /* even */
266 case 4: d->parity = '?'; break;
267 case 5: d->parity = 'Z'; break; /* zero */
268 case 6: d->parity = '?'; break;
269 case 7: d->parity = 'o'; break; /* one */
270 }
271
272 d->dlab = idata & 0x80? 1 : 0;
273
274 debug("[ ns16550 (%s): write to lctl: 0x%02x (%s%s"
275 "setting mode %i%c%s) ]\n", d->name, (int)idata,
276 d->dlab? "Divisor Latch access, " : "",
277 idata&0x40? "sending BREAK, " : "",
278 d->databits, d->parity, d->stopbits);
279 } else {
280 odata = d->reg[com_lctl];
281 debug("[ ns16550 (%s): read from lctl: 0x%02x ]\n",
282 d->name, (int)odata);
283 }
284 break;
285
286 case com_mcr:
287 if (writeflag == MEM_WRITE) {
288 d->reg[com_mcr] = idata;
289 debug("[ ns16550 (%s): write to mcr: 0x%02x ]\n",
290 d->name, (int)idata);
291 if (!(d->reg[com_iir] & IIR_TXRDY)
292 && (idata & MCR_IENABLE))
293 d->reg[com_iir] |= IIR_TXRDY;
294 dev_ns16550_tick(cpu, d);
295 } else {
296 odata = d->reg[com_mcr];
297 debug("[ ns16550 (%s): read from mcr: 0x%02x ]\n",
298 d->name, (int)odata);
299 }
300 break;
301
302 default:
303 if (writeflag==MEM_READ) {
304 debug("[ ns16550 (%s): read from reg %i ]\n",
305 d->name, (int)relative_addr);
306 odata = d->reg[relative_addr];
307 } else {
308 debug("[ ns16550 (%s): write to reg %i:",
309 d->name, (int)relative_addr);
310 for (i=0; i<len; i++)
311 debug(" %02x", data[i]);
312 debug(" ]\n");
313 d->reg[relative_addr] = idata;
314 }
315 }
316
317 if (writeflag == MEM_READ)
318 memory_writemax64(cpu, data, len, odata);
319
320 return 1;
321 }
322
323
324 DEVINIT(ns16550)
325 {
326 struct ns_data *d = malloc(sizeof(struct ns_data));
327 size_t nlen;
328 char *name;
329
330 if (d == NULL) {
331 fprintf(stderr, "out of memory\n");
332 exit(1);
333 }
334 memset(d, 0, sizeof(struct ns_data));
335 d->irqnr = devinit->irq_nr;
336 d->addrmult = devinit->addr_mult;
337 d->in_use = devinit->in_use;
338 d->enable_fifo = 1;
339 d->dlab = 0;
340 d->divisor = 115200 / 9600;
341 d->databits = 8;
342 d->parity = 'N';
343 d->stopbits = "1";
344 d->name = devinit->name2 != NULL? devinit->name2 : "";
345 d->console_handle =
346 console_start_slave(devinit->machine, devinit->name2 != NULL?
347 devinit->name2 : devinit->name, d->in_use);
348
349 nlen = strlen(devinit->name) + 10;
350 if (devinit->name2 != NULL)
351 nlen += strlen(devinit->name2);
352 name = malloc(nlen);
353 if (name == NULL) {
354 fprintf(stderr, "out of memory\n");
355 exit(1);
356 }
357 if (devinit->name2 != NULL && devinit->name2[0])
358 snprintf(name, nlen, "%s [%s]", devinit->name, devinit->name2);
359 else
360 snprintf(name, nlen, "%s", devinit->name);
361
362 memory_device_register(devinit->machine->memory, name, devinit->addr,
363 DEV_NS16550_LENGTH * d->addrmult, dev_ns16550_access, d,
364 DM_DEFAULT, NULL);
365 machine_add_tickfunction(devinit->machine,
366 dev_ns16550_tick, d, TICK_SHIFT, 0.0);
367
368 /*
369 * NOTE: Ugly cast into a pointer, because this is a convenient way
370 * to return the console handle to code in src/machine.c.
371 */
372 devinit->return_ptr = (void *)(size_t)d->console_handle;
373
374 return 1;
375 }
376

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