/[gxemul]/trunk/src/devices/dev_ns16550.c
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Contents of /trunk/src/devices/dev_ns16550.c

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Revision 12 - (show annotations)
Mon Oct 8 16:18:38 2007 UTC (12 years, 2 months ago) by dpavlin
File MIME type: text/plain
File size: 10108 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.905 2005/08/16 09:16:24 debug Exp $
20050628	Continuing the work on the ARM translation engine. end_of_page
		works. Experimenting with load/store translation caches
		(virtual -> physical -> host).
20050629	More ARM stuff (memory access translation cache, mostly). This
		might break a lot of stuff elsewhere, probably some MIPS-
		related translation things.
20050630	Many load/stores are now automatically generated and included
		into cpu_arm_instr.c; 1024 functions in total (!).
		Fixes based on feedback from Alec Voropay: only print 8 hex
		digits instead of 16 in some cases when emulating 32-bit
		machines; similar 8 vs 16 digit fix for breakpoint addresses;
		4Kc has 16 TLB entries, not 48; the MIPS config select1
		register is now printed with "reg ,0".
		Also changing many other occurances of 16 vs 8 digit output.
		Adding cache associativity fields to mips_cpu_types.h; updating
		some other cache fields; making the output of
		mips_cpu_dumpinfo() look nicer.
		Generalizing the bintrans stuff for device accesses to also
		work with the new translation system. (This might also break
		some MIPS things.)
		Adding multi-load/store instructions to the ARM disassembler
		and the translator, and some optimizations of various kinds.
20050701	Adding a simple dev_disk (it can read/write sectors from
		disk images).
20050712	Adding dev_ether (a simple ethernet send/receive device).
		Debugger command "ninstrs" for toggling show_nr_of_instructions
		during runtime.
		Removing the framebuffer logo.
20050713	Continuing on dev_ether.
		Adding a dummy cpu_alpha (again).
20050714	More work on cpu_alpha.
20050715	More work on cpu_alpha. Many instructions work, enough to run
		a simple framebuffer fill test (similar to the ARM test).
20050716	More Alpha stuff.
20050717	Minor updates (Alpha stuff).
20050718	Minor updates (Alpha stuff).
20050719	Generalizing some Alpha instructions.
20050720	More Alpha-related updates.
20050721	Continuing on cpu_alpha. Importing rpb.h from NetBSD/alpha.
20050722	Alpha-related updates: userland stuff (Hello World using
		write() compiled statically for FreeBSD/Alpha runs fine), and
		more instructions are now implemented.
20050723	Fixing ldq_u and stq_u.
		Adding more instructions (conditional moves, masks, extracts,
		shifts).
20050724	More FreeBSD/Alpha userland stuff, and adding some more
		instructions (inserts).
20050725	Continuing on the Alpha stuff. (Adding dummy ldt/stt.)
		Adding a -A command line option to turn off alignment checks
		in some cases (for translated code).
		Trying to remove the old bintrans code which updated the pc
		and nr_of_executed_instructions for every instruction.
20050726	Making another attempt att removing the pc/nr of instructions
		code. This time it worked, huge performance increase for
		artificial test code, but performance loss for real-world
		code :-( so I'm scrapping that code for now.
		Tiny performance increase on Alpha (by using ret instead of
		jmp, to play nice with the Alpha's branch prediction) for the
		old MIPS bintrans backend.
20050727	Various minor fixes and cleanups.
20050728	Switching from a 2-level virtual to host/physical translation
		system for ARM emulation, to a 1-level translation.
		Trying to switch from 2-level to 1-level for the MIPS bintrans
		system as well (Alpha only, so far), but there is at least one
		problem: caches and/or how they work with device mappings.
20050730	Doing the 2-level to 1-level conversion for the i386 backend.
		The cache/device bug is still there for R2K/3K :(
		Various other minor updates (Malta etc).
		The mc146818 clock now updates the UIP bit in a way which works
		better with Linux for at least sgimips and Malta emulation.
		Beginning the work on refactoring the dyntrans system.
20050731	Continuing the dyntrans refactoring.
		Fixing a small but serious host alignment bug in memory_rw.
		Adding support for big-endian load/stores to the i386 bintrans
		backend.
		Another minor i386 bintrans backend update: stores from the
		zero register are now one (or two) loads shorter.
		The slt and sltu instructions were incorrectly implemented for
		the i386 backend; only using them for 32-bit mode for now.
20050801	Continuing the dyntrans refactoring.
		Cleanup of the ns16550 serial controller (removing unnecessary
		code).
		Bugfix (memory corruption bug) in dev_gt, and a patch/hack from
		Alec Voropay for Linux/Malta.
20050802	More cleanup/refactoring of the dyntrans subsystem: adding
		phys_page pointers to the lookup tables, for quick jumps
		between translated pages.
		Better fix for the ns16550 device (but still no real FIFO
		functionality).
		Converting cpu_ppc to the new dyntrans system. This means that
		I will have to start from scratch with implementing each
		instruction, and figure out how to implement dual 64/32-bit
		modes etc.
		Removing the URISC CPU family, because it was useless.
20050803	When selecting a machine type, the main type can now be omitted
		if the subtype name is unique. (I.e. -E can be omitted.)
		Fixing a dyntrans/device update bug. (Writes to offset 0 of
		a device could sometimes go unnoticed.)
		Adding an experimental "instruction combination" hack for
		ARM for memset-like byte fill loops.
20050804	Minor progress on cpu_alpha and related things.
		Finally fixing the MIPS dmult/dmultu bugs.
		Fixing some minor TODOs.
20050805	Generalizing the 8259 PIC. It now also works with Cobalt
		and evbmips emulation, in addition to the x86 hack.
		Finally converting the ns16550 device to use devinit.
		Continuing the work on the dyntrans system. Thinking about
		how to add breakpoints.
20050806	More dyntrans updates. Breakpoints seem to work now.
20050807	Minor updates: cpu_alpha and related things; removing
		dev_malta (as it isn't used any more).
		Dyntrans: working on general "show trace tree" support.
		The trace tree stuff now works with both the old MIPS code and
		with newer dyntrans modes. :)
		Continuing on Alpha-related stuff (trying to get *BSD to boot
		a bit further, adding more instructions, etc).
20050808	Adding a dummy IA64 cpu family, and continuing the refactoring
		of the dyntrans system.
		Removing the regression test stuff, because it was more or
		less useless.
		Adding loadlinked/storeconditional type instructions to the
		Alpha emulation. (Needed for Linux/alpha. Not very well tested
		yet.)
20050809	The function call trace tree now prints a per-function nr of
		arguments. (Semi-meaningless, since that data isn't read yet
		from the ELFs; some hardcoded symbols such as memcpy() and
		strlen() work fine, though.)
		More dyntrans refactoring; taking out more of the things that
		are common to all cpu families.
20050810	Working on adding support for "dual mode" for PPC dyntrans
		(i.e. both 64-bit and 32-bit modes).
		(Re)adding some simple PPC instructions.
20050811	Adding a dummy M68K cpu family. The dyntrans system isn't ready
		for variable-length ISAs yet, so it's completely bogus so far.
		Re-adding more PPC instructions.
		Adding a hack to src/file.c which allows OpenBSD/mac68k a.out
		kernels to be loaded.
		Beginning to add PPC loads/stores. So far they only work in
		32-bit mode.
20050812	The configure file option "add_remote" now accepts symbolic
		host names, in addition to numeric IPv4 addresses.
		Re-adding more PPC instructions.
20050814	Continuing to port back more PPC instructions.
		Found and fixed the cache/device write-update bug for 32-bit
		MIPS bintrans. :-)
		Triggered a really weird and annoying bug in Compaq's C
		compiler; ccc sometimes outputs code which loads from an
		address _before_ checking whether the pointer was NULL or not.
		(I'm not sure how to handle this problem.)
20050815	Removing all of the old x86 instruction execution code; adding
		a new (dummy) dyntrans module for x86.
		Taking the first steps to extend the dyntrans system to support
		variable-length instructions.
		Slowly preparing for the next release.
20050816	Adding a dummy SPARC cpu module.
		Minor updates (documentation etc) for the release.

==============  RELEASE 0.3.5  ==============


1 /*
2 * Copyright (C) 2003-2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_ns16550.c,v 1.40 2005/08/12 06:15:31 debug Exp $
29 *
30 * NS16550 serial controller.
31 *
32 *
33 * TODO: Implement the FIFO.
34 */
35
36 #include <stdio.h>
37 #include <stdlib.h>
38 #include <string.h>
39
40 #include "console.h"
41 #include "cpu.h"
42 #include "device.h"
43 #include "machine.h"
44 #include "memory.h"
45 #include "misc.h"
46
47 #include "comreg.h"
48
49
50 /* #define debug fatal */
51
52 #define TICK_SHIFT 14
53 #define DEV_NS16550_LENGTH 8
54
55 struct ns_data {
56 int addrmult;
57 int in_use;
58 int irqnr;
59 int console_handle;
60 int enable_fifo;
61
62 unsigned char reg[DEV_NS16550_LENGTH];
63 unsigned char fcr; /* FIFO control register */
64
65 int dlab; /* Divisor Latch Access bit */
66 int divisor;
67
68 int databits;
69 char parity;
70 const char *stopbits;
71 };
72
73
74 /*
75 * dev_ns16550_tick():
76 *
77 * This function is called at regular intervals. An interrupt is caused to the
78 * CPU if there is a character available for reading, or if the transmitter
79 * slot is empty (i.e. the ns16550 is ready to transmit).
80 */
81 void dev_ns16550_tick(struct cpu *cpu, void *extra)
82 {
83 struct ns_data *d = extra;
84
85 d->reg[com_iir] &= ~IIR_RXRDY;
86 if (d->in_use && console_charavail(d->console_handle))
87 d->reg[com_iir] |= IIR_RXRDY;
88
89 /*
90 * If interrupts are enabled, and interrupts are pending, then
91 * cause a CPU interrupt.
92 */
93 if (((d->reg[com_ier] & IER_ETXRDY) && (d->reg[com_iir] & IIR_TXRDY)) ||
94 ((d->reg[com_ier] & IER_ERXRDY) && (d->reg[com_iir] & IIR_RXRDY))) {
95 d->reg[com_iir] &= ~IIR_NOPEND;
96 if (d->reg[com_mcr] & MCR_IENABLE)
97 cpu_interrupt(cpu, d->irqnr);
98 } else {
99 d->reg[com_iir] |= IIR_NOPEND;
100 cpu_interrupt_ack(cpu, d->irqnr);
101 }
102 }
103
104
105 /*
106 * dev_ns16550_access():
107 */
108 int dev_ns16550_access(struct cpu *cpu, struct memory *mem,
109 uint64_t relative_addr, unsigned char *data, size_t len,
110 int writeflag, void *extra)
111 {
112 uint64_t idata = 0, odata=0;
113 int i;
114 struct ns_data *d = extra;
115
116 idata = memory_readmax64(cpu, data, len);
117
118 /* The NS16550 should be accessed using byte read/writes: */
119 if (len != 1)
120 fatal("[ ns16550: len=%i, idata=0x%16llx! ]\n",
121 len, (long long)idata);
122
123 /*
124 * Always ready to transmit:
125 */
126 d->reg[com_lsr] |= LSR_TXRDY | LSR_TSRE;
127 d->reg[com_msr] |= MSR_DCD | MSR_DSR | MSR_CTS;
128
129 d->reg[com_iir] &= ~0xf0;
130 if (d->enable_fifo)
131 d->reg[com_iir] |= ((d->fcr << 5) & 0xc0);
132
133 d->reg[com_lsr] &= ~LSR_RXRDY;
134 if (d->in_use && console_charavail(d->console_handle))
135 d->reg[com_lsr] |= LSR_RXRDY;
136
137 relative_addr /= d->addrmult;
138
139 if (relative_addr >= DEV_NS16550_LENGTH) {
140 fatal("[ ns16550: outside register space? relative_addr="
141 "0x%llx. bad addrmult? bad device length? ]\n",
142 (long long)relative_addr);
143 return 0;
144 }
145
146 switch (relative_addr) {
147
148 case com_data: /* data AND low byte of the divisor */
149 /* Read/write of the Divisor value: */
150 if (d->dlab) {
151 /* Write or read the low byte of the divisor: */
152 if (writeflag == MEM_WRITE)
153 d->divisor = (d->divisor & 0xff00) | idata;
154 else
155 odata = d->divisor & 0xff;
156 break;
157 }
158
159 /* Read/write of data: */
160 if (writeflag == MEM_WRITE) {
161 if (d->reg[com_mcr] & MCR_LOOPBACK)
162 console_makeavail(d->console_handle, idata);
163 else
164 console_putchar(d->console_handle, idata);
165 d->reg[com_iir] |= IIR_TXRDY;
166 } else {
167 if (d->in_use)
168 odata = console_readchar(d->console_handle);
169 else
170 odata = 0;
171 }
172 dev_ns16550_tick(cpu, d);
173 break;
174
175 case com_ier: /* interrupt enable AND high byte of the divisor */
176 /* Read/write of the Divisor value: */
177 if (d->dlab) {
178 if (writeflag == MEM_WRITE) {
179 /* Set the high byte of the divisor: */
180 d->divisor = (d->divisor & 0xff) | (idata << 8);
181 debug("[ ns16550: speed set to %i bps ]\n",
182 (int)(115200 / d->divisor));
183 } else
184 odata = d->divisor >> 8;
185 break;
186 }
187
188 /* IER: */
189 if (writeflag == MEM_WRITE) {
190 /* This is to supress Linux' behaviour */
191 if (idata != 0)
192 debug("[ ns16550: write to ier: 0x%02x ]\n",
193 (int)idata);
194
195 /* Needed for NetBSD 2.0.x, but not 1.6.2? */
196 if (!(d->reg[com_ier] & IER_ETXRDY)
197 && (idata & IER_ETXRDY))
198 d->reg[com_iir] |= IIR_TXRDY;
199
200 d->reg[com_ier] = idata;
201 dev_ns16550_tick(cpu, d);
202 } else
203 odata = d->reg[com_ier];
204 break;
205
206 case com_iir: /* interrupt identification (r), fifo control (w) */
207 if (writeflag == MEM_WRITE) {
208 debug("[ ns16550: write to fifo control: 0x%02x ]\n",
209 (int)idata);
210 d->fcr = idata;
211 } else {
212 odata = d->reg[com_iir];
213 debug("[ ns16550: read from iir: 0x%02x ]\n",
214 (int)odata);
215 dev_ns16550_tick(cpu, d);
216 }
217 break;
218
219 case com_lsr:
220 if (writeflag == MEM_WRITE) {
221 debug("[ ns16550: write to lsr: 0x%02x ]\n",
222 (int)idata);
223 d->reg[com_lsr] = idata;
224 } else {
225 odata = d->reg[com_lsr];
226 /* debug("[ ns16550: read from lsr: 0x%02x ]\n",
227 (int)odata); */
228 }
229 break;
230
231 case com_msr:
232 if (writeflag == MEM_WRITE) {
233 debug("[ ns16550: write to msr: 0x%02x ]\n",
234 (int)idata);
235 d->reg[com_msr] = idata;
236 } else {
237 odata = d->reg[com_msr];
238 debug("[ ns16550: read from msr: 0x%02x ]\n",
239 (int)odata);
240 }
241 break;
242
243 case com_lctl:
244 if (writeflag == MEM_WRITE) {
245 d->reg[com_lctl] = idata;
246 switch (idata & 0x7) {
247 case 0: d->databits = 5; d->stopbits = "1"; break;
248 case 1: d->databits = 6; d->stopbits = "1"; break;
249 case 2: d->databits = 7; d->stopbits = "1"; break;
250 case 3: d->databits = 8; d->stopbits = "1"; break;
251 case 4: d->databits = 5; d->stopbits = "1.5"; break;
252 case 5: d->databits = 6; d->stopbits = "2"; break;
253 case 6: d->databits = 7; d->stopbits = "2"; break;
254 case 7: d->databits = 8; d->stopbits = "2"; break;
255 }
256 switch ((idata & 0x38) / 0x8) {
257 case 0: d->parity = 'N'; break; /* none */
258 case 1: d->parity = 'O'; break; /* odd */
259 case 2: d->parity = '?'; break;
260 case 3: d->parity = 'E'; break; /* even */
261 case 4: d->parity = '?'; break;
262 case 5: d->parity = 'Z'; break; /* zero */
263 case 6: d->parity = '?'; break;
264 case 7: d->parity = 'o'; break; /* one */
265 }
266
267 d->dlab = idata & 0x80? 1 : 0;
268
269 debug("[ ns16550: write to lctl: 0x%02x (%s%s"
270 "setting mode %i%c%s) ]\n",
271 (int)idata,
272 d->dlab? "Divisor Latch access, " : "",
273 idata&0x40? "sending BREAK, " : "",
274 d->databits, d->parity, d->stopbits);
275 } else {
276 odata = d->reg[com_lctl];
277 debug("[ ns16550: read from lctl: 0x%02x ]\n",
278 (int)odata);
279 }
280 break;
281
282 case com_mcr:
283 if (writeflag == MEM_WRITE) {
284 d->reg[com_mcr] = idata;
285 debug("[ ns16550: write to mcr: 0x%02x ]\n",
286 (int)idata);
287 } else {
288 odata = d->reg[com_mcr];
289 debug("[ ns16550: read from mcr: 0x%02x ]\n",
290 (int)odata);
291 }
292 break;
293
294 default:
295 if (writeflag==MEM_READ) {
296 debug("[ ns16550: read from reg %i ]\n",
297 (int)relative_addr);
298 odata = d->reg[relative_addr];
299 } else {
300 debug("[ ns16550: write to reg %i:",
301 (int)relative_addr);
302 for (i=0; i<len; i++)
303 debug(" %02x", data[i]);
304 debug(" ]\n");
305 d->reg[relative_addr] = idata;
306 }
307 }
308
309 if (writeflag == MEM_READ)
310 memory_writemax64(cpu, data, len, odata);
311
312 return 1;
313 }
314
315
316 /*
317 * devinit_ns16550():
318 */
319 int devinit_ns16550(struct devinit *devinit)
320 {
321 struct ns_data *d = malloc(sizeof(struct ns_data));
322 size_t nlen;
323 char *name;
324
325 if (d == NULL) {
326 fprintf(stderr, "out of memory\n");
327 exit(1);
328 }
329 memset(d, 0, sizeof(struct ns_data));
330 d->irqnr = devinit->irq_nr;
331 d->addrmult = devinit->addr_mult;
332 d->in_use = devinit->in_use;
333 d->enable_fifo = 1;
334 d->dlab = 0;
335 d->divisor = 115200 / 9600;
336 d->databits = 8;
337 d->parity = 'N';
338 d->stopbits = "1";
339 d->console_handle =
340 console_start_slave(devinit->machine, devinit->name);
341
342 nlen = strlen(devinit->name) + 10;
343 if (devinit->name2 != NULL)
344 nlen += strlen(devinit->name2);
345 name = malloc(nlen);
346 if (name == NULL) {
347 fprintf(stderr, "out of memory\n");
348 exit(1);
349 }
350 if (devinit->name2 != NULL && devinit->name2[0])
351 snprintf(name, nlen, "%s [%s]", devinit->name, devinit->name2);
352 else
353 snprintf(name, nlen, "%s", devinit->name);
354
355 memory_device_register(devinit->machine->memory, name, devinit->addr,
356 DEV_NS16550_LENGTH * d->addrmult, dev_ns16550_access, d,
357 MEM_DEFAULT, NULL);
358 machine_add_tickfunction(devinit->machine,
359 dev_ns16550_tick, d, TICK_SHIFT);
360
361 /*
362 * NOTE: Ugly cast into a pointer, because this is a convenient way
363 * to return the console handle to code in src/machine.c.
364 */
365 devinit->return_ptr = (void *)(size_t)d->console_handle;
366
367 return 1;
368 }
369

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