/[gxemul]/trunk/src/devices/dev_ns16550.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Contents of /trunk/src/devices/dev_ns16550.c

Parent Directory Parent Directory | Revision Log Revision Log

Revision 34 - (show annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 7 months ago) by dpavlin
File MIME type: text/plain
File size: 10497 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============
1 /*
2 * Copyright (C) 2003-2007 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_ns16550.c,v 1.58 2006/12/30 13:30:58 debug Exp $
29 *
30 * NS16550 serial controller.
31 *
32 *
33 * TODO: Implement the FIFO.
34 */
35
36 #include <stdio.h>
37 #include <stdlib.h>
38 #include <string.h>
39
40 #include "console.h"
41 #include "cpu.h"
42 #include "device.h"
43 #include "interrupt.h"
44 #include "machine.h"
45 #include "memory.h"
46 #include "misc.h"
47
48 #include "comreg.h"
49
50
51 /* #define debug fatal */
52
53 #define TICK_SHIFT 14
54 #define DEV_NS16550_LENGTH 8
55
56 struct ns_data {
57 int addrmult;
58 int in_use;
59 char *name;
60 int console_handle;
61 int enable_fifo;
62
63 struct interrupt irq;
64
65 unsigned char reg[DEV_NS16550_LENGTH];
66 unsigned char fcr; /* FIFO control register */
67 int int_asserted;
68 int dlab; /* Divisor Latch Access bit */
69 int divisor;
70
71 int databits;
72 char parity;
73 const char *stopbits;
74 };
75
76
77 DEVICE_TICK(ns16550)
78 {
79 /*
80 * This function is called at regular intervals. An interrupt is
81 * asserted if there is a character available for reading, or if the
82 * transmitter slot is empty (i.e. the ns16550 is ready to transmit).
83 */
84 struct ns_data *d = extra;
85
86 d->reg[com_iir] &= ~IIR_RXRDY;
87 if (console_charavail(d->console_handle))
88 d->reg[com_iir] |= IIR_RXRDY;
89
90 /*
91 * If interrupts are enabled, and interrupts are pending, then
92 * cause a CPU interrupt.
93 */
94
95 if (((d->reg[com_ier] & IER_ETXRDY) && (d->reg[com_iir] & IIR_TXRDY)) ||
96 ((d->reg[com_ier] & IER_ERXRDY) && (d->reg[com_iir] & IIR_RXRDY))) {
97 d->reg[com_iir] &= ~IIR_NOPEND;
98 if (d->reg[com_mcr] & MCR_IENABLE) {
99 INTERRUPT_ASSERT(d->irq);
100 d->int_asserted = 1;
101 }
102 } else {
103 d->reg[com_iir] |= IIR_NOPEND;
104 if (d->int_asserted)
105 INTERRUPT_DEASSERT(d->irq);
106 d->int_asserted = 0;
107 }
108 }
109
110
111 DEVICE_ACCESS(ns16550)
112 {
113 uint64_t idata = 0, odata=0;
114 size_t i;
115 struct ns_data *d = extra;
116
117 if (writeflag == MEM_WRITE)
118 idata = memory_readmax64(cpu, data, len);
119
120 #if 0
121 /* The NS16550 should be accessed using byte read/writes: */
122 if (len != 1)
123 fatal("[ ns16550 (%s): len=%i, idata=0x%16llx! ]\n",
124 d->name, len, (long long)idata);
125 #endif
126
127 /*
128 * Always ready to transmit:
129 */
130 d->reg[com_lsr] |= LSR_TXRDY | LSR_TSRE;
131 d->reg[com_msr] |= MSR_DCD | MSR_DSR | MSR_CTS;
132
133 d->reg[com_iir] &= ~0xf0;
134 if (d->enable_fifo)
135 d->reg[com_iir] |= ((d->fcr << 5) & 0xc0);
136
137 d->reg[com_lsr] &= ~LSR_RXRDY;
138 if (console_charavail(d->console_handle))
139 d->reg[com_lsr] |= LSR_RXRDY;
140
141 relative_addr /= d->addrmult;
142
143 if (relative_addr >= DEV_NS16550_LENGTH) {
144 fatal("[ ns16550 (%s): outside register space? relative_addr="
145 "0x%llx. bad addrmult? bad device length? ]\n", d->name,
146 (long long)relative_addr);
147 return 0;
148 }
149
150 switch (relative_addr) {
151
152 case com_data: /* data AND low byte of the divisor */
153 /* Read/write of the Divisor value: */
154 if (d->dlab) {
155 /* Write or read the low byte of the divisor: */
156 if (writeflag == MEM_WRITE)
157 d->divisor = (d->divisor & 0xff00) | idata;
158 else
159 odata = d->divisor & 0xff;
160 break;
161 }
162
163 /* Read/write of data: */
164 if (writeflag == MEM_WRITE) {
165 if (d->reg[com_mcr] & MCR_LOOPBACK)
166 console_makeavail(d->console_handle, idata);
167 else
168 console_putchar(d->console_handle, idata);
169 d->reg[com_iir] |= IIR_TXRDY;
170 } else {
171 int x = console_readchar(d->console_handle);
172 odata = x < 0? 0 : x;
173 }
174 dev_ns16550_tick(cpu, d);
175 break;
176
177 case com_ier: /* interrupt enable AND high byte of the divisor */
178 /* Read/write of the Divisor value: */
179 if (d->dlab) {
180 if (writeflag == MEM_WRITE) {
181 /* Set the high byte of the divisor: */
182 d->divisor = (d->divisor & 0xff) | (idata << 8);
183 debug("[ ns16550 (%s): speed set to %i bps ]\n",
184 d->name, (int)(115200 / d->divisor));
185 } else
186 odata = d->divisor >> 8;
187 break;
188 }
189
190 /* IER: */
191 if (writeflag == MEM_WRITE) {
192 /* This is to supress Linux' behaviour */
193 if (idata != 0)
194 debug("[ ns16550 (%s): write to ier: 0x%02x ]"
195 "\n", d->name, (int)idata);
196
197 /* Needed for NetBSD 2.0.x, but not 1.6.2? */
198 if (!(d->reg[com_ier] & IER_ETXRDY)
199 && (idata & IER_ETXRDY))
200 d->reg[com_iir] |= IIR_TXRDY;
201
202 d->reg[com_ier] = idata;
203 dev_ns16550_tick(cpu, d);
204 } else
205 odata = d->reg[com_ier];
206 break;
207
208 case com_iir: /* interrupt identification (r), fifo control (w) */
209 if (writeflag == MEM_WRITE) {
210 debug("[ ns16550 (%s): write to fifo control: 0x%02x ]"
211 "\n", d->name, (int)idata);
212 d->fcr = idata;
213 } else {
214 odata = d->reg[com_iir];
215 if (d->reg[com_iir] & IIR_TXRDY)
216 d->reg[com_iir] &= ~IIR_TXRDY;
217 debug("[ ns16550 (%s): read from iir: 0x%02x ]\n",
218 d->name, (int)odata);
219 dev_ns16550_tick(cpu, d);
220 }
221 break;
222
223 case com_lsr:
224 if (writeflag == MEM_WRITE) {
225 debug("[ ns16550 (%s): write to lsr: 0x%02x ]\n",
226 d->name, (int)idata);
227 d->reg[com_lsr] = idata;
228 } else {
229 odata = d->reg[com_lsr];
230 /* debug("[ ns16550 (%s): read from lsr: 0x%02x ]\n",
231 d->name, (int)odata); */
232 }
233 break;
234
235 case com_msr:
236 if (writeflag == MEM_WRITE) {
237 debug("[ ns16550 (%s): write to msr: 0x%02x ]\n",
238 d->name, (int)idata);
239 d->reg[com_msr] = idata;
240 } else {
241 odata = d->reg[com_msr];
242 debug("[ ns16550 (%s): read from msr: 0x%02x ]\n",
243 d->name, (int)odata);
244 }
245 break;
246
247 case com_lctl:
248 if (writeflag == MEM_WRITE) {
249 d->reg[com_lctl] = idata;
250 switch (idata & 0x7) {
251 case 0: d->databits = 5; d->stopbits = "1"; break;
252 case 1: d->databits = 6; d->stopbits = "1"; break;
253 case 2: d->databits = 7; d->stopbits = "1"; break;
254 case 3: d->databits = 8; d->stopbits = "1"; break;
255 case 4: d->databits = 5; d->stopbits = "1.5"; break;
256 case 5: d->databits = 6; d->stopbits = "2"; break;
257 case 6: d->databits = 7; d->stopbits = "2"; break;
258 case 7: d->databits = 8; d->stopbits = "2"; break;
259 }
260 switch ((idata & 0x38) / 0x8) {
261 case 0: d->parity = 'N'; break; /* none */
262 case 1: d->parity = 'O'; break; /* odd */
263 case 2: d->parity = '?'; break;
264 case 3: d->parity = 'E'; break; /* even */
265 case 4: d->parity = '?'; break;
266 case 5: d->parity = 'Z'; break; /* zero */
267 case 6: d->parity = '?'; break;
268 case 7: d->parity = 'o'; break; /* one */
269 }
270
271 d->dlab = idata & 0x80? 1 : 0;
272
273 debug("[ ns16550 (%s): write to lctl: 0x%02x (%s%s"
274 "setting mode %i%c%s) ]\n", d->name, (int)idata,
275 d->dlab? "Divisor Latch access, " : "",
276 idata&0x40? "sending BREAK, " : "",
277 d->databits, d->parity, d->stopbits);
278 } else {
279 odata = d->reg[com_lctl];
280 debug("[ ns16550 (%s): read from lctl: 0x%02x ]\n",
281 d->name, (int)odata);
282 }
283 break;
284
285 case com_mcr:
286 if (writeflag == MEM_WRITE) {
287 d->reg[com_mcr] = idata;
288 debug("[ ns16550 (%s): write to mcr: 0x%02x ]\n",
289 d->name, (int)idata);
290 if (!(d->reg[com_iir] & IIR_TXRDY)
291 && (idata & MCR_IENABLE))
292 d->reg[com_iir] |= IIR_TXRDY;
293 dev_ns16550_tick(cpu, d);
294 } else {
295 odata = d->reg[com_mcr];
296 debug("[ ns16550 (%s): read from mcr: 0x%02x ]\n",
297 d->name, (int)odata);
298 }
299 break;
300
301 default:
302 if (writeflag==MEM_READ) {
303 debug("[ ns16550 (%s): read from reg %i ]\n",
304 d->name, (int)relative_addr);
305 odata = d->reg[relative_addr];
306 } else {
307 debug("[ ns16550 (%s): write to reg %i:",
308 d->name, (int)relative_addr);
309 for (i=0; i<len; i++)
310 debug(" %02x", data[i]);
311 debug(" ]\n");
312 d->reg[relative_addr] = idata;
313 }
314 }
315
316 if (writeflag == MEM_READ)
317 memory_writemax64(cpu, data, len, odata);
318
319 return 1;
320 }
321
322
323 DEVINIT(ns16550)
324 {
325 struct ns_data *d = malloc(sizeof(struct ns_data));
326 size_t nlen;
327 char *name;
328
329 if (d == NULL) {
330 fprintf(stderr, "out of memory\n");
331 exit(1);
332 }
333 memset(d, 0, sizeof(struct ns_data));
334
335 d->addrmult = devinit->addr_mult;
336 d->in_use = devinit->in_use;
337 d->enable_fifo = 1;
338 d->dlab = 0;
339 d->divisor = 115200 / 9600;
340 d->databits = 8;
341 d->parity = 'N';
342 d->stopbits = "1";
343 d->name = devinit->name2 != NULL? devinit->name2 : "";
344 d->console_handle =
345 console_start_slave(devinit->machine, devinit->name2 != NULL?
346 devinit->name2 : devinit->name, d->in_use);
347
348 INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
349
350 nlen = strlen(devinit->name) + 10;
351 if (devinit->name2 != NULL)
352 nlen += strlen(devinit->name2);
353 name = malloc(nlen);
354 if (name == NULL) {
355 fprintf(stderr, "out of memory\n");
356 exit(1);
357 }
358 if (devinit->name2 != NULL && devinit->name2[0])
359 snprintf(name, nlen, "%s [%s]", devinit->name, devinit->name2);
360 else
361 snprintf(name, nlen, "%s", devinit->name);
362
363 memory_device_register(devinit->machine->memory, name, devinit->addr,
364 DEV_NS16550_LENGTH * d->addrmult, dev_ns16550_access, d,
365 DM_DEFAULT, NULL);
366 machine_add_tickfunction(devinit->machine,
367 dev_ns16550_tick, d, TICK_SHIFT, 0.0);
368
369 /*
370 * NOTE: Ugly cast into a pointer, because this is a convenient way
371 * to return the console handle to code in src/machine.c.
372 */
373 devinit->return_ptr = (void *)(size_t)d->console_handle;
374
375 return 1;
376 }
377
  ViewVC Help
Powered by ViewVC 1.1.26