1 |
/* |
/* |
2 |
* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
3 |
* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
5 |
* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
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* |
* |
28 |
* $Id: dev_ns16550.c,v 1.32 2005/02/19 11:51:33 debug Exp $ |
* $Id: dev_ns16550.c,v 1.54 2006/04/06 18:08:42 debug Exp $ |
29 |
* |
* |
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* NS16550 serial controller. |
* NS16550 serial controller. |
31 |
* |
* |
32 |
* TODO: actually implement the fifo :) |
* |
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* TODO: Implement the FIFO. |
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*/ |
*/ |
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#include <stdio.h> |
#include <stdio.h> |
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40 |
#include "console.h" |
#include "console.h" |
41 |
#include "cpu.h" |
#include "cpu.h" |
42 |
#include "devices.h" |
#include "device.h" |
43 |
#include "machine.h" |
#include "machine.h" |
44 |
#include "memory.h" |
#include "memory.h" |
45 |
#include "misc.h" |
#include "misc.h" |
47 |
#include "comreg.h" |
#include "comreg.h" |
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50 |
/* #define debug fatal */ |
/* #define debug fatal */ |
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#define NS16550_TICK_SHIFT 14 |
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/* #define DISABLE_FIFO */ |
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#define TICK_SHIFT 14 |
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#define DEV_NS16550_LENGTH 8 |
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struct ns_data { |
struct ns_data { |
56 |
int reg[8]; |
int addrmult; |
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int in_use; |
58 |
int irqnr; |
int irqnr; |
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char *name; |
60 |
int console_handle; |
int console_handle; |
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int enable_fifo; |
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int irq_enable; |
unsigned char reg[DEV_NS16550_LENGTH]; |
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int addrmult; |
unsigned char fcr; /* FIFO control register */ |
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int in_use; |
int int_asserted; |
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int dlab; /* Divisor Latch Access bit */ |
int dlab; /* Divisor Latch Access bit */ |
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int divisor; |
int divisor; |
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int databits; |
int databits; |
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char parity; |
char parity; |
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const char *stopbits; |
const char *stopbits; |
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/* |
/* |
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* dev_ns16550_tick(): |
* dev_ns16550_tick(): |
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* |
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* This function is called at regular intervals. An interrupt is caused to the |
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* CPU if there is a character available for reading, or if the transmitter |
80 |
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* slot is empty (i.e. the ns16550 is ready to transmit). |
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*/ |
*/ |
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void dev_ns16550_tick(struct cpu *cpu, void *extra) |
void dev_ns16550_tick(struct cpu *cpu, void *extra) |
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{ |
{ |
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struct ns_data *d = extra; |
struct ns_data *d = extra; |
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d->reg[com_iir] |= IIR_NOPEND; |
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cpu_interrupt_ack(cpu, d->irqnr); |
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d->reg[com_iir] &= ~IIR_RXRDY; |
d->reg[com_iir] &= ~IIR_RXRDY; |
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if (d->in_use) { |
if (console_charavail(d->console_handle)) |
88 |
if (console_charavail(d->console_handle)) |
d->reg[com_iir] |= IIR_RXRDY; |
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d->reg[com_iir] |= IIR_RXRDY; |
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} |
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if ((d->irq_enable & IER_ETXRDY && d->reg[com_iir] & IIR_TXRDY) || |
/* |
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(d->irq_enable & IER_ERXRDY && d->reg[com_iir] & IIR_RXRDY)) { |
* If interrupts are enabled, and interrupts are pending, then |
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* cause a CPU interrupt. |
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*/ |
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if (((d->reg[com_ier] & IER_ETXRDY) && (d->reg[com_iir] & IIR_TXRDY)) || |
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((d->reg[com_ier] & IER_ERXRDY) && (d->reg[com_iir] & IIR_RXRDY))) { |
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d->reg[com_iir] &= ~IIR_NOPEND; |
d->reg[com_iir] &= ~IIR_NOPEND; |
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if (d->reg[com_mcr] & MCR_IENABLE) |
if (d->reg[com_mcr] & MCR_IENABLE) { |
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cpu_interrupt(cpu, d->irqnr); |
cpu_interrupt(cpu, d->irqnr); |
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d->int_asserted = 1; |
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} |
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} else { |
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d->reg[com_iir] |= IIR_NOPEND; |
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if (d->int_asserted) |
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cpu_interrupt_ack(cpu, d->irqnr); |
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d->int_asserted = 0; |
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} |
} |
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} |
} |
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/* |
/* |
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* dev_ns16550_access(): |
* dev_ns16550_access(): |
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*/ |
*/ |
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int dev_ns16550_access(struct cpu *cpu, struct memory *mem, |
DEVICE_ACCESS(ns16550) |
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uint64_t relative_addr, unsigned char *data, size_t len, |
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int writeflag, void *extra) |
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{ |
{ |
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uint64_t idata = 0, odata=0; |
uint64_t idata = 0, odata=0; |
117 |
int i; |
size_t i; |
118 |
struct ns_data *d = extra; |
struct ns_data *d = extra; |
119 |
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idata = memory_readmax64(cpu, data, len); |
if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
122 |
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#if 0 |
124 |
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/* The NS16550 should be accessed using byte read/writes: */ |
125 |
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if (len != 1) |
126 |
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fatal("[ ns16550 (%s): len=%i, idata=0x%16llx! ]\n", |
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d->name, len, (long long)idata); |
128 |
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#endif |
129 |
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/* Always ready to transmit: */ |
/* |
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* Always ready to transmit: |
132 |
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*/ |
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d->reg[com_lsr] |= LSR_TXRDY | LSR_TSRE; |
d->reg[com_lsr] |= LSR_TXRDY | LSR_TSRE; |
134 |
d->reg[com_lsr] &= ~LSR_RXRDY; |
d->reg[com_msr] |= MSR_DCD | MSR_DSR | MSR_CTS; |
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d->reg[com_msr] = MSR_DCD | MSR_DSR | MSR_CTS; |
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135 |
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#ifdef DISABLE_FIFO |
d->reg[com_iir] &= ~0xf0; |
137 |
/* FIFO turned off: */ |
if (d->enable_fifo) |
138 |
d->reg[com_iir] &= 0x0f; |
d->reg[com_iir] |= ((d->fcr << 5) & 0xc0); |
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#endif |
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139 |
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if (d->in_use) { |
d->reg[com_lsr] &= ~LSR_RXRDY; |
141 |
if (console_charavail(d->console_handle)) { |
if (console_charavail(d->console_handle)) |
142 |
d->reg[com_lsr] |= LSR_RXRDY; |
d->reg[com_lsr] |= LSR_RXRDY; |
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} |
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} |
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143 |
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relative_addr /= d->addrmult; |
relative_addr /= d->addrmult; |
145 |
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146 |
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if (relative_addr >= DEV_NS16550_LENGTH) { |
147 |
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fatal("[ ns16550 (%s): outside register space? relative_addr=" |
148 |
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"0x%llx. bad addrmult? bad device length? ]\n", d->name, |
149 |
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(long long)relative_addr); |
150 |
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return 0; |
151 |
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} |
152 |
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153 |
switch (relative_addr) { |
switch (relative_addr) { |
154 |
case com_data: /* com_data or com_dlbl */ |
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155 |
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case com_data: /* data AND low byte of the divisor */ |
156 |
/* Read/write of the Divisor value: */ |
/* Read/write of the Divisor value: */ |
157 |
if (d->dlab) { |
if (d->dlab) { |
158 |
if (writeflag == MEM_WRITE) { |
/* Write or read the low byte of the divisor: */ |
159 |
/* Set the low byte of the divisor: */ |
if (writeflag == MEM_WRITE) |
160 |
d->divisor &= ~0xff; |
d->divisor = (d->divisor & 0xff00) | idata; |
161 |
d->divisor |= (idata & 0xff); |
else |
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} else { |
|
162 |
odata = d->divisor & 0xff; |
odata = d->divisor & 0xff; |
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} |
|
163 |
break; |
break; |
164 |
} |
} |
165 |
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166 |
/* Read write of data: */ |
/* Read/write of data: */ |
167 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
168 |
if (d->reg[com_mcr] & MCR_LOOPBACK) { |
if (d->reg[com_mcr] & MCR_LOOPBACK) |
169 |
console_makeavail(d->console_handle, idata); |
console_makeavail(d->console_handle, idata); |
170 |
} else { |
else |
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#if 0 |
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/* Ugly hack: don't show form feeds: */ |
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if (idata != 12) |
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#endif |
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171 |
console_putchar(d->console_handle, idata); |
console_putchar(d->console_handle, idata); |
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} |
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172 |
d->reg[com_iir] |= IIR_TXRDY; |
d->reg[com_iir] |= IIR_TXRDY; |
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dev_ns16550_tick(cpu, d); |
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return 1; |
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173 |
} else { |
} else { |
174 |
if (d->in_use) |
int x = console_readchar(d->console_handle); |
175 |
odata = console_readchar(d->console_handle); |
odata = x < 0? 0 : x; |
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else |
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odata = 0; |
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dev_ns16550_tick(cpu, d); |
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176 |
} |
} |
177 |
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dev_ns16550_tick(cpu, d); |
178 |
break; |
break; |
179 |
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180 |
case com_ier: /* interrupt enable AND high byte of the divisor */ |
case com_ier: /* interrupt enable AND high byte of the divisor */ |
181 |
/* Read/write of the Divisor value: */ |
/* Read/write of the Divisor value: */ |
182 |
if (d->dlab) { |
if (d->dlab) { |
183 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
184 |
/* Set the high byte of the divisor: */ |
/* Set the high byte of the divisor: */ |
185 |
d->divisor &= ~0xff00; |
d->divisor = (d->divisor & 0xff) | (idata << 8); |
186 |
d->divisor |= ((idata & 0xff) << 8); |
debug("[ ns16550 (%s): speed set to %i bps ]\n", |
187 |
debug("[ ns16550 speed set to %i bps ]\n", |
d->name, (int)(115200 / d->divisor)); |
188 |
115200 / d->divisor); |
} else |
189 |
} else { |
odata = d->divisor >> 8; |
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odata = (d->divisor & 0xff00) >> 8; |
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} |
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190 |
break; |
break; |
191 |
} |
} |
192 |
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194 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
195 |
/* This is to supress Linux' behaviour */ |
/* This is to supress Linux' behaviour */ |
196 |
if (idata != 0) |
if (idata != 0) |
197 |
debug("[ ns16550 write to ier: 0x%02x ]\n", |
debug("[ ns16550 (%s): write to ier: 0x%02x ]" |
198 |
idata); |
"\n", d->name, (int)idata); |
199 |
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200 |
/* Needed for NetBSD 2.0, but not 1.6.2? */ |
/* Needed for NetBSD 2.0.x, but not 1.6.2? */ |
201 |
if (!(d->irq_enable & IER_ETXRDY) |
if (!(d->reg[com_ier] & IER_ETXRDY) |
202 |
&& (idata & IER_ETXRDY)) |
&& (idata & IER_ETXRDY)) |
203 |
d->reg[com_iir] |= IIR_TXRDY; |
d->reg[com_iir] |= IIR_TXRDY; |
204 |
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|
205 |
d->irq_enable = idata; |
d->reg[com_ier] = idata; |
206 |
dev_ns16550_tick(cpu, d); |
dev_ns16550_tick(cpu, d); |
207 |
} else { |
} else |
208 |
odata = d->reg[relative_addr]; |
odata = d->reg[com_ier]; |
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} |
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209 |
break; |
break; |
210 |
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211 |
case com_iir: /* interrupt identification (r), fifo control (w) */ |
case com_iir: /* interrupt identification (r), fifo control (w) */ |
212 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
213 |
debug("[ ns16550 write to fifo control ]\n"); |
debug("[ ns16550 (%s): write to fifo control: 0x%02x ]" |
214 |
d->reg[relative_addr] = idata; |
"\n", d->name, (int)idata); |
215 |
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d->fcr = idata; |
216 |
} else { |
} else { |
217 |
odata = d->reg[relative_addr]; |
odata = d->reg[com_iir]; |
218 |
debug("[ ns16550 read from iir: 0x%02x ]\n", odata); |
if (d->reg[com_iir] & IIR_TXRDY) |
219 |
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d->reg[com_iir] &= ~IIR_TXRDY; |
220 |
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debug("[ ns16550 (%s): read from iir: 0x%02x ]\n", |
221 |
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d->name, (int)odata); |
222 |
dev_ns16550_tick(cpu, d); |
dev_ns16550_tick(cpu, d); |
223 |
} |
} |
224 |
break; |
break; |
225 |
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|
226 |
case com_lsr: |
case com_lsr: |
227 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
228 |
debug("[ ns16550 write to lsr ]\n"); |
debug("[ ns16550 (%s): write to lsr: 0x%02x ]\n", |
229 |
d->reg[relative_addr] = idata; |
d->name, (int)idata); |
230 |
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d->reg[com_lsr] = idata; |
231 |
} else { |
} else { |
232 |
odata = d->reg[relative_addr]; |
odata = d->reg[com_lsr]; |
233 |
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/* debug("[ ns16550 (%s): read from lsr: 0x%02x ]\n", |
234 |
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d->name, (int)odata); */ |
235 |
} |
} |
236 |
break; |
break; |
237 |
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|
238 |
case com_msr: |
case com_msr: |
239 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
240 |
debug("[ ns16550 write to msr ]\n"); |
debug("[ ns16550 (%s): write to msr: 0x%02x ]\n", |
241 |
d->reg[relative_addr] = idata; |
d->name, (int)idata); |
242 |
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d->reg[com_msr] = idata; |
243 |
} else { |
} else { |
244 |
odata = d->reg[relative_addr]; |
odata = d->reg[com_msr]; |
245 |
|
debug("[ ns16550 (%s): read from msr: 0x%02x ]\n", |
246 |
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d->name, (int)odata); |
247 |
} |
} |
248 |
break; |
break; |
249 |
|
|
250 |
case com_lctl: |
case com_lctl: |
251 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
252 |
d->reg[relative_addr] = idata; |
d->reg[com_lctl] = idata; |
253 |
switch (idata & 0x7) { |
switch (idata & 0x7) { |
254 |
case 0: d->databits = 5; d->stopbits = "1"; break; |
case 0: d->databits = 5; d->stopbits = "1"; break; |
255 |
case 1: d->databits = 6; d->stopbits = "1"; break; |
case 1: d->databits = 6; d->stopbits = "1"; break; |
273 |
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274 |
d->dlab = idata & 0x80? 1 : 0; |
d->dlab = idata & 0x80? 1 : 0; |
275 |
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|
276 |
debug("[ ns16550 write to lctl: 0x%02x (%s%s" |
debug("[ ns16550 (%s): write to lctl: 0x%02x (%s%s" |
277 |
"setting mode %i%c%s) ]\n", |
"setting mode %i%c%s) ]\n", d->name, (int)idata, |
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(int)idata, |
|
278 |
d->dlab? "Divisor Latch access, " : "", |
d->dlab? "Divisor Latch access, " : "", |
279 |
idata&0x40? "sending BREAK, " : "", |
idata&0x40? "sending BREAK, " : "", |
280 |
d->databits, d->parity, d->stopbits); |
d->databits, d->parity, d->stopbits); |
281 |
} else { |
} else { |
282 |
odata = d->reg[relative_addr]; |
odata = d->reg[com_lctl]; |
283 |
debug("[ ns16550 read from lctl: 0x%02x ]\n", odata); |
debug("[ ns16550 (%s): read from lctl: 0x%02x ]\n", |
284 |
|
d->name, (int)odata); |
285 |
} |
} |
286 |
break; |
break; |
287 |
|
|
288 |
case com_mcr: |
case com_mcr: |
289 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
290 |
d->reg[relative_addr] = idata; |
d->reg[com_mcr] = idata; |
291 |
debug("[ ns16550 write to mcr: 0x%02x ]\n", idata); |
debug("[ ns16550 (%s): write to mcr: 0x%02x ]\n", |
292 |
|
d->name, (int)idata); |
293 |
|
if (!(d->reg[com_iir] & IIR_TXRDY) |
294 |
|
&& (idata & MCR_IENABLE)) |
295 |
|
d->reg[com_iir] |= IIR_TXRDY; |
296 |
|
dev_ns16550_tick(cpu, d); |
297 |
} else { |
} else { |
298 |
odata = d->reg[relative_addr]; |
odata = d->reg[com_mcr]; |
299 |
debug("[ ns16550 read from mcr: 0x%02x ]\n", odata); |
debug("[ ns16550 (%s): read from mcr: 0x%02x ]\n", |
300 |
|
d->name, (int)odata); |
301 |
} |
} |
302 |
break; |
break; |
303 |
|
|
304 |
default: |
default: |
305 |
if (writeflag==MEM_READ) { |
if (writeflag==MEM_READ) { |
306 |
debug("[ ns16550 read from reg %i ]\n", |
debug("[ ns16550 (%s): read from reg %i ]\n", |
307 |
(int)relative_addr); |
d->name, (int)relative_addr); |
308 |
odata = d->reg[relative_addr]; |
odata = d->reg[relative_addr]; |
309 |
} else { |
} else { |
310 |
debug("[ ns16550 write to reg %i:", |
debug("[ ns16550 (%s): write to reg %i:", |
311 |
(int)relative_addr); |
d->name, (int)relative_addr); |
312 |
for (i=0; i<len; i++) |
for (i=0; i<len; i++) |
313 |
debug(" %02x", data[i]); |
debug(" %02x", data[i]); |
314 |
debug(" ]\n"); |
debug(" ]\n"); |
323 |
} |
} |
324 |
|
|
325 |
|
|
326 |
/* |
DEVINIT(ns16550) |
|
* dev_ns16550_init(): |
|
|
*/ |
|
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int dev_ns16550_init(struct machine *machine, struct memory *mem, |
|
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uint64_t baseaddr, int irq_nr, int addrmult, int in_use, |
|
|
char *name) |
|
327 |
{ |
{ |
328 |
struct ns_data *d; |
struct ns_data *d = malloc(sizeof(struct ns_data)); |
329 |
char *name2; |
size_t nlen; |
330 |
|
char *name; |
331 |
|
|
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d = malloc(sizeof(struct ns_data)); |
|
332 |
if (d == NULL) { |
if (d == NULL) { |
333 |
fprintf(stderr, "out of memory\n"); |
fprintf(stderr, "out of memory\n"); |
334 |
exit(1); |
exit(1); |
335 |
} |
} |
336 |
memset(d, 0, sizeof(struct ns_data)); |
memset(d, 0, sizeof(struct ns_data)); |
337 |
d->irqnr = irq_nr; |
d->irqnr = devinit->irq_nr; |
338 |
d->addrmult = addrmult; |
d->addrmult = devinit->addr_mult; |
339 |
d->in_use = in_use; |
d->in_use = devinit->in_use; |
340 |
d->dlab = 0; |
d->enable_fifo = 1; |
341 |
d->divisor = 115200 / 9600; |
d->dlab = 0; |
342 |
d->databits = 8; |
d->divisor = 115200 / 9600; |
343 |
d->parity = 'N'; |
d->databits = 8; |
344 |
d->stopbits = "1"; |
d->parity = 'N'; |
345 |
d->console_handle = console_start_slave(machine, name); |
d->stopbits = "1"; |
346 |
|
d->name = devinit->name2 != NULL? devinit->name2 : ""; |
347 |
name2 = malloc(strlen(name) + 20); |
d->console_handle = |
348 |
if (name2 == NULL) { |
console_start_slave(devinit->machine, devinit->name2 != NULL? |
349 |
fprintf(stderr, "out of memory in dev_ns16550_init()\n"); |
devinit->name2 : devinit->name, d->in_use); |
350 |
|
|
351 |
|
nlen = strlen(devinit->name) + 10; |
352 |
|
if (devinit->name2 != NULL) |
353 |
|
nlen += strlen(devinit->name2); |
354 |
|
name = malloc(nlen); |
355 |
|
if (name == NULL) { |
356 |
|
fprintf(stderr, "out of memory\n"); |
357 |
exit(1); |
exit(1); |
358 |
} |
} |
359 |
if (name != NULL && name[0]) |
if (devinit->name2 != NULL && devinit->name2[0]) |
360 |
sprintf(name2, "ns16550 [%s]", name); |
snprintf(name, nlen, "%s [%s]", devinit->name, devinit->name2); |
361 |
else |
else |
362 |
sprintf(name2, "ns16550"); |
snprintf(name, nlen, "%s", devinit->name); |
363 |
|
|
364 |
memory_device_register(mem, name2, baseaddr, |
memory_device_register(devinit->machine->memory, name, devinit->addr, |
365 |
DEV_NS16550_LENGTH * addrmult, dev_ns16550_access, d, |
DEV_NS16550_LENGTH * d->addrmult, dev_ns16550_access, d, |
366 |
MEM_DEFAULT, NULL); |
DM_DEFAULT, NULL); |
367 |
machine_add_tickfunction(machine, dev_ns16550_tick, |
machine_add_tickfunction(devinit->machine, |
368 |
d, NS16550_TICK_SHIFT); |
dev_ns16550_tick, d, TICK_SHIFT, 0.0); |
369 |
|
|
370 |
|
/* |
371 |
|
* NOTE: Ugly cast into a pointer, because this is a convenient way |
372 |
|
* to return the console handle to code in src/machine.c. |
373 |
|
*/ |
374 |
|
devinit->return_ptr = (void *)(size_t)d->console_handle; |
375 |
|
|
376 |
return d->console_handle; |
return 1; |
377 |
} |
} |
378 |
|
|