25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: dev_ns16550.c,v 1.40 2005/08/12 06:15:31 debug Exp $ |
* $Id: dev_ns16550.c,v 1.46 2005/11/23 18:16:42 debug Exp $ |
29 |
* |
* |
30 |
* NS16550 serial controller. |
* NS16550 serial controller. |
31 |
* |
* |
56 |
int addrmult; |
int addrmult; |
57 |
int in_use; |
int in_use; |
58 |
int irqnr; |
int irqnr; |
59 |
|
char *name; |
60 |
int console_handle; |
int console_handle; |
61 |
int enable_fifo; |
int enable_fifo; |
62 |
|
|
63 |
unsigned char reg[DEV_NS16550_LENGTH]; |
unsigned char reg[DEV_NS16550_LENGTH]; |
64 |
unsigned char fcr; /* FIFO control register */ |
unsigned char fcr; /* FIFO control register */ |
65 |
|
int int_asserted; |
66 |
int dlab; /* Divisor Latch Access bit */ |
int dlab; /* Divisor Latch Access bit */ |
67 |
int divisor; |
int divisor; |
68 |
|
|
94 |
if (((d->reg[com_ier] & IER_ETXRDY) && (d->reg[com_iir] & IIR_TXRDY)) || |
if (((d->reg[com_ier] & IER_ETXRDY) && (d->reg[com_iir] & IIR_TXRDY)) || |
95 |
((d->reg[com_ier] & IER_ERXRDY) && (d->reg[com_iir] & IIR_RXRDY))) { |
((d->reg[com_ier] & IER_ERXRDY) && (d->reg[com_iir] & IIR_RXRDY))) { |
96 |
d->reg[com_iir] &= ~IIR_NOPEND; |
d->reg[com_iir] &= ~IIR_NOPEND; |
97 |
if (d->reg[com_mcr] & MCR_IENABLE) |
if (d->reg[com_mcr] & MCR_IENABLE) { |
98 |
cpu_interrupt(cpu, d->irqnr); |
cpu_interrupt(cpu, d->irqnr); |
99 |
|
d->int_asserted = 1; |
100 |
|
} |
101 |
} else { |
} else { |
102 |
d->reg[com_iir] |= IIR_NOPEND; |
d->reg[com_iir] |= IIR_NOPEND; |
103 |
cpu_interrupt_ack(cpu, d->irqnr); |
if (d->int_asserted) |
104 |
|
cpu_interrupt_ack(cpu, d->irqnr); |
105 |
|
d->int_asserted = 0; |
106 |
} |
} |
107 |
} |
} |
108 |
|
|
118 |
int i; |
int i; |
119 |
struct ns_data *d = extra; |
struct ns_data *d = extra; |
120 |
|
|
121 |
idata = memory_readmax64(cpu, data, len); |
if (writeflag == MEM_WRITE) |
122 |
|
idata = memory_readmax64(cpu, data, len); |
123 |
|
|
124 |
|
#if 0 |
125 |
/* The NS16550 should be accessed using byte read/writes: */ |
/* The NS16550 should be accessed using byte read/writes: */ |
126 |
if (len != 1) |
if (len != 1) |
127 |
fatal("[ ns16550: len=%i, idata=0x%16llx! ]\n", |
fatal("[ ns16550 (%s): len=%i, idata=0x%16llx! ]\n", |
128 |
len, (long long)idata); |
d->name, len, (long long)idata); |
129 |
|
#endif |
130 |
|
|
131 |
/* |
/* |
132 |
* Always ready to transmit: |
* Always ready to transmit: |
145 |
relative_addr /= d->addrmult; |
relative_addr /= d->addrmult; |
146 |
|
|
147 |
if (relative_addr >= DEV_NS16550_LENGTH) { |
if (relative_addr >= DEV_NS16550_LENGTH) { |
148 |
fatal("[ ns16550: outside register space? relative_addr=" |
fatal("[ ns16550 (%s): outside register space? relative_addr=" |
149 |
"0x%llx. bad addrmult? bad device length? ]\n", |
"0x%llx. bad addrmult? bad device length? ]\n", d->name, |
150 |
(long long)relative_addr); |
(long long)relative_addr); |
151 |
return 0; |
return 0; |
152 |
} |
} |
166 |
|
|
167 |
/* Read/write of data: */ |
/* Read/write of data: */ |
168 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
169 |
if (d->reg[com_mcr] & MCR_LOOPBACK) |
if (d->reg[com_mcr] & MCR_LOOPBACK) { |
170 |
console_makeavail(d->console_handle, idata); |
console_makeavail(d->console_handle, idata); |
171 |
else |
} else { |
172 |
console_putchar(d->console_handle, idata); |
console_putchar(d->console_handle, idata); |
173 |
|
if (console_are_slaves_allowed()) |
174 |
|
d->in_use = 1; |
175 |
|
} |
176 |
d->reg[com_iir] |= IIR_TXRDY; |
d->reg[com_iir] |= IIR_TXRDY; |
177 |
} else { |
} else { |
178 |
if (d->in_use) |
if (d->in_use) |
189 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
190 |
/* Set the high byte of the divisor: */ |
/* Set the high byte of the divisor: */ |
191 |
d->divisor = (d->divisor & 0xff) | (idata << 8); |
d->divisor = (d->divisor & 0xff) | (idata << 8); |
192 |
debug("[ ns16550: speed set to %i bps ]\n", |
debug("[ ns16550 (%s): speed set to %i bps ]\n", |
193 |
(int)(115200 / d->divisor)); |
d->name, (int)(115200 / d->divisor)); |
194 |
} else |
} else |
195 |
odata = d->divisor >> 8; |
odata = d->divisor >> 8; |
196 |
break; |
break; |
200 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
201 |
/* This is to supress Linux' behaviour */ |
/* This is to supress Linux' behaviour */ |
202 |
if (idata != 0) |
if (idata != 0) |
203 |
debug("[ ns16550: write to ier: 0x%02x ]\n", |
debug("[ ns16550 (%s): write to ier: 0x%02x ]" |
204 |
(int)idata); |
"\n", d->name, (int)idata); |
205 |
|
|
206 |
/* Needed for NetBSD 2.0.x, but not 1.6.2? */ |
/* Needed for NetBSD 2.0.x, but not 1.6.2? */ |
207 |
if (!(d->reg[com_ier] & IER_ETXRDY) |
if (!(d->reg[com_ier] & IER_ETXRDY) |
216 |
|
|
217 |
case com_iir: /* interrupt identification (r), fifo control (w) */ |
case com_iir: /* interrupt identification (r), fifo control (w) */ |
218 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
219 |
debug("[ ns16550: write to fifo control: 0x%02x ]\n", |
debug("[ ns16550 (%s): write to fifo control: 0x%02x ]" |
220 |
(int)idata); |
"\n", d->name, (int)idata); |
221 |
d->fcr = idata; |
d->fcr = idata; |
222 |
} else { |
} else { |
223 |
odata = d->reg[com_iir]; |
odata = d->reg[com_iir]; |
224 |
debug("[ ns16550: read from iir: 0x%02x ]\n", |
debug("[ ns16550 (%s): read from iir: 0x%02x ]\n", |
225 |
(int)odata); |
d->name, (int)odata); |
226 |
dev_ns16550_tick(cpu, d); |
dev_ns16550_tick(cpu, d); |
227 |
} |
} |
228 |
break; |
break; |
229 |
|
|
230 |
case com_lsr: |
case com_lsr: |
231 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
232 |
debug("[ ns16550: write to lsr: 0x%02x ]\n", |
debug("[ ns16550 (%s): write to lsr: 0x%02x ]\n", |
233 |
(int)idata); |
d->name, (int)idata); |
234 |
d->reg[com_lsr] = idata; |
d->reg[com_lsr] = idata; |
235 |
} else { |
} else { |
236 |
odata = d->reg[com_lsr]; |
odata = d->reg[com_lsr]; |
237 |
/* debug("[ ns16550: read from lsr: 0x%02x ]\n", |
/* debug("[ ns16550 (%s): read from lsr: 0x%02x ]\n", |
238 |
(int)odata); */ |
d->name, (int)odata); */ |
239 |
} |
} |
240 |
break; |
break; |
241 |
|
|
242 |
case com_msr: |
case com_msr: |
243 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
244 |
debug("[ ns16550: write to msr: 0x%02x ]\n", |
debug("[ ns16550 (%s): write to msr: 0x%02x ]\n", |
245 |
(int)idata); |
d->name, (int)idata); |
246 |
d->reg[com_msr] = idata; |
d->reg[com_msr] = idata; |
247 |
} else { |
} else { |
248 |
odata = d->reg[com_msr]; |
odata = d->reg[com_msr]; |
249 |
debug("[ ns16550: read from msr: 0x%02x ]\n", |
debug("[ ns16550 (%s): read from msr: 0x%02x ]\n", |
250 |
(int)odata); |
d->name, (int)odata); |
251 |
} |
} |
252 |
break; |
break; |
253 |
|
|
277 |
|
|
278 |
d->dlab = idata & 0x80? 1 : 0; |
d->dlab = idata & 0x80? 1 : 0; |
279 |
|
|
280 |
debug("[ ns16550: write to lctl: 0x%02x (%s%s" |
debug("[ ns16550 (%s): write to lctl: 0x%02x (%s%s" |
281 |
"setting mode %i%c%s) ]\n", |
"setting mode %i%c%s) ]\n", d->name, (int)idata, |
|
(int)idata, |
|
282 |
d->dlab? "Divisor Latch access, " : "", |
d->dlab? "Divisor Latch access, " : "", |
283 |
idata&0x40? "sending BREAK, " : "", |
idata&0x40? "sending BREAK, " : "", |
284 |
d->databits, d->parity, d->stopbits); |
d->databits, d->parity, d->stopbits); |
285 |
} else { |
} else { |
286 |
odata = d->reg[com_lctl]; |
odata = d->reg[com_lctl]; |
287 |
debug("[ ns16550: read from lctl: 0x%02x ]\n", |
debug("[ ns16550 (%s): read from lctl: 0x%02x ]\n", |
288 |
(int)odata); |
d->name, (int)odata); |
289 |
} |
} |
290 |
break; |
break; |
291 |
|
|
292 |
case com_mcr: |
case com_mcr: |
293 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
294 |
d->reg[com_mcr] = idata; |
d->reg[com_mcr] = idata; |
295 |
debug("[ ns16550: write to mcr: 0x%02x ]\n", |
debug("[ ns16550 (%s): write to mcr: 0x%02x ]\n", |
296 |
(int)idata); |
d->name, (int)idata); |
297 |
} else { |
} else { |
298 |
odata = d->reg[com_mcr]; |
odata = d->reg[com_mcr]; |
299 |
debug("[ ns16550: read from mcr: 0x%02x ]\n", |
debug("[ ns16550 (%s): read from mcr: 0x%02x ]\n", |
300 |
(int)odata); |
d->name, (int)odata); |
301 |
} |
} |
302 |
break; |
break; |
303 |
|
|
304 |
default: |
default: |
305 |
if (writeflag==MEM_READ) { |
if (writeflag==MEM_READ) { |
306 |
debug("[ ns16550: read from reg %i ]\n", |
debug("[ ns16550 (%s): read from reg %i ]\n", |
307 |
(int)relative_addr); |
d->name, (int)relative_addr); |
308 |
odata = d->reg[relative_addr]; |
odata = d->reg[relative_addr]; |
309 |
} else { |
} else { |
310 |
debug("[ ns16550: write to reg %i:", |
debug("[ ns16550 (%s): write to reg %i:", |
311 |
(int)relative_addr); |
d->name, (int)relative_addr); |
312 |
for (i=0; i<len; i++) |
for (i=0; i<len; i++) |
313 |
debug(" %02x", data[i]); |
debug(" %02x", data[i]); |
314 |
debug(" ]\n"); |
debug(" ]\n"); |
337 |
exit(1); |
exit(1); |
338 |
} |
} |
339 |
memset(d, 0, sizeof(struct ns_data)); |
memset(d, 0, sizeof(struct ns_data)); |
340 |
d->irqnr = devinit->irq_nr; |
d->irqnr = devinit->irq_nr; |
341 |
d->addrmult = devinit->addr_mult; |
d->addrmult = devinit->addr_mult; |
342 |
d->in_use = devinit->in_use; |
d->in_use = devinit->in_use; |
343 |
d->enable_fifo = 1; |
d->enable_fifo = 1; |
344 |
d->dlab = 0; |
d->dlab = 0; |
345 |
d->divisor = 115200 / 9600; |
d->divisor = 115200 / 9600; |
346 |
d->databits = 8; |
d->databits = 8; |
347 |
d->parity = 'N'; |
d->parity = 'N'; |
348 |
d->stopbits = "1"; |
d->stopbits = "1"; |
349 |
|
d->name = devinit->name2 != NULL? devinit->name2 : ""; |
350 |
d->console_handle = |
d->console_handle = |
351 |
console_start_slave(devinit->machine, devinit->name); |
console_start_slave(devinit->machine, devinit->name); |
352 |
|
|
365 |
|
|
366 |
memory_device_register(devinit->machine->memory, name, devinit->addr, |
memory_device_register(devinit->machine->memory, name, devinit->addr, |
367 |
DEV_NS16550_LENGTH * d->addrmult, dev_ns16550_access, d, |
DEV_NS16550_LENGTH * d->addrmult, dev_ns16550_access, d, |
368 |
MEM_DEFAULT, NULL); |
DM_DEFAULT, NULL); |
369 |
machine_add_tickfunction(devinit->machine, |
machine_add_tickfunction(devinit->machine, |
370 |
dev_ns16550_tick, d, TICK_SHIFT); |
dev_ns16550_tick, d, TICK_SHIFT); |
371 |
|
|