25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: dev_ns16550.c,v 1.32 2005/02/19 11:51:33 debug Exp $ |
* $Id: dev_ns16550.c,v 1.42 2005/10/26 14:37:04 debug Exp $ |
29 |
* |
* |
30 |
* NS16550 serial controller. |
* NS16550 serial controller. |
31 |
* |
* |
32 |
* TODO: actually implement the fifo :) |
* |
33 |
|
* TODO: Implement the FIFO. |
34 |
*/ |
*/ |
35 |
|
|
36 |
#include <stdio.h> |
#include <stdio.h> |
39 |
|
|
40 |
#include "console.h" |
#include "console.h" |
41 |
#include "cpu.h" |
#include "cpu.h" |
42 |
#include "devices.h" |
#include "device.h" |
43 |
#include "machine.h" |
#include "machine.h" |
44 |
#include "memory.h" |
#include "memory.h" |
45 |
#include "misc.h" |
#include "misc.h" |
47 |
#include "comreg.h" |
#include "comreg.h" |
48 |
|
|
49 |
|
|
50 |
/* #define debug fatal */ |
/* #define debug fatal */ |
|
|
|
|
#define NS16550_TICK_SHIFT 14 |
|
|
|
|
|
/* #define DISABLE_FIFO */ |
|
51 |
|
|
52 |
|
#define TICK_SHIFT 14 |
53 |
|
#define DEV_NS16550_LENGTH 8 |
54 |
|
|
55 |
struct ns_data { |
struct ns_data { |
56 |
int reg[8]; |
int addrmult; |
57 |
|
int in_use; |
58 |
int irqnr; |
int irqnr; |
59 |
|
char *name; |
60 |
int console_handle; |
int console_handle; |
61 |
|
int enable_fifo; |
62 |
|
|
63 |
|
unsigned char reg[DEV_NS16550_LENGTH]; |
64 |
|
unsigned char fcr; /* FIFO control register */ |
65 |
|
|
|
int irq_enable; |
|
|
int addrmult; |
|
|
int in_use; |
|
66 |
int dlab; /* Divisor Latch Access bit */ |
int dlab; /* Divisor Latch Access bit */ |
67 |
int divisor; |
int divisor; |
68 |
|
|
69 |
int databits; |
int databits; |
70 |
char parity; |
char parity; |
71 |
const char *stopbits; |
const char *stopbits; |
74 |
|
|
75 |
/* |
/* |
76 |
* dev_ns16550_tick(): |
* dev_ns16550_tick(): |
77 |
|
* |
78 |
|
* This function is called at regular intervals. An interrupt is caused to the |
79 |
|
* CPU if there is a character available for reading, or if the transmitter |
80 |
|
* slot is empty (i.e. the ns16550 is ready to transmit). |
81 |
*/ |
*/ |
82 |
void dev_ns16550_tick(struct cpu *cpu, void *extra) |
void dev_ns16550_tick(struct cpu *cpu, void *extra) |
83 |
{ |
{ |
84 |
struct ns_data *d = extra; |
struct ns_data *d = extra; |
85 |
|
|
|
d->reg[com_iir] |= IIR_NOPEND; |
|
|
cpu_interrupt_ack(cpu, d->irqnr); |
|
|
|
|
86 |
d->reg[com_iir] &= ~IIR_RXRDY; |
d->reg[com_iir] &= ~IIR_RXRDY; |
87 |
if (d->in_use) { |
if (d->in_use && console_charavail(d->console_handle)) |
88 |
if (console_charavail(d->console_handle)) |
d->reg[com_iir] |= IIR_RXRDY; |
|
d->reg[com_iir] |= IIR_RXRDY; |
|
|
} |
|
89 |
|
|
90 |
if ((d->irq_enable & IER_ETXRDY && d->reg[com_iir] & IIR_TXRDY) || |
/* |
91 |
(d->irq_enable & IER_ERXRDY && d->reg[com_iir] & IIR_RXRDY)) { |
* If interrupts are enabled, and interrupts are pending, then |
92 |
|
* cause a CPU interrupt. |
93 |
|
*/ |
94 |
|
if (((d->reg[com_ier] & IER_ETXRDY) && (d->reg[com_iir] & IIR_TXRDY)) || |
95 |
|
((d->reg[com_ier] & IER_ERXRDY) && (d->reg[com_iir] & IIR_RXRDY))) { |
96 |
d->reg[com_iir] &= ~IIR_NOPEND; |
d->reg[com_iir] &= ~IIR_NOPEND; |
97 |
if (d->reg[com_mcr] & MCR_IENABLE) |
if (d->reg[com_mcr] & MCR_IENABLE) |
98 |
cpu_interrupt(cpu, d->irqnr); |
cpu_interrupt(cpu, d->irqnr); |
99 |
|
} else { |
100 |
|
d->reg[com_iir] |= IIR_NOPEND; |
101 |
|
cpu_interrupt_ack(cpu, d->irqnr); |
102 |
} |
} |
103 |
} |
} |
104 |
|
|
114 |
int i; |
int i; |
115 |
struct ns_data *d = extra; |
struct ns_data *d = extra; |
116 |
|
|
117 |
idata = memory_readmax64(cpu, data, len); |
if (writeflag == MEM_WRITE) |
118 |
|
idata = memory_readmax64(cpu, data, len); |
119 |
|
|
120 |
/* Always ready to transmit: */ |
/* The NS16550 should be accessed using byte read/writes: */ |
121 |
|
if (len != 1) |
122 |
|
fatal("[ ns16550 (%s): len=%i, idata=0x%16llx! ]\n", |
123 |
|
d->name, len, (long long)idata); |
124 |
|
|
125 |
|
/* |
126 |
|
* Always ready to transmit: |
127 |
|
*/ |
128 |
d->reg[com_lsr] |= LSR_TXRDY | LSR_TSRE; |
d->reg[com_lsr] |= LSR_TXRDY | LSR_TSRE; |
129 |
d->reg[com_lsr] &= ~LSR_RXRDY; |
d->reg[com_msr] |= MSR_DCD | MSR_DSR | MSR_CTS; |
|
d->reg[com_msr] = MSR_DCD | MSR_DSR | MSR_CTS; |
|
130 |
|
|
131 |
#ifdef DISABLE_FIFO |
d->reg[com_iir] &= ~0xf0; |
132 |
/* FIFO turned off: */ |
if (d->enable_fifo) |
133 |
d->reg[com_iir] &= 0x0f; |
d->reg[com_iir] |= ((d->fcr << 5) & 0xc0); |
134 |
#endif |
|
135 |
|
d->reg[com_lsr] &= ~LSR_RXRDY; |
136 |
if (d->in_use) { |
if (d->in_use && console_charavail(d->console_handle)) |
137 |
if (console_charavail(d->console_handle)) { |
d->reg[com_lsr] |= LSR_RXRDY; |
|
d->reg[com_lsr] |= LSR_RXRDY; |
|
|
} |
|
|
} |
|
138 |
|
|
139 |
relative_addr /= d->addrmult; |
relative_addr /= d->addrmult; |
140 |
|
|
141 |
|
if (relative_addr >= DEV_NS16550_LENGTH) { |
142 |
|
fatal("[ ns16550 (%s): outside register space? relative_addr=" |
143 |
|
"0x%llx. bad addrmult? bad device length? ]\n", d->name, |
144 |
|
(long long)relative_addr); |
145 |
|
return 0; |
146 |
|
} |
147 |
|
|
148 |
switch (relative_addr) { |
switch (relative_addr) { |
149 |
case com_data: /* com_data or com_dlbl */ |
|
150 |
|
case com_data: /* data AND low byte of the divisor */ |
151 |
/* Read/write of the Divisor value: */ |
/* Read/write of the Divisor value: */ |
152 |
if (d->dlab) { |
if (d->dlab) { |
153 |
if (writeflag == MEM_WRITE) { |
/* Write or read the low byte of the divisor: */ |
154 |
/* Set the low byte of the divisor: */ |
if (writeflag == MEM_WRITE) |
155 |
d->divisor &= ~0xff; |
d->divisor = (d->divisor & 0xff00) | idata; |
156 |
d->divisor |= (idata & 0xff); |
else |
|
} else { |
|
157 |
odata = d->divisor & 0xff; |
odata = d->divisor & 0xff; |
|
} |
|
158 |
break; |
break; |
159 |
} |
} |
160 |
|
|
161 |
/* Read write of data: */ |
/* Read/write of data: */ |
162 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
163 |
if (d->reg[com_mcr] & MCR_LOOPBACK) { |
if (d->reg[com_mcr] & MCR_LOOPBACK) |
164 |
console_makeavail(d->console_handle, idata); |
console_makeavail(d->console_handle, idata); |
165 |
} else { |
else |
|
#if 0 |
|
|
/* Ugly hack: don't show form feeds: */ |
|
|
if (idata != 12) |
|
|
#endif |
|
166 |
console_putchar(d->console_handle, idata); |
console_putchar(d->console_handle, idata); |
|
} |
|
|
|
|
167 |
d->reg[com_iir] |= IIR_TXRDY; |
d->reg[com_iir] |= IIR_TXRDY; |
|
dev_ns16550_tick(cpu, d); |
|
|
return 1; |
|
168 |
} else { |
} else { |
169 |
if (d->in_use) |
if (d->in_use) |
170 |
odata = console_readchar(d->console_handle); |
odata = console_readchar(d->console_handle); |
171 |
else |
else |
172 |
odata = 0; |
odata = 0; |
|
dev_ns16550_tick(cpu, d); |
|
173 |
} |
} |
174 |
|
dev_ns16550_tick(cpu, d); |
175 |
break; |
break; |
176 |
|
|
177 |
case com_ier: /* interrupt enable AND high byte of the divisor */ |
case com_ier: /* interrupt enable AND high byte of the divisor */ |
178 |
/* Read/write of the Divisor value: */ |
/* Read/write of the Divisor value: */ |
179 |
if (d->dlab) { |
if (d->dlab) { |
180 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
181 |
/* Set the high byte of the divisor: */ |
/* Set the high byte of the divisor: */ |
182 |
d->divisor &= ~0xff00; |
d->divisor = (d->divisor & 0xff) | (idata << 8); |
183 |
d->divisor |= ((idata & 0xff) << 8); |
debug("[ ns16550 (%s): speed set to %i bps ]\n", |
184 |
debug("[ ns16550 speed set to %i bps ]\n", |
d->name, (int)(115200 / d->divisor)); |
185 |
115200 / d->divisor); |
} else |
186 |
} else { |
odata = d->divisor >> 8; |
|
odata = (d->divisor & 0xff00) >> 8; |
|
|
} |
|
187 |
break; |
break; |
188 |
} |
} |
189 |
|
|
191 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
192 |
/* This is to supress Linux' behaviour */ |
/* This is to supress Linux' behaviour */ |
193 |
if (idata != 0) |
if (idata != 0) |
194 |
debug("[ ns16550 write to ier: 0x%02x ]\n", |
debug("[ ns16550 (%s): write to ier: 0x%02x ]" |
195 |
idata); |
"\n", d->name, (int)idata); |
196 |
|
|
197 |
/* Needed for NetBSD 2.0, but not 1.6.2? */ |
/* Needed for NetBSD 2.0.x, but not 1.6.2? */ |
198 |
if (!(d->irq_enable & IER_ETXRDY) |
if (!(d->reg[com_ier] & IER_ETXRDY) |
199 |
&& (idata & IER_ETXRDY)) |
&& (idata & IER_ETXRDY)) |
200 |
d->reg[com_iir] |= IIR_TXRDY; |
d->reg[com_iir] |= IIR_TXRDY; |
201 |
|
|
202 |
d->irq_enable = idata; |
d->reg[com_ier] = idata; |
203 |
dev_ns16550_tick(cpu, d); |
dev_ns16550_tick(cpu, d); |
204 |
} else { |
} else |
205 |
odata = d->reg[relative_addr]; |
odata = d->reg[com_ier]; |
|
} |
|
206 |
break; |
break; |
207 |
|
|
208 |
case com_iir: /* interrupt identification (r), fifo control (w) */ |
case com_iir: /* interrupt identification (r), fifo control (w) */ |
209 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
210 |
debug("[ ns16550 write to fifo control ]\n"); |
debug("[ ns16550 (%s): write to fifo control: 0x%02x ]" |
211 |
d->reg[relative_addr] = idata; |
"\n", d->name, (int)idata); |
212 |
|
d->fcr = idata; |
213 |
} else { |
} else { |
214 |
odata = d->reg[relative_addr]; |
odata = d->reg[com_iir]; |
215 |
debug("[ ns16550 read from iir: 0x%02x ]\n", odata); |
debug("[ ns16550 (%s): read from iir: 0x%02x ]\n", |
216 |
|
d->name, (int)odata); |
217 |
dev_ns16550_tick(cpu, d); |
dev_ns16550_tick(cpu, d); |
218 |
} |
} |
219 |
break; |
break; |
220 |
|
|
221 |
case com_lsr: |
case com_lsr: |
222 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
223 |
debug("[ ns16550 write to lsr ]\n"); |
debug("[ ns16550 (%s): write to lsr: 0x%02x ]\n", |
224 |
d->reg[relative_addr] = idata; |
d->name, (int)idata); |
225 |
|
d->reg[com_lsr] = idata; |
226 |
} else { |
} else { |
227 |
odata = d->reg[relative_addr]; |
odata = d->reg[com_lsr]; |
228 |
|
/* debug("[ ns16550 (%s): read from lsr: 0x%02x ]\n", |
229 |
|
d->name, (int)odata); */ |
230 |
} |
} |
231 |
break; |
break; |
232 |
|
|
233 |
case com_msr: |
case com_msr: |
234 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
235 |
debug("[ ns16550 write to msr ]\n"); |
debug("[ ns16550 (%s): write to msr: 0x%02x ]\n", |
236 |
d->reg[relative_addr] = idata; |
d->name, (int)idata); |
237 |
|
d->reg[com_msr] = idata; |
238 |
} else { |
} else { |
239 |
odata = d->reg[relative_addr]; |
odata = d->reg[com_msr]; |
240 |
|
debug("[ ns16550 (%s): read from msr: 0x%02x ]\n", |
241 |
|
d->name, (int)odata); |
242 |
} |
} |
243 |
break; |
break; |
244 |
|
|
245 |
case com_lctl: |
case com_lctl: |
246 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
247 |
d->reg[relative_addr] = idata; |
d->reg[com_lctl] = idata; |
248 |
switch (idata & 0x7) { |
switch (idata & 0x7) { |
249 |
case 0: d->databits = 5; d->stopbits = "1"; break; |
case 0: d->databits = 5; d->stopbits = "1"; break; |
250 |
case 1: d->databits = 6; d->stopbits = "1"; break; |
case 1: d->databits = 6; d->stopbits = "1"; break; |
268 |
|
|
269 |
d->dlab = idata & 0x80? 1 : 0; |
d->dlab = idata & 0x80? 1 : 0; |
270 |
|
|
271 |
debug("[ ns16550 write to lctl: 0x%02x (%s%s" |
debug("[ ns16550 (%s): write to lctl: 0x%02x (%s%s" |
272 |
"setting mode %i%c%s) ]\n", |
"setting mode %i%c%s) ]\n", d->name, (int)idata, |
|
(int)idata, |
|
273 |
d->dlab? "Divisor Latch access, " : "", |
d->dlab? "Divisor Latch access, " : "", |
274 |
idata&0x40? "sending BREAK, " : "", |
idata&0x40? "sending BREAK, " : "", |
275 |
d->databits, d->parity, d->stopbits); |
d->databits, d->parity, d->stopbits); |
276 |
} else { |
} else { |
277 |
odata = d->reg[relative_addr]; |
odata = d->reg[com_lctl]; |
278 |
debug("[ ns16550 read from lctl: 0x%02x ]\n", odata); |
debug("[ ns16550 (%s): read from lctl: 0x%02x ]\n", |
279 |
|
d->name, (int)odata); |
280 |
} |
} |
281 |
break; |
break; |
282 |
|
|
283 |
case com_mcr: |
case com_mcr: |
284 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
285 |
d->reg[relative_addr] = idata; |
d->reg[com_mcr] = idata; |
286 |
debug("[ ns16550 write to mcr: 0x%02x ]\n", idata); |
debug("[ ns16550 (%s): write to mcr: 0x%02x ]\n", |
287 |
|
d->name, (int)idata); |
288 |
} else { |
} else { |
289 |
odata = d->reg[relative_addr]; |
odata = d->reg[com_mcr]; |
290 |
debug("[ ns16550 read from mcr: 0x%02x ]\n", odata); |
debug("[ ns16550 (%s): read from mcr: 0x%02x ]\n", |
291 |
|
d->name, (int)odata); |
292 |
} |
} |
293 |
break; |
break; |
294 |
|
|
295 |
default: |
default: |
296 |
if (writeflag==MEM_READ) { |
if (writeflag==MEM_READ) { |
297 |
debug("[ ns16550 read from reg %i ]\n", |
debug("[ ns16550 (%s): read from reg %i ]\n", |
298 |
(int)relative_addr); |
d->name, (int)relative_addr); |
299 |
odata = d->reg[relative_addr]; |
odata = d->reg[relative_addr]; |
300 |
} else { |
} else { |
301 |
debug("[ ns16550 write to reg %i:", |
debug("[ ns16550 (%s): write to reg %i:", |
302 |
(int)relative_addr); |
d->name, (int)relative_addr); |
303 |
for (i=0; i<len; i++) |
for (i=0; i<len; i++) |
304 |
debug(" %02x", data[i]); |
debug(" %02x", data[i]); |
305 |
debug(" ]\n"); |
debug(" ]\n"); |
315 |
|
|
316 |
|
|
317 |
/* |
/* |
318 |
* dev_ns16550_init(): |
* devinit_ns16550(): |
319 |
*/ |
*/ |
320 |
int dev_ns16550_init(struct machine *machine, struct memory *mem, |
int devinit_ns16550(struct devinit *devinit) |
|
uint64_t baseaddr, int irq_nr, int addrmult, int in_use, |
|
|
char *name) |
|
321 |
{ |
{ |
322 |
struct ns_data *d; |
struct ns_data *d = malloc(sizeof(struct ns_data)); |
323 |
char *name2; |
size_t nlen; |
324 |
|
char *name; |
325 |
|
|
|
d = malloc(sizeof(struct ns_data)); |
|
326 |
if (d == NULL) { |
if (d == NULL) { |
327 |
fprintf(stderr, "out of memory\n"); |
fprintf(stderr, "out of memory\n"); |
328 |
exit(1); |
exit(1); |
329 |
} |
} |
330 |
memset(d, 0, sizeof(struct ns_data)); |
memset(d, 0, sizeof(struct ns_data)); |
331 |
d->irqnr = irq_nr; |
d->irqnr = devinit->irq_nr; |
332 |
d->addrmult = addrmult; |
d->addrmult = devinit->addr_mult; |
333 |
d->in_use = in_use; |
d->in_use = devinit->in_use; |
334 |
d->dlab = 0; |
d->enable_fifo = 1; |
335 |
d->divisor = 115200 / 9600; |
d->dlab = 0; |
336 |
d->databits = 8; |
d->divisor = 115200 / 9600; |
337 |
d->parity = 'N'; |
d->databits = 8; |
338 |
d->stopbits = "1"; |
d->parity = 'N'; |
339 |
d->console_handle = console_start_slave(machine, name); |
d->stopbits = "1"; |
340 |
|
d->name = devinit->name2 != NULL? devinit->name2 : ""; |
341 |
name2 = malloc(strlen(name) + 20); |
d->console_handle = |
342 |
if (name2 == NULL) { |
console_start_slave(devinit->machine, devinit->name); |
343 |
fprintf(stderr, "out of memory in dev_ns16550_init()\n"); |
|
344 |
|
nlen = strlen(devinit->name) + 10; |
345 |
|
if (devinit->name2 != NULL) |
346 |
|
nlen += strlen(devinit->name2); |
347 |
|
name = malloc(nlen); |
348 |
|
if (name == NULL) { |
349 |
|
fprintf(stderr, "out of memory\n"); |
350 |
exit(1); |
exit(1); |
351 |
} |
} |
352 |
if (name != NULL && name[0]) |
if (devinit->name2 != NULL && devinit->name2[0]) |
353 |
sprintf(name2, "ns16550 [%s]", name); |
snprintf(name, nlen, "%s [%s]", devinit->name, devinit->name2); |
354 |
else |
else |
355 |
sprintf(name2, "ns16550"); |
snprintf(name, nlen, "%s", devinit->name); |
356 |
|
|
357 |
memory_device_register(mem, name2, baseaddr, |
memory_device_register(devinit->machine->memory, name, devinit->addr, |
358 |
DEV_NS16550_LENGTH * addrmult, dev_ns16550_access, d, |
DEV_NS16550_LENGTH * d->addrmult, dev_ns16550_access, d, |
359 |
MEM_DEFAULT, NULL); |
MEM_DEFAULT, NULL); |
360 |
machine_add_tickfunction(machine, dev_ns16550_tick, |
machine_add_tickfunction(devinit->machine, |
361 |
d, NS16550_TICK_SHIFT); |
dev_ns16550_tick, d, TICK_SHIFT); |
362 |
|
|
363 |
|
/* |
364 |
|
* NOTE: Ugly cast into a pointer, because this is a convenient way |
365 |
|
* to return the console handle to code in src/machine.c. |
366 |
|
*/ |
367 |
|
devinit->return_ptr = (void *)(size_t)d->console_handle; |
368 |
|
|
369 |
return d->console_handle; |
return 1; |
370 |
} |
} |
371 |
|
|