src/devices/dev_mpc40x.c

/*
 *  Copyright (C) 2005-2007  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *   
 *
 *  $Id: dev_mpc40x.c,v 1.12 2007/06/15 18:13:04 debug Exp $
 *
 *  COMMENT: IBM MPC40X bridge (PCI and interrupt controller)
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "bus_pci.h"
#include "cpu.h"
#include "device.h"
#include "interrupt.h"
#include "machine.h"
#include "memory.h"
#include "misc.h"

#include "mpc40xreg.h"


struct mpc40x_data {
        struct interrupt ppc_irq;       /*  Connected to the CPU  */

        uint32_t        sr;             /*  Interrupt Status register  */
        uint32_t        er;             /*  Interrupt Enable register  */

        struct pci_data *pci_data;      /*  PCI bus  */
};


void mpc40x_interrupt_assert(struct interrupt *interrupt)
{
        struct mpc40x_data *d = interrupt->extra;
        d->sr |= interrupt->line;
        if (d->sr & d->er)
                INTERRUPT_ASSERT(d->ppc_irq);
}
void mpc40x_interrupt_deassert(struct interrupt *interrupt)
{
        struct mpc40x_data *d = interrupt->extra;
        d->sr &= ~interrupt->line;
        if (!(d->sr & d->er))
                INTERRUPT_DEASSERT(d->ppc_irq);
}


/*
 *  dev_mpc40x_pci_access():
 *
 *  Passes PCI indirect addr and data accesses onto bus_pci.
 */
DEVICE_ACCESS(mpc40x_pci)
{
        uint64_t idata = 0, odata = 0;
        int bus, dev, func, reg;
        struct mpc40x_data *d = extra;

        if (writeflag == MEM_WRITE)
                idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN);

        switch (relative_addr) {
        case 0: /*  Address:  */
                bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
                bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
                break;

        case 4: /*  Data:  */
                bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
                    &odata : &idata, len, writeflag);
                break;
        }

        if (writeflag == MEM_READ)
                memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata);

        return 1;
}


/*
 *  dev_mpc40x_int_access():
 *
 *  The interrupt controller.
 */
DEVICE_ACCESS(mpc40x_int)
{
        struct mpc40x_data *d = extra;
        uint64_t idata = 0, odata = 0;

        if (writeflag == MEM_WRITE)
                idata = memory_readmax64(cpu, data, len);

        switch (relative_addr) {

        case MPC_UIC_SR:
                /*  Status register (cleared by writing ones):  */
                if (writeflag == MEM_READ) {
                        odata = d->sr;
                } else {
                        d->sr &= ~idata;
                        if (!(d->sr & d->er))
                                INTERRUPT_DEASSERT(d->ppc_irq);
                }
                break;

        case MPC_UIC_SRS:
                /*  Status register set:  */
                if (writeflag == MEM_READ) {
                        fatal("[ mpc40x_int: read from MPC_UIC_SRS? ]\n");
                        odata = d->sr;
                } else {
                        d->sr = idata;
                        if (d->sr & d->er)
                                INTERRUPT_ASSERT(d->ppc_irq);
                        else
                                INTERRUPT_DEASSERT(d->ppc_irq);
                }
                break;

        case MPC_UIC_ER:
                /*  Enable register:  */
                if (writeflag == MEM_READ) {
                        odata = d->er;
                } else {
                        d->er = idata;
                        if (d->sr & d->er)
                                INTERRUPT_ASSERT(d->ppc_irq);
                        else
                                INTERRUPT_DEASSERT(d->ppc_irq);
                }
                break;

        case MPC_UIC_MSR:
                /*  Masked status:  */
                if (writeflag == MEM_READ) {
                        odata = d->sr & d->er;
                } else {
                        fatal("[ mpc40x_int: write to MPC_UIC_MSR? ]\n");
                }
                break;

        default:if (writeflag == MEM_WRITE) {
                        fatal("[ mpc40x_int: unimplemented write to "
                            "offset 0x%x: data=0x%x ]\n", (int)
                            relative_addr, (int)idata);
                } else {
                        fatal("[ mpc40x_int: unimplemented read from "
                            "offset 0x%x ]\n", (int)relative_addr);
                }
        }

        if (writeflag == MEM_READ)
                memory_writemax64(cpu, data, len, odata);

        return 1;
}


DEVINIT(mpc40x)
{
        struct mpc40x_data *d;
        char tmp[300];
        int i;

        CHECK_ALLOCATION(d = malloc(sizeof(struct mpc40x_data)));
        memset(d, 0, sizeof(struct mpc40x_data));

        /*  Connect to the CPU's interrupt pin:  */
        INTERRUPT_CONNECT(devinit->interrupt_path, d->ppc_irq);

        /*  Register 32 MPC40X interrupts:  */
        for (i=0; i<32; i++) {
                struct interrupt template;
                char n[300];
                snprintf(n, sizeof(n), "%s.mpc40x.%i",
                    devinit->interrupt_path, i);
                memset(&template, 0, sizeof(template));
                template.line = 1 << i;
                template.name = n;
                template.extra = d;
                template.interrupt_assert = mpc40x_interrupt_assert;
                template.interrupt_deassert = mpc40x_interrupt_deassert;
                interrupt_handler_register(&template);
        }

        /*  Register a PCI bus:  */
        snprintf(tmp, sizeof(tmp), "%s.mpc40x", devinit->interrupt_path);
        d->pci_data = bus_pci_init(
            devinit->machine,
            tmp,                /*  pciirq path  */
            0,                  /*  pci device io offset  */
            0,                  /*  pci device mem offset  */
            MPC_PCI_IO_BASE,    /*  PCI portbase  */
            MPC_PCI_MEM_BASE,   /*  PCI membase: TODO  */
            tmp,                /*  PCI irqbase  */
            0,                  /*  ISA portbase: TODO  */
            0,                  /*  ISA membase: TODO  */
            tmp);               /*  ISA irqbase  */

#if 0
        switch (devinit->machine->machine_type) {

        case MACHINE_SANDPOINT:
                bus_pci_add(devinit->machine, d->pci_data,
                    devinit->machine->memory, 0, 0, 0, "sandpoint_pci");
                break;

        default:fatal("!\n! WARNING: mpc40x for non-implemented machine"
                    " type\n!\n");
                exit(1);
        }
#endif

        /*  PCI configuration registers:  */
        memory_device_register(devinit->machine->memory, "mpc40x_pci",
            MPC10X_MAPB_CNFG_DATA, 8, dev_mpc40x_pci_access, d, DM_DEFAULT, NULL);

        /*  Interrupt controller:  */
        memory_device_register(devinit->machine->memory, "mpc40x_int",
            MPC_UIC_BASE, MPC_UIC_SIZE, dev_mpc40x_int_access, d,
            DM_DEFAULT, NULL);

        /*  Two serial ports:  */
        snprintf(tmp, sizeof(tmp), "ns16550 irq=%s.mpc40x.%i addr=0x%llx "
            "name2=tty0", devinit->interrupt_path, 31 - MPC_IB_UART_0,
            (long long)MPC_COM0);
        devinit->machine->main_console_handle = (size_t)
            device_add(devinit->machine, tmp);
#if 0
        snprintf(tmp, sizeof(tmp), "ns16550 irq=%s.mpc40x.%i addr=0x%llx "
            "name2=tty1", devinit->interrupt_path, 31 - MPC_IB_UART_1,
            (long long)MPC_COM1);
        device_add(devinit->machine, tmp);
#endif

        devinit->return_ptr = d->pci_data;

        return 1;
}

1	dpavlin	20	/*
2	dpavlin	34	* Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3	dpavlin	20	*
4			* Redistribution and use in source and binary forms, with or without
5			* modification, are permitted provided that the following conditions are met:
6			*
7			* 1. Redistributions of source code must retain the above copyright
8			* notice, this list of conditions and the following disclaimer.
9			* 2. Redistributions in binary form must reproduce the above copyright
10			* notice, this list of conditions and the following disclaimer in the
11			* documentation and/or other materials provided with the distribution.
12			* 3. The name of the author may not be used to endorse or promote products
13			* derived from this software without specific prior written permission.
14			*
15			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25			* SUCH DAMAGE.
26			*
27			*
28	dpavlin	49	* $Id: dev_mpc40x.c,v 1.12 2007/06/15 18:13:04 debug Exp $
29	dpavlin	42	*
30	dpavlin	49	* COMMENT: IBM MPC40X bridge (PCI and interrupt controller)
31	dpavlin	20	*/
32
33			#include <stdio.h>
34			#include <stdlib.h>
35			#include <string.h>
36
37			#include "bus_pci.h"
38			#include "cpu.h"
39			#include "device.h"
40	dpavlin	42	#include "interrupt.h"
41	dpavlin	20	#include "machine.h"
42			#include "memory.h"
43			#include "misc.h"
44
45	dpavlin	49	#include "mpc40xreg.h"
46	dpavlin	20
47
48	dpavlin	49	struct mpc40x_data {
49	dpavlin	34	struct interrupt ppc_irq; /* Connected to the CPU */
50
51			uint32_t sr; /* Interrupt Status register */
52			uint32_t er; /* Interrupt Enable register */
53
54			struct pci_data pci_data; / PCI bus */
55			};
56
57
58	dpavlin	49	void mpc40x_interrupt_assert(struct interrupt *interrupt)
59	dpavlin	34	{
60	dpavlin	49	struct mpc40x_data *d = interrupt->extra;
61	dpavlin	42	d->sr \|= interrupt->line;
62	dpavlin	34	if (d->sr & d->er)
63			INTERRUPT_ASSERT(d->ppc_irq);
64			}
65	dpavlin	49	void mpc40x_interrupt_deassert(struct interrupt *interrupt)
66	dpavlin	34	{
67	dpavlin	49	struct mpc40x_data *d = interrupt->extra;
68	dpavlin	42	d->sr &= ~interrupt->line;
69	dpavlin	34	if (!(d->sr & d->er))
70			INTERRUPT_DEASSERT(d->ppc_irq);
71			}
72
73
74	dpavlin	20	/*
75	dpavlin	49	* dev_mpc40x_pci_access():
76	dpavlin	20	*
77	dpavlin	22	* Passes PCI indirect addr and data accesses onto bus_pci.
78	dpavlin	20	*/
79	dpavlin	49	DEVICE_ACCESS(mpc40x_pci)
80	dpavlin	20	{
81			uint64_t idata = 0, odata = 0;
82	dpavlin	22	int bus, dev, func, reg;
83	dpavlin	49	struct mpc40x_data *d = extra;
84	dpavlin	20
85			if (writeflag == MEM_WRITE)
86	dpavlin	22	idata = memory_readmax64(cpu, data, len\|MEM_PCI_LITTLE_ENDIAN);
87	dpavlin	20
88	dpavlin	22	switch (relative_addr) {
89			case 0: /* Address: */
90			bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
91			bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
92			break;
93	dpavlin	20
94	dpavlin	22	case 4: /* Data: */
95			bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
96			&odata : &idata, len, writeflag);
97			break;
98			}
99	dpavlin	20
100			if (writeflag == MEM_READ)
101	dpavlin	22	memory_writemax64(cpu, data, len\|MEM_PCI_LITTLE_ENDIAN, odata);
102	dpavlin	20
103			return 1;
104			}
105
106
107			/*
108	dpavlin	49	* dev_mpc40x_int_access():
109	dpavlin	20	*
110			* The interrupt controller.
111			*/
112	dpavlin	49	DEVICE_ACCESS(mpc40x_int)
113	dpavlin	20	{
114	dpavlin	49	struct mpc40x_data *d = extra;
115	dpavlin	20	uint64_t idata = 0, odata = 0;
116
117			if (writeflag == MEM_WRITE)
118			idata = memory_readmax64(cpu, data, len);
119
120			switch (relative_addr) {
121
122	dpavlin	49	case MPC_UIC_SR:
123	dpavlin	20	/* Status register (cleared by writing ones): */
124	dpavlin	34	if (writeflag == MEM_READ) {
125	dpavlin	20	odata = d->sr;
126	dpavlin	34	} else {
127	dpavlin	20	d->sr &= ~idata;
128	dpavlin	34	if (!(d->sr & d->er))
129			INTERRUPT_DEASSERT(d->ppc_irq);
130			}
131	dpavlin	20	break;
132
133	dpavlin	49	case MPC_UIC_SRS:
134	dpavlin	20	/* Status register set: */
135			if (writeflag == MEM_READ) {
136	dpavlin	49	fatal("[ mpc40x_int: read from MPC_UIC_SRS? ]\n");
137	dpavlin	20	odata = d->sr;
138	dpavlin	34	} else {
139	dpavlin	20	d->sr = idata;
140	dpavlin	34	if (d->sr & d->er)
141			INTERRUPT_ASSERT(d->ppc_irq);
142			else
143			INTERRUPT_DEASSERT(d->ppc_irq);
144			}
145	dpavlin	20	break;
146
147	dpavlin	49	case MPC_UIC_ER:
148	dpavlin	20	/* Enable register: */
149	dpavlin	34	if (writeflag == MEM_READ) {
150	dpavlin	20	odata = d->er;
151	dpavlin	34	} else {
152	dpavlin	20	d->er = idata;
153	dpavlin	34	if (d->sr & d->er)
154			INTERRUPT_ASSERT(d->ppc_irq);
155			else
156			INTERRUPT_DEASSERT(d->ppc_irq);
157			}
158	dpavlin	20	break;
159
160	dpavlin	49	case MPC_UIC_MSR:
161	dpavlin	20	/* Masked status: */
162	dpavlin	34	if (writeflag == MEM_READ) {
163	dpavlin	20	odata = d->sr & d->er;
164	dpavlin	34	} else {
165	dpavlin	49	fatal("[ mpc40x_int: write to MPC_UIC_MSR? ]\n");
166	dpavlin	34	}
167	dpavlin	20	break;
168
169			default:if (writeflag == MEM_WRITE) {
170	dpavlin	49	fatal("[ mpc40x_int: unimplemented write to "
171	dpavlin	20	"offset 0x%x: data=0x%x ]\n", (int)
172			relative_addr, (int)idata);
173			} else {
174	dpavlin	49	fatal("[ mpc40x_int: unimplemented read from "
175	dpavlin	20	"offset 0x%x ]\n", (int)relative_addr);
176			}
177			}
178
179			if (writeflag == MEM_READ)
180			memory_writemax64(cpu, data, len, odata);
181
182			return 1;
183			}
184
185
186	dpavlin	49	DEVINIT(mpc40x)
187	dpavlin	20	{
188	dpavlin	49	struct mpc40x_data *d;
189	dpavlin	20	char tmp[300];
190	dpavlin	34	int i;
191	dpavlin	20
192	dpavlin	49	CHECK_ALLOCATION(d = malloc(sizeof(struct mpc40x_data)));
193			memset(d, 0, sizeof(struct mpc40x_data));
194	dpavlin	20
195	dpavlin	34	/* Connect to the CPU's interrupt pin: */
196			INTERRUPT_CONNECT(devinit->interrupt_path, d->ppc_irq);
197
198	dpavlin	49	/* Register 32 MPC40X interrupts: */
199	dpavlin	34	for (i=0; i<32; i++) {
200			struct interrupt template;
201			char n[300];
202	dpavlin	49	snprintf(n, sizeof(n), "%s.mpc40x.%i",
203	dpavlin	34	devinit->interrupt_path, i);
204			memset(&template, 0, sizeof(template));
205	dpavlin	42	template.line = 1 << i;
206	dpavlin	34	template.name = n;
207			template.extra = d;
208	dpavlin	49	template.interrupt_assert = mpc40x_interrupt_assert;
209			template.interrupt_deassert = mpc40x_interrupt_deassert;
210	dpavlin	34	interrupt_handler_register(&template);
211			}
212
213	dpavlin	20	/* Register a PCI bus: */
214	dpavlin	49	snprintf(tmp, sizeof(tmp), "%s.mpc40x", devinit->interrupt_path);
215	dpavlin	20	d->pci_data = bus_pci_init(
216	dpavlin	34	devinit->machine,
217			tmp, /* pciirq path */
218	dpavlin	20	0, /* pci device io offset */
219			0, /* pci device mem offset */
220	dpavlin	49	MPC_PCI_IO_BASE, /* PCI portbase */
221			MPC_PCI_MEM_BASE, /* PCI membase: TODO */
222	dpavlin	34	tmp, /* PCI irqbase */
223	dpavlin	20	0, /* ISA portbase: TODO */
224			0, /* ISA membase: TODO */
225	dpavlin	34	tmp); /* ISA irqbase */
226	dpavlin	20
227	dpavlin	49	#if 0
228	dpavlin	34	switch (devinit->machine->machine_type) {
229
230	dpavlin	49	case MACHINE_SANDPOINT:
231	dpavlin	34	bus_pci_add(devinit->machine, d->pci_data,
232	dpavlin	49	devinit->machine->memory, 0, 0, 0, "sandpoint_pci");
233	dpavlin	20	break;
234	dpavlin	34
235	dpavlin	49	default:fatal("!\n! WARNING: mpc40x for non-implemented machine"
236	dpavlin	20	" type\n!\n");
237			exit(1);
238			}
239	dpavlin	49	#endif
240	dpavlin	20
241			/* PCI configuration registers: */
242	dpavlin	49	memory_device_register(devinit->machine->memory, "mpc40x_pci",
243	dpavlin	52	MPC10X_MAPB_CNFG_DATA, 8, dev_mpc40x_pci_access, d, DM_DEFAULT, NULL);
244	dpavlin	20
245			/* Interrupt controller: */
246	dpavlin	49	memory_device_register(devinit->machine->memory, "mpc40x_int",
247			MPC_UIC_BASE, MPC_UIC_SIZE, dev_mpc40x_int_access, d,
248	dpavlin	34	DM_DEFAULT, NULL);
249	dpavlin	20
250			/* Two serial ports: */
251	dpavlin	49	snprintf(tmp, sizeof(tmp), "ns16550 irq=%s.mpc40x.%i addr=0x%llx "
252			"name2=tty0", devinit->interrupt_path, 31 - MPC_IB_UART_0,
253			(long long)MPC_COM0);
254	dpavlin	34	devinit->machine->main_console_handle = (size_t)
255			device_add(devinit->machine, tmp);
256	dpavlin	49	#if 0
257			snprintf(tmp, sizeof(tmp), "ns16550 irq=%s.mpc40x.%i addr=0x%llx "
258			"name2=tty1", devinit->interrupt_path, 31 - MPC_IB_UART_1,
259			(long long)MPC_COM1);
260			device_add(devinit->machine, tmp);
261			#endif
262	dpavlin	20
263	dpavlin	34	devinit->return_ptr = d->pci_data;
264
265			return 1;
266	dpavlin	20	}
267