/[gxemul]/trunk/src/devices/dev_mpc40x.c
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Annotation of /trunk/src/devices/dev_mpc40x.c

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Revision 42 - (hide annotations)
Mon Oct 8 16:22:32 2007 UTC (16 years, 6 months ago) by dpavlin
Original Path: trunk/src/devices/dev_cpc700.c
File MIME type: text/plain
File size: 7183 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1613 2007/06/15 20:11:26 debug Exp $
20070501	Continuing a little on m88k disassembly (control registers,
		more instructions).
		Adding a dummy mvme88k machine mode.
20070502	Re-adding MIPS load/store alignment exceptions.
20070503	Implementing more of the M88K disassembly code.
20070504	Adding disassembly of some more M88K load/store instructions.
		Implementing some relatively simple M88K instructions (br.n,
		xor[.u] imm, and[.u] imm).
20070505	Implementing M88K three-register and, or, xor, and jmp[.n],
		bsr[.n] including function call trace stuff.
		Applying a patch from Bruce M. Simpson which implements the
		SYSCON_BOARD_CPU_CLOCK_FREQ_ID object of the syscon call in
		the yamon PROM emulation.
20070506	Implementing M88K bb0[.n] and bb1[.n], and skeletons for
		ldcr and stcr (although no control regs are implemented yet).
20070509	Found and fixed the bug which caused Linux for QEMU_MIPS to
		stop working in 0.4.5.1: It was a faulty change to the MIPS
		'sc' and 'scd' instructions I made while going through gcc -W
		warnings on 20070428.
20070510	Updating the Linux/QEMU_MIPS section in guestoses.html to
		use mips-test-0.2.tar.gz instead of 0.1.
		A big thank you to Miod Vallat for sending me M88K manuals.
		Implementing more M88K instructions (addu, subu, div[u], mulu,
		ext[u], clr, set, cmp).
20070511	Fixing bugs in the M88K "and" and "and.u" instructions (found
		by comparing against the manual).
		Implementing more M88K instructions (mask[.u], mak, bcnd (auto-
		generated)) and some more control register details.
		Cleanup: Removing the experimental AVR emulation mode and
		corresponding devices; AVR emulation wasn't really meaningful.
		Implementing autogeneration of most M88K loads/stores. The
		rectangle drawing demo (with -O0) for M88K runs :-)
		Beginning on M88K exception handling.
		More M88K instructions: tb0, tb1, rte, sub, jsr[.n].
		Adding some skeleton MVME PROM ("BUG") emulation.
20070512	Fixing a bug in the M88K cmp instruction.
		Adding the M88K lda (scaled register) instruction.
		Fixing bugs in 64-bit (32-bit pairs) M88K loads/stores.
		Removing the unused tick_hz stuff from the machine struct.
		Implementing the M88K xmem instruction. OpenBSD/mvme88k gets
		far enough to display the Copyright banner :-)
		Implementing subu.co (guess), addu.co, addu.ci, ff0, and ff1.
		Adding a dev_mvme187, for MVME187-specific devices/registers.
		OpenBSD/mvme88k prints more boot messages. :)
20070515	Continuing on MVME187 emulation (adding more devices, beginning
		on the CMMUs, etc).
		Adding the M88K and.c, xor.c, and or.c instructions, and making
		sure that mul, div, etc cause exceptions if executed when SFD1
		is disabled.
20070517	Continuing on M88K and MVME187 emulation in general; moving
		the CMMU registers to the CPU struct, separating dev_pcc2 from
		dev_mvme187, and beginning on memory_m88k.c (BATC and PATC).
		Fixing a bug in 64-bit (32-bit pairs) M88K fast stores.
		Implementing the clock part of dev_mk48txx.
		Implementing the M88K fstcr and xcr instructions.
		Implementing m88k_cpu_tlbdump().
		Beginning on the implementation of a separate address space
		for M88K .usr loads/stores.
20070520	Removing the non-working (skeleton) Sandpoint, SonyNEWS, SHARK
		Dnard, and Zaurus machine modes.
		Experimenting with dyntrans to_be_translated read-ahead. It
		seems to give a very small performance increase for MIPS
		emulation, but a large performance degradation for SuperH. Hm.
20070522	Disabling correct SuperH ITLB emulation; it does not seem to be
		necessary in order to let SH4 guest OSes run, and it slows down
		userspace code.
		Implementing "samepage" branches for SuperH emulation, and some
		other minor speed hacks.
20070525	Continuing on M88K memory-related stuff: exceptions, memory
		transaction register contents, etc.
		Implementing the M88K subu.ci instruction.
		Removing the non-working (skeleton) Iyonix machine mode.
		OpenBSD/mvme88k reaches userland :-), starts executing
		/sbin/init's instructions, and issues a few syscalls, before
		crashing.
20070526	Fixing bugs in dev_mk48txx, so that OpenBSD/mvme88k detects
		the correct time-of-day.
		Implementing a generic IRQ controller for the test machines
		(dev_irqc), similar to a proposed patch from Petr Stepan.
		Experimenting some more with translation read-ahead.
		Adding an "expect" script for automated OpenBSD/landisk
		install regression/performance tests.
20070527	Adding a dummy mmEye (SH3) machine mode skeleton.
		FINALLY found the strange M88K bug I have been hunting: I had
		not emulated the SNIP value for exceptions occurring in
		branch delay slots correctly.
		Implementing correct exceptions for 64-bit M88K loads/stores.
		Address to symbol lookups are now disabled when M88K is
		running in usermode (because usermode addresses don't have
		anything to do with supervisor addresses).
20070531	Removing the mmEye machine mode skeleton.
20070604	Some minor code cleanup.
20070605	Moving src/useremul.c into a subdir (src/useremul/), and
		cleaning up some more legacy constructs.
		Adding -Wstrict-aliasing and -fstrict-aliasing detection to
		the configure script.
20070606	Adding a check for broken GCC on Solaris to the configure
		script. (GCC 3.4.3 on Solaris cannot handle static variables
		which are initialized to 0 or NULL. :-/)
		Removing the old (non-working) ARC emulation modes: NEC RD94,
		R94, R96, and R98, and the last traces of Olivetti M700 and
		Deskstation Tyne.
		Removing the non-working skeleton WDSC device (dev_wdsc).
20070607	Thinking about how to use the host's cc + ld at runtime to
		generate native code. (See experiments/native_cc_ld_test.i
		for an example.)
20070608	Adding a program counter sampling timer, which could be useful
		for native code generation experiments.
		The KN02_CSR_NRMMOD bit in the DECstation 5000/200 (KN02) CSR
		should always be set, to allow a 5000/200 PROM to boot.
20070609	Moving out breakpoint details from the machine struct into
		a helper struct, and removing the limit on max nr of
		breakpoints.
20070610	Moving out tick functions into a helper struct as well (which
		also gets rid of the max limit).
20070612	FINALLY figured out why Debian/DECstation stopped working when
		translation read-ahead was enabled: in src/memory_rw.c, the
		call to invalidate_code_translation was made also if the
		memory access was an instruction load (if the page was mapped
		as writable); it shouldn't be called in that case.
20070613	Implementing some more MIPS32/64 revision 2 instructions: di,
		ei, ext, dext, dextm, dextu, and ins.
20070614	Implementing an instruction combination for the NetBSD/arm
		idle loop (making the host not use any cpu if NetBSD/arm
		inside the emulator is not using any cpu).
		Increasing the nr of ARM VPH entries from 128 to 384.
20070615	Removing the ENABLE_arch stuff from the configure script, so
		that all included architectures are included in both release
		and development builds.
		Moving memory related helper functions from misc.c to memory.c.
		Adding preliminary instructions for netbooting NetBSD/pmppc to
		guestoses.html; it doesn't work yet, there are weird timeouts.
		Beginning a total rewrite of the userland emulation modes
		(removing all emulation modes, beginning from scratch with
		NetBSD/MIPS and FreeBSD/Alpha only).
20070616	After fixing a bug in the DEC21143 NIC (the TDSTAT_OWN bit was
		only cleared for the last segment when transmitting, not all
		segments), NetBSD/pmppc boots with root-on-nfs without the
		timeouts. Updating guestoses.html.
		Removing the skeleton PSP (Playstation Portable) mode.
		Moving X11-related stuff in the machine struct into a helper
		struct.
		Cleanup of out-of-memory checks, to use a new CHECK_ALLOCATION
		macro (which prints a meaningful error message).
		Adding a COMMENT to each machine and device (for automagic
		.index comment generation).
		Doing regression testing for the next release.

==============  RELEASE 0.4.6  ==============


1 dpavlin 20 /*
2 dpavlin 34 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 dpavlin 20 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 42 * $Id: dev_cpc700.c,v 1.12 2007/06/15 18:13:04 debug Exp $
29     *
30     * COMMENT: IBM CPC700 bridge (PCI and interrupt controller)
31 dpavlin 20 */
32    
33     #include <stdio.h>
34     #include <stdlib.h>
35     #include <string.h>
36    
37     #include "bus_pci.h"
38     #include "cpu.h"
39     #include "device.h"
40 dpavlin 42 #include "interrupt.h"
41 dpavlin 20 #include "machine.h"
42     #include "memory.h"
43     #include "misc.h"
44    
45     #include "cpc700reg.h"
46    
47    
48 dpavlin 34 struct cpc700_data {
49     struct interrupt ppc_irq; /* Connected to the CPU */
50    
51     uint32_t sr; /* Interrupt Status register */
52     uint32_t er; /* Interrupt Enable register */
53    
54     struct pci_data *pci_data; /* PCI bus */
55     };
56    
57    
58     void cpc700_interrupt_assert(struct interrupt *interrupt)
59     {
60     struct cpc700_data *d = interrupt->extra;
61 dpavlin 42 d->sr |= interrupt->line;
62 dpavlin 34 if (d->sr & d->er)
63     INTERRUPT_ASSERT(d->ppc_irq);
64     }
65     void cpc700_interrupt_deassert(struct interrupt *interrupt)
66     {
67     struct cpc700_data *d = interrupt->extra;
68 dpavlin 42 d->sr &= ~interrupt->line;
69 dpavlin 34 if (!(d->sr & d->er))
70     INTERRUPT_DEASSERT(d->ppc_irq);
71     }
72    
73    
74 dpavlin 20 /*
75     * dev_cpc700_pci_access():
76     *
77 dpavlin 22 * Passes PCI indirect addr and data accesses onto bus_pci.
78 dpavlin 20 */
79 dpavlin 22 DEVICE_ACCESS(cpc700_pci)
80 dpavlin 20 {
81     uint64_t idata = 0, odata = 0;
82 dpavlin 22 int bus, dev, func, reg;
83 dpavlin 20 struct cpc700_data *d = extra;
84    
85     if (writeflag == MEM_WRITE)
86 dpavlin 22 idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN);
87 dpavlin 20
88 dpavlin 22 switch (relative_addr) {
89     case 0: /* Address: */
90     bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
91     bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
92     break;
93 dpavlin 20
94 dpavlin 22 case 4: /* Data: */
95     bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
96     &odata : &idata, len, writeflag);
97     break;
98     }
99 dpavlin 20
100     if (writeflag == MEM_READ)
101 dpavlin 22 memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata);
102 dpavlin 20
103     return 1;
104     }
105    
106    
107     /*
108     * dev_cpc700_int_access():
109     *
110     * The interrupt controller.
111     */
112 dpavlin 22 DEVICE_ACCESS(cpc700_int)
113 dpavlin 20 {
114     struct cpc700_data *d = extra;
115     uint64_t idata = 0, odata = 0;
116    
117     if (writeflag == MEM_WRITE)
118     idata = memory_readmax64(cpu, data, len);
119    
120     switch (relative_addr) {
121    
122     case CPC_UIC_SR:
123     /* Status register (cleared by writing ones): */
124 dpavlin 34 if (writeflag == MEM_READ) {
125 dpavlin 20 odata = d->sr;
126 dpavlin 34 } else {
127 dpavlin 20 d->sr &= ~idata;
128 dpavlin 34 if (!(d->sr & d->er))
129     INTERRUPT_DEASSERT(d->ppc_irq);
130     }
131 dpavlin 20 break;
132    
133     case CPC_UIC_SRS:
134     /* Status register set: */
135     if (writeflag == MEM_READ) {
136     fatal("[ cpc700_int: read from CPC_UIC_SRS? ]\n");
137     odata = d->sr;
138 dpavlin 34 } else {
139 dpavlin 20 d->sr = idata;
140 dpavlin 34 if (d->sr & d->er)
141     INTERRUPT_ASSERT(d->ppc_irq);
142     else
143     INTERRUPT_DEASSERT(d->ppc_irq);
144     }
145 dpavlin 20 break;
146    
147     case CPC_UIC_ER:
148     /* Enable register: */
149 dpavlin 34 if (writeflag == MEM_READ) {
150 dpavlin 20 odata = d->er;
151 dpavlin 34 } else {
152 dpavlin 20 d->er = idata;
153 dpavlin 34 if (d->sr & d->er)
154     INTERRUPT_ASSERT(d->ppc_irq);
155     else
156     INTERRUPT_DEASSERT(d->ppc_irq);
157     }
158 dpavlin 20 break;
159    
160     case CPC_UIC_MSR:
161     /* Masked status: */
162 dpavlin 34 if (writeflag == MEM_READ) {
163 dpavlin 20 odata = d->sr & d->er;
164 dpavlin 34 } else {
165 dpavlin 20 fatal("[ cpc700_int: write to CPC_UIC_MSR? ]\n");
166 dpavlin 34 }
167 dpavlin 20 break;
168    
169     default:if (writeflag == MEM_WRITE) {
170     fatal("[ cpc700_int: unimplemented write to "
171     "offset 0x%x: data=0x%x ]\n", (int)
172     relative_addr, (int)idata);
173     } else {
174     fatal("[ cpc700_int: unimplemented read from "
175     "offset 0x%x ]\n", (int)relative_addr);
176     }
177     }
178    
179     if (writeflag == MEM_READ)
180     memory_writemax64(cpu, data, len, odata);
181    
182     return 1;
183     }
184    
185    
186 dpavlin 34 DEVINIT(cpc700)
187 dpavlin 20 {
188     struct cpc700_data *d;
189     char tmp[300];
190 dpavlin 34 int i;
191 dpavlin 20
192 dpavlin 42 CHECK_ALLOCATION(d = malloc(sizeof(struct cpc700_data)));
193 dpavlin 20 memset(d, 0, sizeof(struct cpc700_data));
194    
195 dpavlin 34 /* Connect to the CPU's interrupt pin: */
196     INTERRUPT_CONNECT(devinit->interrupt_path, d->ppc_irq);
197    
198     /* Register 32 CPC700 interrupts: */
199     for (i=0; i<32; i++) {
200     struct interrupt template;
201     char n[300];
202     snprintf(n, sizeof(n), "%s.cpc700.%i",
203     devinit->interrupt_path, i);
204     memset(&template, 0, sizeof(template));
205 dpavlin 42 template.line = 1 << i;
206 dpavlin 34 template.name = n;
207     template.extra = d;
208     template.interrupt_assert = cpc700_interrupt_assert;
209     template.interrupt_deassert = cpc700_interrupt_deassert;
210     interrupt_handler_register(&template);
211     }
212    
213 dpavlin 20 /* Register a PCI bus: */
214 dpavlin 34 snprintf(tmp, sizeof(tmp), "%s.cpc700", devinit->interrupt_path);
215 dpavlin 20 d->pci_data = bus_pci_init(
216 dpavlin 34 devinit->machine,
217     tmp, /* pciirq path */
218 dpavlin 20 0, /* pci device io offset */
219     0, /* pci device mem offset */
220     CPC_PCI_IO_BASE, /* PCI portbase */
221     CPC_PCI_MEM_BASE, /* PCI membase: TODO */
222 dpavlin 34 tmp, /* PCI irqbase */
223 dpavlin 20 0, /* ISA portbase: TODO */
224     0, /* ISA membase: TODO */
225 dpavlin 34 tmp); /* ISA irqbase */
226 dpavlin 20
227 dpavlin 34 switch (devinit->machine->machine_type) {
228    
229 dpavlin 20 case MACHINE_PMPPC:
230 dpavlin 34 bus_pci_add(devinit->machine, d->pci_data,
231     devinit->machine->memory, 0, 0, 0, "heuricon_pmppc");
232 dpavlin 20 break;
233 dpavlin 34
234 dpavlin 20 default:fatal("!\n! WARNING: cpc700 for non-implemented machine"
235     " type\n!\n");
236     exit(1);
237     }
238    
239     /* PCI configuration registers: */
240 dpavlin 34 memory_device_register(devinit->machine->memory, "cpc700_pci",
241     CPC_PCICFGADR, 8, dev_cpc700_pci_access, d, DM_DEFAULT, NULL);
242 dpavlin 20
243     /* Interrupt controller: */
244 dpavlin 34 memory_device_register(devinit->machine->memory, "cpc700_int",
245     CPC_UIC_BASE, CPC_UIC_SIZE, dev_cpc700_int_access, d,
246     DM_DEFAULT, NULL);
247 dpavlin 20
248     /* Two serial ports: */
249 dpavlin 34 snprintf(tmp, sizeof(tmp), "ns16550 irq=%s.cpc700.%i addr=0x%llx "
250     "name2=tty0", devinit->interrupt_path, 31 - CPC_IB_UART_0,
251     (long long)CPC_COM0);
252     devinit->machine->main_console_handle = (size_t)
253     device_add(devinit->machine, tmp);
254     snprintf(tmp, sizeof(tmp), "ns16550 irq=%s.cpc700.%i addr=0x%llx "
255     "name2=tty1", devinit->interrupt_path, 31 - CPC_IB_UART_1,
256     (long long)CPC_COM1);
257     device_add(devinit->machine, tmp);
258 dpavlin 20
259 dpavlin 34 devinit->return_ptr = d->pci_data;
260    
261     return 1;
262 dpavlin 20 }
263    

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