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/* |
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* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_mpc10x.c,v 1.12 2007/06/15 18:13:04 debug Exp $ |
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* |
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* COMMENT: mpc10x bridge (PCI and interrupt controller) |
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* based on dev_uninorth.c |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "bus_pci.h" |
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#include "cpu.h" |
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#include "device.h" |
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#include "interrupt.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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|
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#if 0 |
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|
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#define PCI_VENDOR_ID_MOTOROLA 0x1057 |
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#define MPC10X_BRIDGE_106 ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) | \ |
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PCI_VENDOR_ID_MOTOROLA) |
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#define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA) |
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#define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA) |
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#define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA) |
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|
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#define MPC10X_MAPB_CNFG_ADDR 0xfec00000 |
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#define MPC10X_MAPB_CNFG_DATA 0xfee00000 |
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|
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#define MPC10X_MAPB_ISA_IO_BASE 0xfe000000 |
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#define MPC10X_MAPB_ISA_MEM_BASE 0x80000000 |
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#define MPC10X_MAPB_DRAM_OFFSET 0x00000000 |
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|
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#define MPC10X_MAPB_PCI_IO_START 0x00000000 |
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#define MPC10X_MAPB_PCI_IO_END (0x00c00000 - 1) |
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#define MPC10X_MAPB_PCI_MEM_START 0x80000000 |
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#define MPC10X_MAPB_PCI_MEM_END (0xc0000000 - 1) |
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|
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#define MPC10X_MAPB_PCI_MEM_OFFSET (MPC10X_MAPB_ISA_MEM_BASE - \ |
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MPC10X_MAPB_PCI_MEM_START) |
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|
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#endif |
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|
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struct mpc10x_data { |
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int pciirq; |
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|
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struct pci_data *pci_data; |
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uint64_t cur_addr; |
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}; |
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|
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|
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DEVICE_ACCESS(mpc10x_addr) |
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{ |
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struct mpc10x_data *d = extra; |
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|
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if (writeflag == MEM_WRITE) { |
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uint64_t idata = memory_readmax64(cpu, data, len |
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| MEM_PCI_LITTLE_ENDIAN); |
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int bus, dev, func, reg; |
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|
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d->cur_addr = idata; |
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if (idata == 0) |
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return 0; |
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|
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/* Decompose the Uni-North tag: */ |
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if (idata & 1) { |
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idata &= ~1; |
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bus_pci_decompose_1(idata, &bus, &dev, &func, ®); |
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} else { |
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bus = 0; |
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for (dev=11; dev<32; dev++) |
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if (idata & (1 << dev)) |
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break; |
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if (dev == 32) |
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fatal("[ dev_mpc10x_addr_access: no dev? " |
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"idata=0x%08x ]\n", (int)idata); |
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|
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func = (idata >> 8) & 7; |
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reg = idata & 0xff; |
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} |
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|
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bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg); |
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} else { |
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/* TODO: is returning the current address like this |
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the correct behaviour? */ |
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memory_writemax64(cpu, data, len | MEM_PCI_LITTLE_ENDIAN, |
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d->cur_addr); |
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} |
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|
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return 1; |
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} |
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|
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|
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DEVICE_ACCESS(mpc10x_data) |
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{ |
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struct mpc10x_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN); |
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|
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bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ? &odata : |
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&idata, len, writeflag); |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata); |
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|
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return 1; |
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} |
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|
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|
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struct pci_data *dev_mpc10x_init(struct machine *machine, struct memory *mem, |
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uint64_t addr, int isa_irqbase, int pciirq) |
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{ |
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struct mpc10x_data *d; |
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// char tmp[100]; |
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uint64_t pci_io_offset, pci_mem_offset; |
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uint64_t isa_portbase = 0, isa_membase = 0; |
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uint64_t pci_portbase = 0, pci_membase = 0; |
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|
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CHECK_ALLOCATION(d = malloc(sizeof(struct mpc10x_data))); |
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memset(d, 0, sizeof(struct mpc10x_data)); |
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|
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d->pciirq = pciirq; |
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|
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pci_io_offset = 0x00000000ULL; |
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pci_mem_offset = 0x00000000ULL; |
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pci_portbase = 0xfebffe00ULL; |
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pci_membase = 0x80000000ULL; |
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isa_portbase = 0xfe000000ULL; |
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isa_membase = 0x80000000ULL; |
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|
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/* Create a PCI bus: */ |
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d->pci_data = bus_pci_init(machine, "ZZZ_irq_stuff", |
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pci_io_offset, pci_mem_offset, |
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pci_portbase, pci_membase, "XXX_pci_irqbase", |
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isa_portbase, isa_membase, "YYY_isa_irqbase"); |
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|
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/* Add the PCI glue for the controller itself: */ |
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bus_pci_add(machine, d->pci_data, mem, 0, 0x1f, 0, "mpc10x"); |
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|
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/* ADDR and DATA configuration ports: */ |
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memory_device_register(mem, "mpc10x_pci_addr", addr + 0xc00000, |
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4, dev_mpc10x_addr_access, d, DM_DEFAULT, NULL); |
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memory_device_register(mem, "mpc10x_pci_data", addr + 0xe00000, |
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8, dev_mpc10x_data_access, d, DM_DEFAULT, NULL); |
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|
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return d->pci_data; |
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} |
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