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/* |
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* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_mpc10x.c,v 1.12 2007/06/15 18:13:04 debug Exp $ |
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* |
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* COMMENT: IBM mpc10x bridge (PCI and interrupt controller) |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "bus_pci.h" |
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#include "cpu.h" |
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#include "device.h" |
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#include "interrupt.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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|
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#include "mpc10xreg.h" |
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|
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|
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struct mpc10x_data { |
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struct interrupt ppc_irq; /* Connected to the CPU */ |
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|
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uint32_t sr; /* Interrupt Status register */ |
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uint32_t er; /* Interrupt Enable register */ |
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|
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struct pci_data *pci_data; /* PCI bus */ |
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}; |
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|
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|
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void mpc10x_interrupt_assert(struct interrupt *interrupt) |
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{ |
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struct mpc10x_data *d = interrupt->extra; |
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d->sr |= interrupt->line; |
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if (d->sr & d->er) |
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INTERRUPT_ASSERT(d->ppc_irq); |
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} |
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void mpc10x_interrupt_deassert(struct interrupt *interrupt) |
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{ |
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struct mpc10x_data *d = interrupt->extra; |
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d->sr &= ~interrupt->line; |
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if (!(d->sr & d->er)) |
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INTERRUPT_DEASSERT(d->ppc_irq); |
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} |
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|
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|
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/* |
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* dev_mpc10x_pci_access(): |
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* |
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* Passes PCI indirect addr and data accesses onto bus_pci. |
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*/ |
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DEVICE_ACCESS(mpc10x_pci) |
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{ |
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uint64_t idata = 0, odata = 0; |
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int bus, dev, func, reg; |
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struct mpc10x_data *d = extra; |
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|
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if (writeflag == MEM_WRITE) { |
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idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN); |
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debug("mpc10x_pci WRITE offset 0x%x: 0x%x\n", relative_addr, odata); |
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} |
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|
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debug("relative: %d i: 0x%x o: 0x%x data: %s len: %d\n", relative_addr,idata, odata, data, len ); |
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|
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switch (relative_addr) { |
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case 0: /* Address: */ |
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bus_pci_decompose_1(idata, &bus, &dev, &func, ®); |
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bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg); |
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break; |
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|
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case 4: /* Data: */ |
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bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ? |
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&odata : &idata, len, writeflag); |
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break; |
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} |
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|
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#define PCI_VENDOR_ID_MOTOROLA 0x1057 |
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#define MPC10X_BRIDGE_106 ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) | \ |
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PCI_VENDOR_ID_MOTOROLA) |
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#define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA) |
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#define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA) |
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#define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA) |
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|
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debug("i: 0x%x o: 0x%x\n", idata, odata ); |
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if (writeflag == MEM_READ) { |
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memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata); |
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odata = MPC10X_BRIDGE_8245; |
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debug("mpc10x_pci READ offset 0x%x: 0x%x\n", relative_addr, odata); |
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} |
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|
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return 1; |
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} |
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|
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|
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/* |
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* dev_mpc10x_int_access(): |
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* |
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* The interrupt controller. |
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*/ |
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DEVICE_ACCESS(mpc10x_int) |
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{ |
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struct mpc10x_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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|
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switch (relative_addr) { |
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|
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case MPC_UIC_SR: |
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/* Status register (cleared by writing ones): */ |
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if (writeflag == MEM_READ) { |
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odata = d->sr; |
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} else { |
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d->sr &= ~idata; |
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if (!(d->sr & d->er)) |
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INTERRUPT_DEASSERT(d->ppc_irq); |
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} |
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break; |
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|
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case MPC_UIC_SRS: |
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/* Status register set: */ |
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if (writeflag == MEM_READ) { |
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fatal("[ mpc10x_int: read from MPC_UIC_SRS? ]\n"); |
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odata = d->sr; |
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} else { |
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d->sr = idata; |
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if (d->sr & d->er) |
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INTERRUPT_ASSERT(d->ppc_irq); |
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else |
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INTERRUPT_DEASSERT(d->ppc_irq); |
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} |
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break; |
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|
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case MPC_UIC_ER: |
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/* Enable register: */ |
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if (writeflag == MEM_READ) { |
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odata = d->er; |
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} else { |
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d->er = idata; |
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if (d->sr & d->er) |
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INTERRUPT_ASSERT(d->ppc_irq); |
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else |
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INTERRUPT_DEASSERT(d->ppc_irq); |
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} |
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break; |
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|
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case MPC_UIC_MSR: |
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/* Masked status: */ |
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if (writeflag == MEM_READ) { |
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odata = d->sr & d->er; |
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} else { |
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fatal("[ mpc10x_int: write to MPC_UIC_MSR? ]\n"); |
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} |
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break; |
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|
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default:if (writeflag == MEM_WRITE) { |
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fatal("[ mpc10x_int: unimplemented write to " |
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"offset 0x%x: data=0x%x ]\n", (int) |
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relative_addr, (int)idata); |
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} else { |
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fatal("[ mpc10x_int: unimplemented read from " |
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"offset 0x%x ]\n", (int)relative_addr); |
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} |
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} |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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/* |
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* dev_mpc10x_config_access(): |
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* |
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* Configuration |
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*/ |
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|
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DEVICE_ACCESS(mpc10x_config) |
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{ |
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uint64_t idata = 0, odata = 0; |
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|
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debug("mpc10x_config relative: %d i: 0x%x o: 0x%x data: %x len: %x write: %x w: %x r: %x\n", relative_addr,idata, odata, data, len, writeflag, MEM_WRITE, MEM_READ ); |
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if (writeflag == MEM_WRITE) { |
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idata = memory_readmax64(cpu, data, len); |
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debug("[ mpc10x_config WRITE offset 0x%x: 0x%x odata: 0x%x data: 0x%x len: %d ]\n", relative_addr, idata, odata, data, len); |
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} |
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if (writeflag == MEM_READ) { |
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fatal("[ mpc10x_config: read! ]\n"); |
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} |
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|
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return 1; |
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} |
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|
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#define PCI_VENDOR_ID_MOTOROLA 0x1057 |
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#define MPC10X_BRIDGE_106 ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) | \ |
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PCI_VENDOR_ID_MOTOROLA) |
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#define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA) |
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#define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA) |
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#define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA) |
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|
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DEVICE_ACCESS(mpc10x_data) |
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{ |
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uint64_t idata = 0, odata = 0; |
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|
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debug("mpc10x_data: relative: %d i: 0x%x o: 0x%x data: %s len: %d write: %d\n", relative_addr,idata, odata, data, len, writeflag ); |
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if (writeflag == MEM_WRITE) { |
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idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN); |
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fatal("[ mpc10x_data: write -> %x ]\n", (int)idata); |
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} |
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if (writeflag == MEM_READ) { |
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odata = MPC10X_BRIDGE_8245; |
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memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata); |
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debug("odata = %x\n", (int)odata); |
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debug("[ mpc10x_data: READ offset 0x%x: 0x%x odata: 0x%x data: 0x%x len: %d ]\n", relative_addr, idata, odata, data, len); |
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} |
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|
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return 1; |
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} |
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|
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|
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DEVINIT(mpc10x) |
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{ |
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struct mpc10x_data *d; |
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char tmp[300]; |
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int i; |
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|
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CHECK_ALLOCATION(d = malloc(sizeof(struct mpc10x_data))); |
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memset(d, 0, sizeof(struct mpc10x_data)); |
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|
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/* Connect to the CPU's interrupt pin: */ |
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INTERRUPT_CONNECT(devinit->interrupt_path, d->ppc_irq); |
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|
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/* Register 32 mpc10x interrupts: */ |
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for (i=0; i<32; i++) { |
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struct interrupt template; |
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char n[300]; |
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snprintf(n, sizeof(n), "%s.mpc10x.%i", |
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devinit->interrupt_path, i); |
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memset(&template, 0, sizeof(template)); |
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template.line = 1 << i; |
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template.name = n; |
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template.extra = d; |
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template.interrupt_assert = mpc10x_interrupt_assert; |
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template.interrupt_deassert = mpc10x_interrupt_deassert; |
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interrupt_handler_register(&template); |
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} |
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|
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#define MPC10X_MAPB_CNFG_ADDR 0xfec00000 |
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#define MPC10X_MAPB_CNFG_DATA 0xfee00000 |
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|
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#define MPC10X_MAPB_ISA_IO_BASE 0xfe000000 |
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#define MPC10X_MAPB_ISA_MEM_BASE 0x80000000 |
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#define MPC10X_MAPB_DRAM_OFFSET 0x00000000 |
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|
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#define MPC10X_MAPB_PCI_IO_START 0x00000000 |
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#define MPC10X_MAPB_PCI_IO_END (0x00c00000 - 1) |
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#define MPC10X_MAPB_PCI_MEM_START 0x80000000 |
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#define MPC10X_MAPB_PCI_MEM_END (0xc0000000 - 1) |
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|
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#define MPC10X_MAPB_PCI_MEM_OFFSET (MPC10X_MAPB_ISA_MEM_BASE - \ |
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MPC10X_MAPB_PCI_MEM_START) |
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|
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|
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|
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/* Register a PCI bus: */ |
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snprintf(tmp, sizeof(tmp), "%s.mpc10x", devinit->interrupt_path); |
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d->pci_data = bus_pci_init( |
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devinit->machine, |
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tmp, /* pciirq path */ |
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0x00000000, /* pci device io offset */ |
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0x00000000, /* pci device mem offset */ |
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0xfe000000, /* PCI portbase */ |
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0x80000000, /* PCI membase: TODO */ |
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tmp, /* PCI irqbase */ |
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0xfe000000, /* ISA portbase: TODO */ |
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0x80000000, /* ISA membase: TODO */ |
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tmp); /* ISA irqbase */ |
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|
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/* PCI host bridge */ |
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bus_pci_add(devinit->machine, d->pci_data, |
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devinit->machine->memory, 0, 0, 0, "mpc10x_host_bridge"); |
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|
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/* MPC10x configuration */ |
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memory_device_register(devinit->machine->memory, "mpc10x_config", |
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0xfec00000, 1, dev_mpc10x_config_access, d, DM_DEFAULT, NULL); |
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memory_device_register(devinit->machine->memory, "mpc10x_data", |
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0xfee00000, 8, dev_mpc10x_data_access, d, DM_DEFAULT, NULL); |
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|
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#if 0 |
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/* PCI configuration registers: */ |
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memory_device_register(devinit->machine->memory, "mpc10x_pci", |
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0xfee00000, 8, dev_mpc10x_pci_access, d, DM_DEFAULT, NULL); |
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|
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/* Interrupt controller: */ |
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memory_device_register(devinit->machine->memory, "mpc10x_int", |
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MPC_UIC_BASE, MPC_UIC_SIZE, dev_mpc10x_int_access, d, |
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DM_DEFAULT, NULL); |
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#endif |
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|
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/* Two serial ports: */ |
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snprintf(tmp, sizeof(tmp), "ns16550 irq=%s.mpc10x.%i addr=0x%llx " |
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"name2=tty0", devinit->interrupt_path, 31 - MPC_IB_UART_0, |
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(long long)MPC_COM0); |
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devinit->machine->main_console_handle = (size_t) |
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device_add(devinit->machine, tmp); |
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#if 0 |
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snprintf(tmp, sizeof(tmp), "ns16550 irq=%s.mpc10x.%i addr=0x%llx " |
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"name2=tty1", devinit->interrupt_path, 31 - MPC_IB_UART_1, |
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(long long)MPC_COM1); |
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device_add(devinit->machine, tmp); |
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#endif |
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|
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devinit->return_ptr = d->pci_data; |
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|
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return 1; |
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} |
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