/[gxemul]/trunk/src/devices/dev_mp.c
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Contents of /trunk/src/devices/dev_mp.c

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Revision 20 - (show annotations)
Mon Oct 8 16:19:23 2007 UTC (14 years, 3 months ago) by dpavlin
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File size: 7726 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1055 2005/11/25 22:48:36 debug Exp $
20051031	Adding disassembly support for more ARM instructions (clz,
		smul* etc), and adding a hack to support "new tiny" pages
		for StrongARM.
20051101	Minor documentation updates (NetBSD 2.0.2 -> 2.1, and OpenBSD
		3.7 -> 3.8, and lots of testing).
		Changing from 1-sector PIO mode 0 transfers to 128-sector PIO
		mode 3 (in dev_wdc).
		Various minor ARM dyntrans updates (pc-relative loads from
		within the same page as the instruction are now treated as
		constant "mov").
20051102	Re-enabling instruction combinations (they were accidentally
		disabled).
		Dyntrans TLB entries are now overwritten using a round-robin
		scheme instead of randomly. This increases performance.
		Fixing a typo in file.c (thanks to Chuan-Hua Chang for
		noticing it).
		Experimenting with adding ATAPI support to dev_wdc (to make
		emulated *BSD detect cdroms as cdroms, not harddisks).
20051104	Various minor updates.
20051105	Continuing on the ATAPI emulation. Seems to work well enough
		for a NetBSD/cats installation, but not OpenBSD/cats.
		Various other updates.
20051106	Modifying the -Y command line option to allow scaleup with
		certain graphic controllers (only dev_vga so far), not just
		scaledown.
		Some minor dyntrans cleanups.
20051107	Beginning a cleanup up the PCI subsystem (removing the
		read_register hack, etc).
20051108	Continuing the cleanup; splitting up some pci devices into a
		normal autodev device and some separate pci glue code.
20051109	Continuing on the PCI bus stuff; all old pci_*.c have been
		incorporated into normal devices and/or rewritten as glue code
		only, adding a dummy Intel 82371AB PIIX4 for Malta (not really
		tested yet).
		Minor pckbc fix so that Linux doesn't complain.
		Working on the DEC 21143 NIC (ethernet mac rom stuff mostly).
		Various other minor fixes.
20051110	Some more ARM dyntrans fine-tuning (e.g. some instruction
		combinations (cmps followed by conditional branch within the
		same page) and special cases for DPIs with regform when the
		shifter isn't used).
20051111	ARM dyntrans updates: O(n)->O(1) for just-mark-as-non-
		writable in the generic pc_to_pointers function, and some other
		minor hacks.
		Merging Cobalt and evbmips (Malta) ISA interrupt handling,
		and some minor fixes to allow Linux to accept harddisk irqs.
20051112	Minor device updates (pckbc, dec21143, lpt, ...), most
		importantly fixing the ALI M1543/M5229 so that harddisk irqs
		work with Linux/CATS.
20051113	Some more generalizations of the PCI subsystem.
		Finally took the time to add a hack for SCSI CDROM TOCs; this
		enables OpenBSD to use partition 'a' (as needed by the OpenBSD
		installer), and Windows NT's installer to get a bit further.
		Also fixing dev_wdc to allow Linux to detect ATAPI CDROMs.
		Continuing on the DEC 21143.
20051114	Minor ARM dyntrans tweaks; ARM cmps+branch optimization when
		comparing with 0, and generalizing the xchg instr. comb.
		Adding disassembly of ARM mrrc/mcrr and q{,d}{add,sub}.
20051115	Continuing on various PPC things (BATs, other address trans-
		lation things, various loads/stores, BeBox emulation, etc.).
		Beginning to work on PPC interrupt/exception support.
20051116	Factoring out some code which initializes legacy ISA devices
		from those machines that use them (bus_isa).
		Continuing on PPC interrupt/exception support.
20051117	Minor Malta fixes: RTC year offset = 80, disabling a speed hack
		which caused NetBSD to detect a too fast cpu, and adding a new
		hack to make Linux detect a faster cpu.
		Continuing on the Artesyn PM/PPC emulation mode.
		Adding an Algor emulation skeleton (P4032 and P5064);
		implementing some of the basics.
		Continuing on PPC emulation in general; usage of unimplemented
		SPRs is now easier to track, continuing on memory/exception
		related issues, etc.
20051118	More work on PPC emulation (tgpr0..3, exception handling,
		memory stuff, syscalls, etc.).
20051119	Changing the ARM dyntrans code to mostly use cpu->pc, and not
		necessarily use arm reg 15. Seems to work.
		Various PPC updates; continuing on the PReP emulation mode.
20051120	Adding a workaround/hack to dev_mc146818 to allow NetBSD/prep
		to detect the clock.
20051121	More cleanup of the PCI bus (memory and I/O bases, etc).
		Continuing on various PPC things (decrementer and timebase,
		WDCs on obio (on PReP) use irq 13, not 14/15).
20051122	Continuing on the CPC700 controller (interrupts etc) for PMPPC,
		and on PPC stuff in general.
		Finally! After some bug fixes to the virtual to physical addr
		translation, NetBSD/{prep,pmppc} 2.1 reach userland and are
		stable enough to be interacted with.
		More PCI updates; reverse-endian device access for PowerPC etc.
20051123	Generalizing the IEEE floating point subsystem (moving it out
		from src/cpus/cpu_mips_coproc.c into a new src/float_emul.c).
		Input via slave xterms was sometimes not really working; fixing
		this for ns16550, and a warning message is now displayed if
		multiple non-xterm consoles are active.
		Adding some PPC floating point support, etc.
		Various interrupt related updates (dev_wdc, _ns16550, _8259,
		and the isa32 common code in machine.c).
		NetBSD/prep can now be installed! :-) (Well, with some manual
		commands necessary before running sysinst.) Updating the
		documentation and various other things to reflect this.
20051124	Various minor documentation updates.
		Continuing the work on the DEC 21143 NIC.
20051125	LOTS of work on the 21143. Both OpenBSD and NetBSD work fine
		with it now, except that OpenBSD sometimes gives a time-out
		warning.
		Minor documentation updates.

==============  RELEASE 0.3.7  ==============


1 /*
2 * Copyright (C) 2003-2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_mp.c,v 1.30 2005/11/13 00:14:09 debug Exp $
29 *
30 * This is a fake multiprocessor (MP) device. It can be useful for
31 * theoretical experiments, but probably bares no resemblance to any
32 * multiprocessor controller used in any real machine.
33 */
34
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38
39 #include "cpu.h"
40 #include "cpu_mips.h"
41 #include "device.h"
42 #include "machine.h"
43 #include "memory.h"
44 #include "misc.h"
45 #include "mp.h"
46
47
48 struct mp_data {
49 struct cpu **cpus;
50 uint64_t startup_addr;
51 uint64_t stack_addr;
52 uint64_t pause_addr;
53
54 /* Each CPU has an array of pending ipis. */
55 int *n_pending_ipis;
56 int **ipi;
57 };
58
59
60 extern int single_step;
61
62
63 /*
64 * dev_mp_access():
65 */
66 int dev_mp_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr,
67 unsigned char *data, size_t len, int writeflag, void *extra)
68 {
69 struct mp_data *d = extra;
70 int i, which_cpu;
71 uint64_t idata = 0, odata = 0;
72
73 if (writeflag == MEM_WRITE)
74 idata = memory_readmax64(cpu, data, len);
75
76 /*
77 * NOTE: It is up to the user of this device to read or write
78 * correct addresses. (A write to NCPUS is pretty useless,
79 * for example.)
80 */
81
82 switch (relative_addr) {
83
84 case DEV_MP_WHOAMI:
85 odata = cpu->cpu_id;
86 break;
87
88 case DEV_MP_NCPUS:
89 odata = cpu->machine->ncpus;
90 break;
91
92 case DEV_MP_STARTUPCPU:
93 which_cpu = idata;
94 d->cpus[which_cpu]->pc = d->startup_addr;
95 switch (cpu->machine->arch) {
96 case ARCH_MIPS:
97 d->cpus[which_cpu]->cd.mips.gpr[MIPS_GPR_SP] =
98 d->stack_addr;
99 break;
100 case ARCH_PPC:
101 d->cpus[which_cpu]->cd.ppc.gpr[1] = d->stack_addr;
102 break;
103 default:
104 fatal("dev_mp(): DEV_MP_STARTUPCPU: not for this"
105 " arch yet!\n");
106 exit(1);
107 }
108 d->cpus[which_cpu]->running = 1;
109 /* debug("[ dev_mp: starting up cpu%i at 0x%llx ]\n",
110 which_cpu, (long long)d->startup_addr); */
111 break;
112
113 case DEV_MP_STARTUPADDR:
114 if (len==4 && (idata >> 32) == 0 && (idata & 0x80000000ULL))
115 idata |= 0xffffffff00000000ULL;
116 d->startup_addr = idata;
117 break;
118
119 case DEV_MP_PAUSE_ADDR:
120 d->pause_addr = idata;
121 break;
122
123 case DEV_MP_PAUSE_CPU:
124 /* Pause all cpus except our selves: */
125 which_cpu = idata;
126
127 for (i=0; i<cpu->machine->ncpus; i++)
128 if (i!=which_cpu)
129 d->cpus[i]->running = 0;
130 break;
131
132 case DEV_MP_UNPAUSE_CPU:
133 /* Unpause all cpus except our selves: */
134 which_cpu = idata;
135 for (i=0; i<cpu->machine->ncpus; i++)
136 if (i!=which_cpu)
137 d->cpus[i]->running = 1;
138 break;
139
140 case DEV_MP_STARTUPSTACK:
141 if (len == 4 && (idata >> 32) == 0 && (idata & 0x80000000ULL))
142 idata |= 0xffffffff00000000ULL;
143 d->stack_addr = idata;
144 break;
145
146 case DEV_MP_HARDWARE_RANDOM:
147 /* Return (up to) 64 bits of "hardware random": */
148 odata = random();
149 odata = (odata << 31) ^ random();
150 odata = (odata << 31) ^ random();
151 break;
152
153 case DEV_MP_MEMORY:
154 /*
155 * Return the number of bytes of memory in the system.
156 *
157 * (It is assumed to be located at physical address 0.
158 * It is actually located at machine->memory_offset_in_mb
159 * but that is only used for SGI emulation so far.)
160 */
161 odata = cpu->machine->physical_ram_in_mb * 1048576;
162 break;
163
164 case DEV_MP_IPI_ONE:
165 case DEV_MP_IPI_MANY:
166 /*
167 * idata should be of the form:
168 *
169 * (IPI_nr << 16) | cpu_id
170 *
171 * This will send an Inter-processor interrupt to a specific
172 * CPU. (DEV_MP_IPI_MANY sends to all _except_ the specific
173 * CPU.)
174 *
175 * Sending an IPI means adding the IPI last in the list of
176 * pending IPIs, and asserting the IPI "pin".
177 */
178 which_cpu = (idata & 0xffff);
179 for (i=0; i<cpu->machine->ncpus; i++) {
180 int send_it = 0;
181 if (relative_addr == DEV_MP_IPI_ONE && i == which_cpu)
182 send_it = 1;
183 if (relative_addr == DEV_MP_IPI_MANY && i != which_cpu)
184 send_it = 1;
185 if (send_it) {
186 d->n_pending_ipis[i] ++;
187 d->ipi[i] = realloc(d->ipi[i],
188 d->n_pending_ipis[i] * sizeof(int));
189 if (d->ipi[i] == NULL) {
190 fprintf(stderr, "out of memory\n");
191 exit(1);
192 }
193 /* Add the IPI last in the array: */
194 d->ipi[i][d->n_pending_ipis[i] - 1] =
195 idata >> 16;
196 cpu_interrupt(d->cpus[i], MIPS_IPI_INT);
197 }
198 }
199 break;
200
201 case DEV_MP_IPI_READ:
202 /*
203 * If the current CPU has any IPIs pending, accessing this
204 * address reads the IPI value. (Writing to this address
205 * discards _all_ pending IPIs.) If there is no pending
206 * IPI, then 0 is returned. Usage of the value 0 for real
207 * IPIs should thus be avoided.
208 */
209 if (writeflag == MEM_WRITE) {
210 d->n_pending_ipis[cpu->cpu_id] = 0;
211 }
212 odata = 0;
213 if (d->n_pending_ipis[cpu->cpu_id] > 0) {
214 odata = d->ipi[cpu->cpu_id][0];
215 if (d->n_pending_ipis[cpu->cpu_id]-- > 1)
216 memmove(&d->ipi[cpu->cpu_id][0],
217 &d->ipi[cpu->cpu_id][1],
218 d->n_pending_ipis[cpu->cpu_id]);
219 }
220 /* Deassert the interrupt, if there are no pending IPIs: */
221 if (d->n_pending_ipis[cpu->cpu_id] == 0)
222 cpu_interrupt_ack(d->cpus[cpu->cpu_id], MIPS_IPI_INT);
223 break;
224
225 case DEV_MP_NCYCLES:
226 /*
227 * Return approximately the number of cycles executed
228 * in this machine. (This value is not updated for each
229 * instruction.)
230 */
231 odata = cpu->machine->ncycles;
232 break;
233
234 default:
235 fatal("[ dev_mp: unimplemented relative addr 0x%x ]\n",
236 relative_addr);
237 }
238
239 if (writeflag == MEM_READ)
240 memory_writemax64(cpu, data, len, odata);
241
242 return 1;
243 }
244
245
246 /*
247 * devinit_mp():
248 */
249 int devinit_mp(struct devinit *devinit)
250 {
251 struct mp_data *d;
252 int n;
253
254 d = malloc(sizeof(struct mp_data));
255 if (d == NULL) {
256 fprintf(stderr, "out of memory\n");
257 exit(1);
258 }
259 memset(d, 0, sizeof(struct mp_data));
260 d->cpus = devinit->machine->cpus;
261 d->startup_addr = INITIAL_PC;
262 d->stack_addr = INITIAL_STACK_POINTER;
263
264 n = devinit->machine->ncpus;
265 d->n_pending_ipis = malloc(n * sizeof(int));
266 d->ipi = malloc(n * sizeof(int *));
267 if (d->ipi == NULL || d->n_pending_ipis == NULL) {
268 fprintf(stderr, "out of memory\n");
269 exit(1);
270 }
271 memset(d->n_pending_ipis, 0, sizeof(int) * n);
272 memset(d->ipi, 0, sizeof(int *) * n);
273
274 memory_device_register(devinit->machine->memory, devinit->name,
275 devinit->addr, DEV_MP_LENGTH, dev_mp_access, d, DM_DEFAULT, NULL);
276
277 return 1;
278 }
279

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