/[gxemul]/trunk/src/devices/dev_mp.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Contents of /trunk/src/devices/dev_mp.c

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Revision 14 - (show annotations)
Mon Oct 8 16:18:51 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 7697 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.982 2005/10/07 22:45:32 debug Exp $
20050816	Some success in decoding the way the SGI O2 PROM draws graphics
		during bootup; lines/rectangles and bitmaps work, enough to
		show the bootlogo etc. :-)
		Adding more PPC instructions, and (dummy) BAT registers.
20050817	Updating the pckbc to support scancode type 3 keyboards
		(required in order to interact with the SGI O2 PROM).
		Adding more PPC instructions.
20050818	Adding more ARM instructions; general register forms.
		Importing armreg.h from NetBSD (ARM cpu ids). Adding a (dummy)
		CATS machine mode (using SA110 as the default CPU).
		Continuing on general dyntrans related stuff.
20050819	Register forms for ARM load/stores. Gaah! The Compaq C Compiler
		bug is triggered for ARM loads as well, not just PPC :-(
		Adding full support for ARM PC-relative load/stores, and load/
		stores where the PC register is the destination register.
		Adding support for ARM a.out binaries.
20050820	Continuing to add more ARM instructions, and correcting some
		bugs. Continuing on CATS emulation.
		More work on the PPC stuff.
20050821	Minor PPC and ARM updates. Adding more machine types.
20050822	All ARM "data processing instructions" are now generated
		automatically.
20050824	Beginning the work on the ARM system control coprocessor.
		Adding support for ARM halfword load/stores, and signed loads.
20050825	Fixing an important bug related to the ARM condition codes.
		OpenBSD/zaurus and NetBSD/netwinder now print some boot
		messages. :)
		Adding a dummy SH (Hitachi SuperH) cpu family.
		Beginning to add some ARM virtual address translation.
		MIPS bugfixes: unaligned PC now cause an ADEL exception (at
		least for non-bintrans execution), and ADEL/ADES (not
		TLBL/TLBS) are used if userland tries to access kernel space.
		(Thanks to Joshua Wise for making me aware of these bugs.)
20050827	More work on the ARM emulation, and various other updates.
20050828	More ARM updates.
		Finally taking the time to work on translation invalidation
		(i.e. invalidating translated code mappings when memory is
		written to). Hopefully this doesn't break anything.
20050829	Moving CPU related files from src/ to a new subdir, src/cpus/.
		Moving PROM emulation stuff from src/ to src/promemul/.
		Better debug instruction trace for ARM loads and stores.
20050830	Various ARM updates (correcting CMP flag calculation, etc).
20050831	PPC instruction updates. (Flag fixes, etc.)
20050901	Various minor PPC and ARM instruction emulation updates.
		Minor OpenFirmware emulation updates.
20050903	Adding support for adding arbitrary ARM coprocessors (with
		the i80321 I/O coprocessor as a first test).
		Various other ARM and PPC updates.
20050904	Adding some SHcompact disassembly routines.
20050907	(Re)adding a dummy HPPA CPU module, and a dummy i960 module.
20050908	Began hacking on some Apple Partition Table support.
20050909	Adding support for loading Mach-O (Darwin PPC) binaries.
20050910	Fixing an ARM bug (Carry flag was incorrectly updated for some
		data processing instructions); OpenBSD/cats and NetBSD/
		netwinder get quite a bit further now.
		Applying a patch to dev_wdc, and a one-liner to dev_pcic, to
		make them work better when emulating new versions of OpenBSD.
		(Thanks to Alexander Yurchenko for the patches.)
		Also doing some other minor updates to dev_wdc. (Some cleanup,
		and finally converting to devinit, etc.)
20050912	IRIX doesn't have u_int64_t by default (noticed by Andreas
		<avr@gnulinux.nl>); configure updated to reflect this.
		Working on ARM register bank switching, CPSR vs SPSR issues,
		and beginning the work on interrupt/exception support.
20050913	Various minor ARM updates (speeding up load/store multiple,
		and fixing a ROR bug in R(); NetBSD/cats now boots as far as
		OpenBSD/cats).
20050917	Adding a dummy Atmel AVR (8-bit) cpu family skeleton.
20050918	Various minor updates.
20050919	Symbols are now loaded from Mach-O executables.
		Continuing the work on adding ARM exception support.
20050920	More work on ARM stuff: OpenBSD/cats and NetBSD/cats reach
		userland! :-)
20050921	Some more progress on ARM interrupt specifics.
20050923	Fixing linesize for VR4121 (patch by Yurchenko). Also fixing
		linesizes/cachesizes for some other VR4xxx.
		Adding a dummy Acer Labs M1543 PCI-ISA bridge (for CATS) and a
		dummy Symphony Labs 83C553 bridge (for Netwinder), usable by 
		dev_footbridge.
20050924	Some PPC progress.
20050925	More PPC progress.
20050926	PPC progress (fixing some bugs etc); Darwin's kernel gets
		slightly further than before.
20050928	Various updates: footbridge/ISA/pciide stuff, and finally
		fixing the VGA text scroll-by-changing-the-base-offset bug.
20050930	Adding a dummy S3 ViRGE pci card for CATS emulation, which
		both NetBSD and OpenBSD detects as VGA.
		Continuing on Footbridge (timers, ISA interrupt stuff).
20051001	Continuing... there are still bugs, probably interrupt-
		related.
20051002	More work on the Footbridge (interrupt stuff).
20051003	Various minor updates. (Trying to find the bug(s).)
20051004	Continuing on the ARM stuff.
20051005	More ARM-related fixes.
20051007	FINALLY! Found and fixed 2 ARM bugs: 1 memory related, and the
		other was because of an error in the ARM manual (load multiple
		with the S-bit set should _NOT_ load usermode registers, as the
		manual says, but it should load saved registers, which may or
		may not happen to be usermode registers).
		NetBSD/cats and OpenBSD/cats seem to install fine now :-)
		except for a minor bug at the end of the OpenBSD/cats install.
		Updating the documentation, preparing for the next release.
20051008	Continuing with release testing and cleanup.
1 /*
2 * Copyright (C) 2003-2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_mp.c,v 1.28 2005/09/18 19:54:15 debug Exp $
29 *
30 * This is a fake multiprocessor (MP) device. It can be useful for
31 * theoretical experiments, but probably bares no resemblance to any
32 * multiprocessor controller used in any real machine.
33 */
34
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38
39 #include "cpu.h"
40 #include "cpu_mips.h"
41 #include "device.h"
42 #include "machine.h"
43 #include "memory.h"
44 #include "misc.h"
45 #include "mp.h"
46
47
48 struct mp_data {
49 struct cpu **cpus;
50 uint64_t startup_addr;
51 uint64_t stack_addr;
52 uint64_t pause_addr;
53
54 /* Each CPU has an array of pending ipis. */
55 int *n_pending_ipis;
56 int **ipi;
57 };
58
59
60 extern int single_step;
61
62
63 /*
64 * dev_mp_access():
65 */
66 int dev_mp_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr,
67 unsigned char *data, size_t len, int writeflag, void *extra)
68 {
69 struct mp_data *d = extra;
70 int i, which_cpu;
71 uint64_t idata = 0, odata = 0;
72
73 idata = memory_readmax64(cpu, data, len);
74
75 /*
76 * NOTE: It is up to the user of this device to read or write
77 * correct addresses. (A write to NCPUS is pretty useless,
78 * for example.)
79 */
80
81 switch (relative_addr) {
82
83 case DEV_MP_WHOAMI:
84 odata = cpu->cpu_id;
85 break;
86
87 case DEV_MP_NCPUS:
88 odata = cpu->machine->ncpus;
89 break;
90
91 case DEV_MP_STARTUPCPU:
92 which_cpu = idata;
93 d->cpus[which_cpu]->pc = d->startup_addr;
94 switch (cpu->machine->arch) {
95 case ARCH_MIPS:
96 d->cpus[which_cpu]->cd.mips.gpr[MIPS_GPR_SP] =
97 d->stack_addr;
98 break;
99 case ARCH_PPC:
100 d->cpus[which_cpu]->cd.ppc.gpr[1] = d->stack_addr;
101 break;
102 default:
103 fatal("dev_mp(): DEV_MP_STARTUPCPU: not for this"
104 " arch yet!\n");
105 exit(1);
106 }
107 d->cpus[which_cpu]->running = 1;
108 /* debug("[ dev_mp: starting up cpu%i at 0x%llx ]\n",
109 which_cpu, (long long)d->startup_addr); */
110 break;
111
112 case DEV_MP_STARTUPADDR:
113 if (len==4 && (idata >> 32) == 0 && (idata & 0x80000000ULL))
114 idata |= 0xffffffff00000000ULL;
115 d->startup_addr = idata;
116 break;
117
118 case DEV_MP_PAUSE_ADDR:
119 d->pause_addr = idata;
120 break;
121
122 case DEV_MP_PAUSE_CPU:
123 /* Pause all cpus except our selves: */
124 which_cpu = idata;
125
126 for (i=0; i<cpu->machine->ncpus; i++)
127 if (i!=which_cpu)
128 d->cpus[i]->running = 0;
129 break;
130
131 case DEV_MP_UNPAUSE_CPU:
132 /* Unpause all cpus except our selves: */
133 which_cpu = idata;
134 for (i=0; i<cpu->machine->ncpus; i++)
135 if (i!=which_cpu)
136 d->cpus[i]->running = 1;
137 break;
138
139 case DEV_MP_STARTUPSTACK:
140 if (len == 4 && (idata >> 32) == 0 && (idata & 0x80000000ULL))
141 idata |= 0xffffffff00000000ULL;
142 d->stack_addr = idata;
143 break;
144
145 case DEV_MP_HARDWARE_RANDOM:
146 /* Return (up to) 64 bits of "hardware random": */
147 odata = random();
148 odata = (odata << 31) ^ random();
149 odata = (odata << 31) ^ random();
150 break;
151
152 case DEV_MP_MEMORY:
153 /*
154 * Return the number of bytes of memory in the system.
155 *
156 * (It is assumed to be located at physical address 0.
157 * It is actually located at machine->memory_offset_in_mb
158 * but that is only used for SGI emulation so far.)
159 */
160 odata = cpu->machine->physical_ram_in_mb * 1048576;
161 break;
162
163 case DEV_MP_IPI_ONE:
164 case DEV_MP_IPI_MANY:
165 /*
166 * idata should be of the form:
167 *
168 * (IPI_nr << 16) | cpu_id
169 *
170 * This will send an Inter-processor interrupt to a specific
171 * CPU. (DEV_MP_IPI_MANY sends to all _except_ the specific
172 * CPU.)
173 *
174 * Sending an IPI means adding the IPI last in the list of
175 * pending IPIs, and asserting the IPI "pin".
176 */
177 which_cpu = (idata & 0xffff);
178 for (i=0; i<cpu->machine->ncpus; i++) {
179 int send_it = 0;
180 if (relative_addr == DEV_MP_IPI_ONE && i == which_cpu)
181 send_it = 1;
182 if (relative_addr == DEV_MP_IPI_MANY && i != which_cpu)
183 send_it = 1;
184 if (send_it) {
185 d->n_pending_ipis[i] ++;
186 d->ipi[i] = realloc(d->ipi[i],
187 d->n_pending_ipis[i] * sizeof(int));
188 if (d->ipi[i] == NULL) {
189 fprintf(stderr, "out of memory\n");
190 exit(1);
191 }
192 /* Add the IPI last in the array: */
193 d->ipi[i][d->n_pending_ipis[i] - 1] =
194 idata >> 16;
195 cpu_interrupt(d->cpus[i], MIPS_IPI_INT);
196 }
197 }
198 break;
199
200 case DEV_MP_IPI_READ:
201 /*
202 * If the current CPU has any IPIs pending, accessing this
203 * address reads the IPI value. (Writing to this address
204 * discards _all_ pending IPIs.) If there is no pending
205 * IPI, then 0 is returned. Usage of the value 0 for real
206 * IPIs should thus be avoided.
207 */
208 if (writeflag == MEM_WRITE) {
209 d->n_pending_ipis[cpu->cpu_id] = 0;
210 }
211 odata = 0;
212 if (d->n_pending_ipis[cpu->cpu_id] > 0) {
213 odata = d->ipi[cpu->cpu_id][0];
214 if (d->n_pending_ipis[cpu->cpu_id]-- > 1)
215 memmove(&d->ipi[cpu->cpu_id][0],
216 &d->ipi[cpu->cpu_id][1],
217 d->n_pending_ipis[cpu->cpu_id]);
218 }
219 /* Deassert the interrupt, if there are no pending IPIs: */
220 if (d->n_pending_ipis[cpu->cpu_id] == 0)
221 cpu_interrupt_ack(d->cpus[cpu->cpu_id], MIPS_IPI_INT);
222 break;
223
224 case DEV_MP_NCYCLES:
225 /*
226 * Return approximately the number of cycles executed
227 * in this machine. (This value is not updated for each
228 * instruction.)
229 */
230 odata = cpu->machine->ncycles;
231 break;
232
233 default:
234 fatal("[ dev_mp: unimplemented relative addr 0x%x ]\n",
235 relative_addr);
236 }
237
238 if (writeflag == MEM_READ)
239 memory_writemax64(cpu, data, len, odata);
240
241 return 1;
242 }
243
244
245 /*
246 * devinit_mp():
247 */
248 int devinit_mp(struct devinit *devinit)
249 {
250 struct mp_data *d;
251 int n;
252
253 d = malloc(sizeof(struct mp_data));
254 if (d == NULL) {
255 fprintf(stderr, "out of memory\n");
256 exit(1);
257 }
258 memset(d, 0, sizeof(struct mp_data));
259 d->cpus = devinit->machine->cpus;
260 d->startup_addr = INITIAL_PC;
261 d->stack_addr = INITIAL_STACK_POINTER;
262
263 n = devinit->machine->ncpus;
264 d->n_pending_ipis = malloc(n * sizeof(int));
265 d->ipi = malloc(n * sizeof(int *));
266 if (d->ipi == NULL || d->n_pending_ipis == NULL) {
267 fprintf(stderr, "out of memory\n");
268 exit(1);
269 }
270 memset(d->n_pending_ipis, 0, sizeof(int) * n);
271 memset(d->ipi, 0, sizeof(int *) * n);
272
273 memory_device_register(devinit->machine->memory, devinit->name,
274 devinit->addr, DEV_MP_LENGTH, dev_mp_access, d, MEM_DEFAULT, NULL);
275
276 return 1;
277 }
278
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