/[gxemul]/trunk/src/devices/dev_mp.c
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Revision 34 - (hide annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 6 months ago) by dpavlin
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++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============
1 dpavlin 4 /*
2 dpavlin 34 * Copyright (C) 2003-2007 Anders Gavare. All rights reserved.
3 dpavlin 4 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 34 * $Id: dev_mp.c,v 1.40 2007/01/28 13:45:46 debug Exp $
29 dpavlin 4 *
30     * This is a fake multiprocessor (MP) device. It can be useful for
31     * theoretical experiments, but probably bares no resemblance to any
32     * multiprocessor controller used in any real machine.
33 dpavlin 34 *
34     * NOTE: The devinit irq string should be the part _after_ "cpu[%i].".
35     * For MIPS, it will be MIPS_IPI_INT.
36 dpavlin 4 */
37    
38     #include <stdio.h>
39     #include <stdlib.h>
40     #include <string.h>
41    
42     #include "cpu.h"
43     #include "device.h"
44     #include "machine.h"
45 dpavlin 34 #include "interrupt.h"
46 dpavlin 4 #include "memory.h"
47     #include "misc.h"
48    
49 dpavlin 24 #include "testmachine/dev_mp.h"
50 dpavlin 4
51 dpavlin 24
52 dpavlin 4 struct mp_data {
53     struct cpu **cpus;
54     uint64_t startup_addr;
55     uint64_t stack_addr;
56     uint64_t pause_addr;
57 dpavlin 8
58     /* Each CPU has an array of pending ipis. */
59     int *n_pending_ipis;
60     int **ipi;
61 dpavlin 34
62     /* Connections to all CPUs' IPI pins: */
63     struct interrupt *ipi_irq;
64 dpavlin 4 };
65    
66    
67 dpavlin 8 extern int single_step;
68    
69    
70 dpavlin 22 DEVICE_ACCESS(mp)
71 dpavlin 4 {
72     struct mp_data *d = extra;
73     int i, which_cpu;
74     uint64_t idata = 0, odata = 0;
75    
76 dpavlin 18 if (writeflag == MEM_WRITE)
77     idata = memory_readmax64(cpu, data, len);
78 dpavlin 4
79     /*
80     * NOTE: It is up to the user of this device to read or write
81     * correct addresses. (A write to NCPUS is pretty useless,
82     * for example.)
83     */
84    
85     switch (relative_addr) {
86    
87     case DEV_MP_WHOAMI:
88     odata = cpu->cpu_id;
89     break;
90    
91     case DEV_MP_NCPUS:
92     odata = cpu->machine->ncpus;
93     break;
94    
95     case DEV_MP_STARTUPCPU:
96     which_cpu = idata;
97     d->cpus[which_cpu]->pc = d->startup_addr;
98     switch (cpu->machine->arch) {
99     case ARCH_MIPS:
100     d->cpus[which_cpu]->cd.mips.gpr[MIPS_GPR_SP] =
101     d->stack_addr;
102     break;
103     case ARCH_PPC:
104     d->cpus[which_cpu]->cd.ppc.gpr[1] = d->stack_addr;
105     break;
106     default:
107     fatal("dev_mp(): DEV_MP_STARTUPCPU: not for this"
108     " arch yet!\n");
109     exit(1);
110     }
111     d->cpus[which_cpu]->running = 1;
112     /* debug("[ dev_mp: starting up cpu%i at 0x%llx ]\n",
113     which_cpu, (long long)d->startup_addr); */
114     break;
115    
116     case DEV_MP_STARTUPADDR:
117     if (len==4 && (idata >> 32) == 0 && (idata & 0x80000000ULL))
118     idata |= 0xffffffff00000000ULL;
119     d->startup_addr = idata;
120     break;
121    
122     case DEV_MP_PAUSE_ADDR:
123     d->pause_addr = idata;
124     break;
125    
126     case DEV_MP_PAUSE_CPU:
127 dpavlin 24 /* Pause all cpus except a specific CPU: */
128 dpavlin 4 which_cpu = idata;
129    
130     for (i=0; i<cpu->machine->ncpus; i++)
131 dpavlin 22 if (i != which_cpu)
132 dpavlin 4 d->cpus[i]->running = 0;
133     break;
134    
135     case DEV_MP_UNPAUSE_CPU:
136 dpavlin 22 /* Unpause a specific CPU: */
137 dpavlin 4 which_cpu = idata;
138 dpavlin 22
139     if (which_cpu >= 0 && which_cpu <cpu->machine->ncpus)
140     d->cpus[which_cpu]->running = 1;
141 dpavlin 4 break;
142    
143     case DEV_MP_STARTUPSTACK:
144     if (len == 4 && (idata >> 32) == 0 && (idata & 0x80000000ULL))
145     idata |= 0xffffffff00000000ULL;
146     d->stack_addr = idata;
147     break;
148    
149     case DEV_MP_HARDWARE_RANDOM:
150 dpavlin 22 /*
151     * Return (up to) 64 bits of "hardware random":
152     *
153     * NOTE: Remember that random() is (usually) 31 bits of
154     * random data, _NOT_ 32, hence this construction.
155     */
156 dpavlin 4 odata = random();
157     odata = (odata << 31) ^ random();
158     odata = (odata << 31) ^ random();
159     break;
160    
161     case DEV_MP_MEMORY:
162     /*
163     * Return the number of bytes of memory in the system.
164     *
165     * (It is assumed to be located at physical address 0.
166     * It is actually located at machine->memory_offset_in_mb
167     * but that is only used for SGI emulation so far.)
168     */
169     odata = cpu->machine->physical_ram_in_mb * 1048576;
170     break;
171    
172 dpavlin 8 case DEV_MP_IPI_ONE:
173     case DEV_MP_IPI_MANY:
174     /*
175     * idata should be of the form:
176     *
177     * (IPI_nr << 16) | cpu_id
178     *
179     * This will send an Inter-processor interrupt to a specific
180     * CPU. (DEV_MP_IPI_MANY sends to all _except_ the specific
181     * CPU.)
182     *
183     * Sending an IPI means adding the IPI last in the list of
184     * pending IPIs, and asserting the IPI "pin".
185     */
186     which_cpu = (idata & 0xffff);
187     for (i=0; i<cpu->machine->ncpus; i++) {
188     int send_it = 0;
189     if (relative_addr == DEV_MP_IPI_ONE && i == which_cpu)
190     send_it = 1;
191     if (relative_addr == DEV_MP_IPI_MANY && i != which_cpu)
192     send_it = 1;
193     if (send_it) {
194     d->n_pending_ipis[i] ++;
195     d->ipi[i] = realloc(d->ipi[i],
196     d->n_pending_ipis[i] * sizeof(int));
197     if (d->ipi[i] == NULL) {
198     fprintf(stderr, "out of memory\n");
199     exit(1);
200     }
201 dpavlin 34
202 dpavlin 8 /* Add the IPI last in the array: */
203     d->ipi[i][d->n_pending_ipis[i] - 1] =
204     idata >> 16;
205 dpavlin 34
206     INTERRUPT_ASSERT(d->ipi_irq[i]);
207 dpavlin 8 }
208     }
209     break;
210    
211     case DEV_MP_IPI_READ:
212     /*
213     * If the current CPU has any IPIs pending, accessing this
214     * address reads the IPI value. (Writing to this address
215     * discards _all_ pending IPIs.) If there is no pending
216     * IPI, then 0 is returned. Usage of the value 0 for real
217     * IPIs should thus be avoided.
218     */
219     if (writeflag == MEM_WRITE) {
220     d->n_pending_ipis[cpu->cpu_id] = 0;
221     }
222     odata = 0;
223     if (d->n_pending_ipis[cpu->cpu_id] > 0) {
224     odata = d->ipi[cpu->cpu_id][0];
225     if (d->n_pending_ipis[cpu->cpu_id]-- > 1)
226     memmove(&d->ipi[cpu->cpu_id][0],
227     &d->ipi[cpu->cpu_id][1],
228     d->n_pending_ipis[cpu->cpu_id]);
229     }
230 dpavlin 34
231 dpavlin 8 /* Deassert the interrupt, if there are no pending IPIs: */
232     if (d->n_pending_ipis[cpu->cpu_id] == 0)
233 dpavlin 34 INTERRUPT_DEASSERT(d->ipi_irq[cpu->cpu_id]);
234 dpavlin 8 break;
235    
236 dpavlin 14 case DEV_MP_NCYCLES:
237     /*
238 dpavlin 28 * Return _approximately_ the number of cycles executed
239     * in this machine.
240     *
241     * Note: At the moment, this is actually the number of
242     * instructions executed on CPU 0.
243     *
244     * (This value is not updated for each instruction.)
245 dpavlin 14 */
246 dpavlin 28 odata = cpu->machine->ninstrs;
247 dpavlin 14 break;
248    
249 dpavlin 4 default:
250     fatal("[ dev_mp: unimplemented relative addr 0x%x ]\n",
251     relative_addr);
252     }
253    
254     if (writeflag == MEM_READ)
255     memory_writemax64(cpu, data, len, odata);
256    
257     return 1;
258     }
259    
260    
261 dpavlin 22 DEVINIT(mp)
262 dpavlin 4 {
263     struct mp_data *d;
264 dpavlin 34 int n, i;
265 dpavlin 8
266 dpavlin 4 d = malloc(sizeof(struct mp_data));
267     if (d == NULL) {
268     fprintf(stderr, "out of memory\n");
269     exit(1);
270     }
271     memset(d, 0, sizeof(struct mp_data));
272     d->cpus = devinit->machine->cpus;
273     d->startup_addr = INITIAL_PC;
274     d->stack_addr = INITIAL_STACK_POINTER;
275    
276 dpavlin 8 n = devinit->machine->ncpus;
277 dpavlin 34
278     /* Connect to all CPUs' IPI pins: */
279     d->ipi_irq = malloc(n * sizeof(struct interrupt));
280     if (d->ipi_irq == NULL) {
281     fprintf(stderr, "out of memory\n");
282     exit(1);
283     }
284     for (i=0; i<n; i++) {
285     char tmpstr[200];
286     snprintf(tmpstr, sizeof(tmpstr), "%s.cpu[%i].%s",
287     devinit->machine->path, i, devinit->interrupt_path);
288     INTERRUPT_CONNECT(tmpstr, d->ipi_irq[i]);
289     }
290    
291 dpavlin 8 d->n_pending_ipis = malloc(n * sizeof(int));
292     d->ipi = malloc(n * sizeof(int *));
293     if (d->ipi == NULL || d->n_pending_ipis == NULL) {
294     fprintf(stderr, "out of memory\n");
295     exit(1);
296     }
297     memset(d->n_pending_ipis, 0, sizeof(int) * n);
298     memset(d->ipi, 0, sizeof(int *) * n);
299 dpavlin 4
300 dpavlin 8 memory_device_register(devinit->machine->memory, devinit->name,
301 dpavlin 20 devinit->addr, DEV_MP_LENGTH, dev_mp_access, d, DM_DEFAULT, NULL);
302 dpavlin 8
303 dpavlin 4 return 1;
304     }
305    
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