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dpavlin |
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/* |
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* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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dpavlin |
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* $Id: dev_mc146818.c,v 1.72 2005/08/02 07:56:37 debug Exp $ |
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dpavlin |
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* |
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* MC146818 real-time clock, used by many different machines types. |
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* (DS1687 as used in some SGI machines is similar to MC146818.) |
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* |
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* This device contains Date/time, the machine's ethernet address (on |
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* DECstation 3100), and can cause periodic (hardware) interrupts. |
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* |
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* NOTE: Many register offsets are multiplied by 4 in this code; this is |
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* because I originally wrote it for DECstation 3100 emulation, where the |
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* registered are spaced that way. |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <time.h> |
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#include "cpu.h" |
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#include "devices.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "mc146818reg.h" |
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#define to_bcd(x) ( ((x)/10) * 16 + ((x)%10) ) |
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/* #define MC146818_DEBUG */ |
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dpavlin |
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#define TICK_SHIFT 14 |
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dpavlin |
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/* 256 on DECstation, SGI uses reg at 72*4 as the Century */ |
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#define N_REGISTERS 1024 |
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struct mc_data { |
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int access_style; |
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int last_addr; |
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int register_choice; |
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int reg[N_REGISTERS]; |
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int addrdiv; |
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int use_bcd; |
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int timebase_hz; |
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int interrupt_hz; |
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int irq_nr; |
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int previous_second; |
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int interrupt_every_x_cycles; |
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int cycles_left_until_interrupt; |
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}; |
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/* |
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* recalc_interrupt_cycle(): |
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* |
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* If automatic_clock_adjustment is turned on, then emulated_hz is modified |
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* dynamically. We have to recalculate how often interrupts are to be |
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* triggered. |
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*/ |
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static void recalc_interrupt_cycle(struct cpu *cpu, struct mc_data *d) |
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{ |
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int64_t emulated_hz = cpu->machine->emulated_hz; |
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#if 0 |
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static int warning_printed = 0; |
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/* |
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* A hack to make Ultrix run, even on very fast host machines. |
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* |
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* (Ultrix was probably never meant to be run on machines with |
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* faster CPUs than around 33 MHz or so.) |
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*/ |
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if (d->access_style == MC146818_DEC && emulated_hz > 30000000) { |
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if (!warning_printed) { |
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fatal("\n*********************************************" |
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"**********************************\n\n Your hos" |
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"t machine is too fast! The emulated CPU speed wil" |
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"l be limited to\n 30 MHz, and clocks inside the" |
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" emulated environment might go faster than\n in" |
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" the real world. You have been warned.\n\n******" |
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"*************************************************" |
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"************************\n\n"); |
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warning_printed = 1; |
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} |
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emulated_hz = 30000000; |
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} |
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#endif |
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if (d->interrupt_hz > 0) |
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d->interrupt_every_x_cycles = |
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emulated_hz / d->interrupt_hz; |
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else |
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d->interrupt_every_x_cycles = 0; |
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} |
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/* |
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* dev_mc146818_tick(): |
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*/ |
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void dev_mc146818_tick(struct cpu *cpu, void *extra) |
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{ |
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struct mc_data *d = extra; |
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if (d == NULL) |
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return; |
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recalc_interrupt_cycle(cpu, d); |
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if ((d->reg[MC_REGB * 4] & MC_REGB_PIE) && |
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d->interrupt_every_x_cycles > 0) { |
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dpavlin |
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d->cycles_left_until_interrupt -= (1 << TICK_SHIFT); |
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dpavlin |
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if (d->cycles_left_until_interrupt < 0 || |
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d->cycles_left_until_interrupt >= |
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d->interrupt_every_x_cycles) { |
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/* debug("[ rtc interrupt (every %i cycles) ]\n", |
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d->interrupt_every_x_cycles); */ |
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cpu_interrupt(cpu, d->irq_nr); |
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d->reg[MC_REGC * 4] |= MC_REGC_PF; |
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/* Reset the cycle countdown: */ |
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while (d->cycles_left_until_interrupt < 0) |
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d->cycles_left_until_interrupt += |
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d->interrupt_every_x_cycles; |
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} |
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} |
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if (d->reg[MC_REGC * 4] & MC_REGC_UF || |
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d->reg[MC_REGC * 4] & MC_REGC_AF || |
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d->reg[MC_REGC * 4] & MC_REGC_PF) |
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d->reg[MC_REGC * 4] |= MC_REGC_IRQF; |
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} |
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/* |
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* dev_mc146818_jazz_access(): |
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* |
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* It seems like JAZZ machines accesses the mc146818 by writing one byte to |
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* 0x90000070 and then reading or writing another byte at 0x......0004000. |
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*/ |
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int dev_mc146818_jazz_access(struct cpu *cpu, struct memory *mem, |
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uint64_t relative_addr, unsigned char *data, size_t len, |
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int writeflag, void *extra) |
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{ |
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struct mc_data *d = extra; |
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#ifdef MC146818_DEBUG |
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if (writeflag == MEM_WRITE) { |
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int i; |
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fatal("[ mc146818_jazz: write to addr=0x%04x: ", |
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(int)relative_addr); |
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for (i=0; i<len; i++) |
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fatal("%02x ", data[i]); |
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fatal("]\n"); |
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} else |
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fatal("[ mc146818_jazz: read from addr=0x%04x ]\n", |
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(int)relative_addr); |
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#endif |
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if (writeflag == MEM_WRITE) { |
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d->last_addr = data[0]; |
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return 1; |
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} else { |
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data[0] = d->last_addr; |
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return 1; |
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} |
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} |
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/* |
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* mc146818_update_time(): |
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* |
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* This function updates the MC146818 registers by reading |
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* the host's clock. |
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*/ |
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static void mc146818_update_time(struct mc_data *d) |
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{ |
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struct tm *tmp; |
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time_t timet; |
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timet = time(NULL); |
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tmp = gmtime(&timet); |
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d->reg[4 * MC_SEC] = tmp->tm_sec; |
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d->reg[4 * MC_MIN] = tmp->tm_min; |
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d->reg[4 * MC_HOUR] = tmp->tm_hour; |
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d->reg[4 * MC_DOW] = tmp->tm_wday + 1; |
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d->reg[4 * MC_DOM] = tmp->tm_mday; |
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d->reg[4 * MC_MONTH] = tmp->tm_mon + 1; |
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d->reg[4 * MC_YEAR] = tmp->tm_year; |
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switch (d->access_style) { |
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case MC146818_ARC_NEC: |
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d->reg[4 * MC_YEAR] += (0x18 - 104); |
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break; |
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case MC146818_SGI: |
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/* |
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* NetBSD/sgimips assumes data in BCD format. |
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* Also, IRIX stores the year value in a weird |
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* format, according to ../arch/sgimips/sgimips/clockvar.h |
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* in NetBSD: |
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* |
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* "If year < 1985, store (year - 1970), else |
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* (year - 1940). This matches IRIX semantics." |
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* |
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* Another rule: It seems that a real SGI IP32 box |
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* uses the value 5 for the year 2005. |
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*/ |
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d->reg[4 * MC_YEAR] = |
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d->reg[4 * MC_YEAR] >= 100 ? |
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(d->reg[4 * MC_YEAR] - 100) : |
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( |
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d->reg[4 * MC_YEAR] < 85 ? |
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(d->reg[4 * MC_YEAR] - 30 + 40) |
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: (d->reg[4 * MC_YEAR] - 40) |
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); |
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/* Century: */ |
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d->reg[72 * 4] = 19 + (tmp->tm_year / 100); |
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break; |
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case MC146818_DEC: |
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/* |
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* DECstations must have 72 or 73 in the |
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* Year field, or Ultrix screems. (Weird.) |
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*/ |
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d->reg[4 * MC_YEAR] = 72; |
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/* |
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* Linux on DECstation stores the year in register 63, |
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* but no other DECstation OS does? (Hm.) |
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*/ |
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d->reg[4 * 63] = tmp->tm_year - 100; |
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break; |
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} |
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if (d->use_bcd) { |
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d->reg[4 * MC_SEC] = to_bcd(d->reg[4 * MC_SEC]); |
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d->reg[4 * MC_MIN] = to_bcd(d->reg[4 * MC_MIN]); |
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d->reg[4 * MC_HOUR] = to_bcd(d->reg[4 * MC_HOUR]); |
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d->reg[4 * MC_DOW] = to_bcd(d->reg[4 * MC_DOW]); |
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d->reg[4 * MC_DOM] = to_bcd(d->reg[4 * MC_DOM]); |
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d->reg[4 * MC_MONTH] = to_bcd(d->reg[4 * MC_MONTH]); |
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d->reg[4 * MC_YEAR] = to_bcd(d->reg[4 * MC_YEAR]); |
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/* Used by Linux on DECstation: (Hm) */ |
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d->reg[4 * 63] = to_bcd(d->reg[4 * 63]); |
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| 282 |
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/* Used on SGI: */ |
| 283 |
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d->reg[4 * 72] = to_bcd(d->reg[4 * 72]); |
| 284 |
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} |
| 285 |
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} |
| 286 |
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| 287 |
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| 288 |
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/* |
| 289 |
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* dev_mc146818_access(): |
| 290 |
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* |
| 291 |
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* TODO: This access function only handles 8-bit accesses! |
| 292 |
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*/ |
| 293 |
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int dev_mc146818_access(struct cpu *cpu, struct memory *mem, |
| 294 |
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uint64_t r, unsigned char *data, size_t len, |
| 295 |
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int writeflag, void *extra) |
| 296 |
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{ |
| 297 |
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struct tm *tmp; |
| 298 |
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time_t timet; |
| 299 |
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struct mc_data *d = extra; |
| 300 |
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int i, relative_addr = r; |
| 301 |
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| 302 |
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relative_addr /= d->addrdiv; |
| 303 |
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| 304 |
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/* Different ways of accessing the registers: */ |
| 305 |
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switch (d->access_style) { |
| 306 |
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case MC146818_PC_CMOS: |
| 307 |
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if (relative_addr == 0x70 || relative_addr == 0x00) { |
| 308 |
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if (writeflag == MEM_WRITE) { |
| 309 |
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d->last_addr = data[0]; |
| 310 |
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return 1; |
| 311 |
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} else { |
| 312 |
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data[0] = d->last_addr; |
| 313 |
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return 1; |
| 314 |
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} |
| 315 |
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} else if (relative_addr == 0x71 || relative_addr == 0x01) |
| 316 |
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relative_addr = d->last_addr * 4; |
| 317 |
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else { |
| 318 |
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fatal("[ mc146818: not accessed as an " |
| 319 |
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"MC146818_PC_CMOS device! ]\n"); |
| 320 |
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} |
| 321 |
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break; |
| 322 |
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case MC146818_ARC_NEC: |
| 323 |
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if (relative_addr == 0x01) { |
| 324 |
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if (writeflag == MEM_WRITE) { |
| 325 |
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d->last_addr = data[0]; |
| 326 |
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return 1; |
| 327 |
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} else { |
| 328 |
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data[0] = d->last_addr; |
| 329 |
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return 1; |
| 330 |
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} |
| 331 |
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} else if (relative_addr == 0x00) |
| 332 |
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relative_addr = d->last_addr * 4; |
| 333 |
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else { |
| 334 |
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fatal("[ mc146818: not accessed as an " |
| 335 |
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"MC146818_ARC_NEC device! ]\n"); |
| 336 |
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} |
| 337 |
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break; |
| 338 |
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case MC146818_ARC_JAZZ: |
| 339 |
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/* See comment for dev_mc146818_jazz_access(). */ |
| 340 |
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relative_addr = d->last_addr * 4; |
| 341 |
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break; |
| 342 |
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case MC146818_DEC: |
| 343 |
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case MC146818_SGI: |
| 344 |
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/* |
| 345 |
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* This device was originally written for DECstation |
| 346 |
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* emulation, so no changes are necessary for that access |
| 347 |
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* style. |
| 348 |
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* |
| 349 |
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* SGI access bytes 0x0..0xd at offsets 0x0yz..0xdyz, where yz |
| 350 |
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* should be ignored. It works _almost_ as DEC, if offsets are |
| 351 |
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* divided by 0x40. |
| 352 |
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*/ |
| 353 |
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default: |
| 354 |
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; |
| 355 |
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} |
| 356 |
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| 357 |
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#ifdef MC146818_DEBUG |
| 358 |
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if (writeflag == MEM_WRITE) { |
| 359 |
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fatal("[ mc146818: write to addr=0x%04x (len %i): ", |
| 360 |
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(int)relative_addr, (int)len); |
| 361 |
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for (i=0; i<len; i++) |
| 362 |
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fatal("%02x ", data[i]); |
| 363 |
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fatal("]\n"); |
| 364 |
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|
} |
| 365 |
|
|
#endif |
| 366 |
|
|
|
| 367 |
|
|
/* |
| 368 |
dpavlin |
12 |
* Sprite seems to wants UF interrupt status, once every second, or |
| 369 |
dpavlin |
4 |
* it hangs forever during bootup. (These do not cause interrupts, |
| 370 |
|
|
* but it is good enough... Sprite polls this, iirc.) |
| 371 |
dpavlin |
12 |
* |
| 372 |
|
|
* Linux on at least sgimips and evbmips (Malta) wants the UIP bit |
| 373 |
|
|
* in REGA to be updated once a second. |
| 374 |
dpavlin |
4 |
*/ |
| 375 |
|
|
timet = time(NULL); |
| 376 |
|
|
tmp = gmtime(&timet); |
| 377 |
|
|
d->reg[MC_REGC * 4] &= ~MC_REGC_UF; |
| 378 |
dpavlin |
12 |
|
| 379 |
dpavlin |
4 |
if (tmp->tm_sec != d->previous_second) { |
| 380 |
dpavlin |
12 |
d->reg[MC_REGA * 4] &= ~MC_REGA_UIP; |
| 381 |
|
|
|
| 382 |
dpavlin |
4 |
d->reg[MC_REGC * 4] |= MC_REGC_UF; |
| 383 |
|
|
d->reg[MC_REGC * 4] |= MC_REGC_IRQF; |
| 384 |
|
|
d->previous_second = tmp->tm_sec; |
| 385 |
|
|
|
| 386 |
|
|
/* For some reason, some Linux/DECstation KN04 kernels want |
| 387 |
|
|
the PF (periodic flag) bit set, even though interrupts |
| 388 |
|
|
are not enabled? */ |
| 389 |
|
|
d->reg[MC_REGC * 4] |= MC_REGC_PF; |
| 390 |
dpavlin |
12 |
} else |
| 391 |
|
|
d->reg[MC_REGA * 4] |= MC_REGA_UIP; |
| 392 |
dpavlin |
4 |
|
| 393 |
|
|
/* RTC data is in either BCD format or binary: */ |
| 394 |
dpavlin |
12 |
if (d->use_bcd) |
| 395 |
dpavlin |
4 |
d->reg[MC_REGB * 4] &= ~(1 << 2); |
| 396 |
dpavlin |
12 |
else |
| 397 |
dpavlin |
4 |
d->reg[MC_REGB * 4] |= (1 << 2); |
| 398 |
|
|
|
| 399 |
|
|
/* RTC date/time is always Valid: */ |
| 400 |
|
|
d->reg[MC_REGD * 4] |= MC_REGD_VRT; |
| 401 |
|
|
|
| 402 |
|
|
if (writeflag == MEM_WRITE) { |
| 403 |
|
|
/* WRITE: */ |
| 404 |
|
|
switch (relative_addr) { |
| 405 |
|
|
case MC_REGA*4: |
| 406 |
|
|
if ((data[0] & MC_REGA_DVMASK) == MC_BASE_32_KHz) |
| 407 |
|
|
d->timebase_hz = 32000; |
| 408 |
|
|
if ((data[0] & MC_REGA_DVMASK) == MC_BASE_1_MHz) |
| 409 |
|
|
d->timebase_hz = 1000000; |
| 410 |
|
|
if ((data[0] & MC_REGA_DVMASK) == MC_BASE_4_MHz) |
| 411 |
|
|
d->timebase_hz = 4000000; |
| 412 |
|
|
switch (data[0] & MC_REGA_RSMASK) { |
| 413 |
|
|
case MC_RATE_NONE: |
| 414 |
|
|
d->interrupt_hz = 0; |
| 415 |
|
|
break; |
| 416 |
|
|
case MC_RATE_1: |
| 417 |
|
|
if (d->timebase_hz == 32000) |
| 418 |
|
|
d->interrupt_hz = 256; |
| 419 |
|
|
else |
| 420 |
|
|
d->interrupt_hz = 32768; |
| 421 |
|
|
break; |
| 422 |
|
|
case MC_RATE_2: |
| 423 |
|
|
if (d->timebase_hz == 32000) |
| 424 |
|
|
d->interrupt_hz = 128; |
| 425 |
|
|
else |
| 426 |
|
|
d->interrupt_hz = 16384; |
| 427 |
|
|
break; |
| 428 |
|
|
case MC_RATE_8192_Hz: d->interrupt_hz = 8192; break; |
| 429 |
|
|
case MC_RATE_4096_Hz: d->interrupt_hz = 4096; break; |
| 430 |
|
|
case MC_RATE_2048_Hz: d->interrupt_hz = 2048; break; |
| 431 |
|
|
case MC_RATE_1024_Hz: d->interrupt_hz = 1024; break; |
| 432 |
|
|
case MC_RATE_512_Hz: d->interrupt_hz = 512; break; |
| 433 |
|
|
case MC_RATE_256_Hz: d->interrupt_hz = 256; break; |
| 434 |
|
|
case MC_RATE_128_Hz: d->interrupt_hz = 128; break; |
| 435 |
|
|
case MC_RATE_64_Hz: d->interrupt_hz = 64; break; |
| 436 |
|
|
case MC_RATE_32_Hz: d->interrupt_hz = 32; break; |
| 437 |
|
|
case MC_RATE_16_Hz: d->interrupt_hz = 16; break; |
| 438 |
|
|
case MC_RATE_8_Hz: d->interrupt_hz = 8; break; |
| 439 |
|
|
case MC_RATE_4_Hz: d->interrupt_hz = 4; break; |
| 440 |
|
|
case MC_RATE_2_Hz: d->interrupt_hz = 2; break; |
| 441 |
|
|
default: |
| 442 |
|
|
/* debug("[ mc146818: unimplemented " |
| 443 |
|
|
"MC_REGA RS: %i ]\n", |
| 444 |
|
|
data[0] & MC_REGA_RSMASK); */ |
| 445 |
|
|
; |
| 446 |
|
|
} |
| 447 |
|
|
|
| 448 |
|
|
recalc_interrupt_cycle(cpu, d); |
| 449 |
|
|
|
| 450 |
|
|
d->cycles_left_until_interrupt = |
| 451 |
|
|
d->interrupt_every_x_cycles; |
| 452 |
|
|
|
| 453 |
|
|
d->reg[MC_REGA * 4] = |
| 454 |
|
|
data[0] & (MC_REGA_RSMASK | MC_REGA_DVMASK); |
| 455 |
|
|
|
| 456 |
|
|
debug("[ rtc set to interrupt every %i:th cycle ]\n", |
| 457 |
|
|
d->interrupt_every_x_cycles); |
| 458 |
|
|
break; |
| 459 |
|
|
case MC_REGB*4: |
| 460 |
|
|
if (((data[0] ^ d->reg[MC_REGB*4]) & MC_REGB_PIE)) |
| 461 |
|
|
d->cycles_left_until_interrupt = |
| 462 |
|
|
d->interrupt_every_x_cycles; |
| 463 |
|
|
d->reg[MC_REGB*4] = data[0]; |
| 464 |
|
|
if (!(data[0] & MC_REGB_PIE)) { |
| 465 |
|
|
cpu_interrupt_ack(cpu, d->irq_nr); |
| 466 |
|
|
/* d->cycles_left_until_interrupt = |
| 467 |
|
|
d->interrupt_every_x_cycles; */ |
| 468 |
|
|
} |
| 469 |
|
|
/* debug("[ mc146818: write to MC_REGB, data[0] " |
| 470 |
|
|
"= 0x%02x ]\n", data[0]); */ |
| 471 |
|
|
break; |
| 472 |
|
|
case MC_REGC*4: |
| 473 |
|
|
d->reg[MC_REGC * 4] = data[0]; |
| 474 |
|
|
debug("[ mc146818: write to MC_REGC, data[0] = " |
| 475 |
|
|
"0x%02x ]\n", data[0]); |
| 476 |
|
|
break; |
| 477 |
|
|
case 0x128: |
| 478 |
|
|
d->reg[relative_addr] = data[0]; |
| 479 |
|
|
if (data[0] & 8) { |
| 480 |
|
|
/* Used on SGI to power off the machine. */ |
| 481 |
|
|
fatal("[ md146818: power off ]\n"); |
| 482 |
|
|
for (i=0; i<cpu->machine->ncpus; i++) |
| 483 |
|
|
cpu->machine->cpus[i]->running = 0; |
| 484 |
|
|
cpu->machine-> |
| 485 |
|
|
exit_without_entering_debugger = 1; |
| 486 |
|
|
} |
| 487 |
|
|
break; |
| 488 |
|
|
default: |
| 489 |
|
|
d->reg[relative_addr] = data[0]; |
| 490 |
|
|
|
| 491 |
|
|
debug("[ mc146818: unimplemented write to " |
| 492 |
|
|
"relative_addr = %08lx: ", (long)relative_addr); |
| 493 |
|
|
for (i=0; i<len; i++) |
| 494 |
|
|
debug("%02x ", data[i]); |
| 495 |
|
|
debug("]\n"); |
| 496 |
|
|
} |
| 497 |
|
|
} else { |
| 498 |
|
|
/* READ: */ |
| 499 |
|
|
switch (relative_addr) { |
| 500 |
|
|
case 0x01: /* Station's ethernet address (6 bytes) */ |
| 501 |
|
|
case 0x05: /* (on DECstation 3100) */ |
| 502 |
|
|
case 0x09: |
| 503 |
|
|
case 0x0d: |
| 504 |
|
|
case 0x11: |
| 505 |
|
|
case 0x15: |
| 506 |
|
|
break; |
| 507 |
|
|
case 4 * MC_SEC: |
| 508 |
|
|
case 4 * MC_MIN: |
| 509 |
|
|
case 4 * MC_HOUR: |
| 510 |
|
|
case 4 * MC_DOW: |
| 511 |
|
|
case 4 * MC_DOM: |
| 512 |
|
|
case 4 * MC_MONTH: |
| 513 |
|
|
case 4 * MC_YEAR: |
| 514 |
|
|
case 4 * 63: /* 63 is used by Linux on DECstation */ |
| 515 |
|
|
case 4 * 72: /* 72 is Century, on SGI (DS1687) */ |
| 516 |
|
|
/* |
| 517 |
|
|
* If the SET bit is set, then we don't automatically |
| 518 |
|
|
* update the values. Otherwise, we update them by |
| 519 |
|
|
* reading from the host's clock: |
| 520 |
|
|
*/ |
| 521 |
|
|
if (d->reg[MC_REGB * 4] & MC_REGB_SET) |
| 522 |
|
|
break; |
| 523 |
|
|
|
| 524 |
|
|
mc146818_update_time(d); |
| 525 |
|
|
break; |
| 526 |
|
|
case 4 * MC_REGC: /* Interrupt ack. */ |
| 527 |
|
|
/* NOTE: Acking is done below, _after_ the |
| 528 |
|
|
register has been read. */ |
| 529 |
|
|
break; |
| 530 |
|
|
default: |
| 531 |
|
|
debug("[ mc146818: read from relative_addr = " |
| 532 |
|
|
"%04x ]\n", (int)relative_addr); |
| 533 |
|
|
; |
| 534 |
|
|
} |
| 535 |
|
|
|
| 536 |
|
|
data[0] = d->reg[relative_addr]; |
| 537 |
|
|
|
| 538 |
|
|
if (relative_addr == MC_REGC*4) { |
| 539 |
|
|
cpu_interrupt_ack(cpu, d->irq_nr); |
| 540 |
|
|
/* d->cycles_left_until_interrupt = |
| 541 |
|
|
d->interrupt_every_x_cycles; */ |
| 542 |
|
|
d->reg[MC_REGC * 4] = 0x00; |
| 543 |
|
|
} |
| 544 |
|
|
} |
| 545 |
|
|
|
| 546 |
|
|
#ifdef MC146818_DEBUG |
| 547 |
|
|
if (writeflag == MEM_READ) { |
| 548 |
|
|
fatal("[ mc146818: read from addr=0x%04x (len %i): ", |
| 549 |
|
|
(int)relative_addr, (int)len); |
| 550 |
|
|
for (i=0; i<len; i++) |
| 551 |
|
|
fatal("%02x ", data[i]); |
| 552 |
|
|
fatal("]\n"); |
| 553 |
|
|
} |
| 554 |
|
|
#endif |
| 555 |
|
|
|
| 556 |
|
|
return 1; |
| 557 |
|
|
} |
| 558 |
|
|
|
| 559 |
|
|
|
| 560 |
|
|
/* |
| 561 |
|
|
* dev_mc146818_init(): |
| 562 |
|
|
* |
| 563 |
|
|
* This needs to work for both DECstation emulation and other machine types, |
| 564 |
|
|
* so it contains both rtc related stuff and the station's Ethernet address. |
| 565 |
|
|
*/ |
| 566 |
|
|
void dev_mc146818_init(struct machine *machine, struct memory *mem, |
| 567 |
|
|
uint64_t baseaddr, int irq_nr, int access_style, int addrdiv) |
| 568 |
|
|
{ |
| 569 |
|
|
unsigned char ether_address[6]; |
| 570 |
|
|
int i, dev_len; |
| 571 |
|
|
struct mc_data *d; |
| 572 |
|
|
|
| 573 |
|
|
d = malloc(sizeof(struct mc_data)); |
| 574 |
|
|
if (d == NULL) { |
| 575 |
|
|
fprintf(stderr, "out of memory\n"); |
| 576 |
|
|
exit(1); |
| 577 |
|
|
} |
| 578 |
|
|
|
| 579 |
|
|
memset(d, 0, sizeof(struct mc_data)); |
| 580 |
|
|
d->irq_nr = irq_nr; |
| 581 |
|
|
d->access_style = access_style; |
| 582 |
|
|
d->addrdiv = addrdiv; |
| 583 |
|
|
|
| 584 |
dpavlin |
6 |
/* Only SGIs and PCs use BCD format (?) */ |
| 585 |
|
|
d->use_bcd = 0; |
| 586 |
|
|
if (access_style == MC146818_SGI || access_style == MC146818_PC_CMOS) |
| 587 |
|
|
d->use_bcd = 1; |
| 588 |
|
|
|
| 589 |
|
|
if (access_style == MC146818_DEC) { |
| 590 |
dpavlin |
4 |
/* Station Ethernet Address, on DECstation 3100: */ |
| 591 |
|
|
for (i=0; i<6; i++) |
| 592 |
|
|
ether_address[i] = 0x10 * (i+1); |
| 593 |
|
|
|
| 594 |
dpavlin |
6 |
d->reg[0x01] = ether_address[0]; |
| 595 |
|
|
d->reg[0x05] = ether_address[1]; |
| 596 |
|
|
d->reg[0x09] = ether_address[2]; |
| 597 |
|
|
d->reg[0x0d] = ether_address[3]; |
| 598 |
|
|
d->reg[0x11] = ether_address[4]; |
| 599 |
|
|
d->reg[0x15] = ether_address[5]; |
| 600 |
|
|
/* TODO: 19, 1d, 21, 25 = checksum bytes 1,2,2,1 resp. */ |
| 601 |
|
|
d->reg[0x29] = ether_address[5]; |
| 602 |
|
|
d->reg[0x2d] = ether_address[4]; |
| 603 |
|
|
d->reg[0x31] = ether_address[3]; |
| 604 |
|
|
d->reg[0x35] = ether_address[2]; |
| 605 |
|
|
d->reg[0x39] = ether_address[1]; |
| 606 |
|
|
d->reg[0x3d] = ether_address[1]; |
| 607 |
|
|
d->reg[0x41] = ether_address[0]; |
| 608 |
|
|
d->reg[0x45] = ether_address[1]; |
| 609 |
|
|
d->reg[0x49] = ether_address[2]; |
| 610 |
|
|
d->reg[0x4d] = ether_address[3]; |
| 611 |
|
|
d->reg[0x51] = ether_address[4]; |
| 612 |
|
|
d->reg[0x55] = ether_address[5]; |
| 613 |
|
|
/* TODO: 59, 5d = checksum bytes 1,2 resp. */ |
| 614 |
|
|
d->reg[0x61] = 0xff; |
| 615 |
|
|
d->reg[0x65] = 0x00; |
| 616 |
|
|
d->reg[0x69] = 0x55; |
| 617 |
|
|
d->reg[0x6d] = 0xaa; |
| 618 |
|
|
d->reg[0x71] = 0xff; |
| 619 |
|
|
d->reg[0x75] = 0x00; |
| 620 |
|
|
d->reg[0x79] = 0x55; |
| 621 |
|
|
d->reg[0x7d] = 0xaa; |
| 622 |
dpavlin |
4 |
|
| 623 |
|
|
/* Battery valid, for DECstations */ |
| 624 |
|
|
d->reg[0xf8] = 1; |
| 625 |
|
|
} |
| 626 |
|
|
|
| 627 |
|
|
if (access_style == MC146818_ARC_JAZZ) |
| 628 |
|
|
memory_device_register(mem, "mc146818_jazz", 0x90000070ULL, |
| 629 |
|
|
1, dev_mc146818_jazz_access, d, MEM_DEFAULT, NULL); |
| 630 |
|
|
|
| 631 |
|
|
dev_len = DEV_MC146818_LENGTH; |
| 632 |
|
|
switch (access_style) { |
| 633 |
|
|
case MC146818_PC_CMOS: |
| 634 |
|
|
dev_len = 2; |
| 635 |
|
|
break; |
| 636 |
|
|
case MC146818_SGI: |
| 637 |
|
|
dev_len = 0x400; |
| 638 |
|
|
} |
| 639 |
|
|
|
| 640 |
|
|
memory_device_register(mem, "mc146818", baseaddr, |
| 641 |
|
|
dev_len * addrdiv, dev_mc146818_access, |
| 642 |
|
|
d, MEM_DEFAULT, NULL); |
| 643 |
|
|
|
| 644 |
|
|
mc146818_update_time(d); |
| 645 |
|
|
|
| 646 |
dpavlin |
12 |
machine_add_tickfunction(machine, dev_mc146818_tick, d, TICK_SHIFT); |
| 647 |
dpavlin |
4 |
} |
| 648 |
|
|
|
Parent Directory
| 
Revision Log