/[gxemul]/trunk/src/devices/dev_mb8696x.c
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Contents of /trunk/src/devices/dev_mb8696x.c

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Revision 34 - (show annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 7 months ago) by dpavlin
File MIME type: text/plain
File size: 8074 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============
1 /*
2 * Copyright (C) 2006-2007 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_mb8696x.c,v 1.3 2007/02/03 20:14:23 debug Exp $
29 *
30 * Fujitsu MB8696x Ethernet interface.
31 *
32 * Used as the LAN adapter (MB86967) in the Dreamcast machine mode.
33 *
34 *
35 * Note: This is just a bogus module so far.
36 *
37 * (TODO: "Reverse engineer" more of NetBSD's mb86960.c to implement this.)
38 */
39
40 #include <stdio.h>
41 #include <stdlib.h>
42 #include <string.h>
43 #include <sys/time.h>
44
45 #include "cpu.h"
46 #include "device.h"
47 #include "machine.h"
48 #include "memory.h"
49 #include "misc.h"
50 #include "net.h"
51
52 #include "mb86960reg.h"
53
54
55 #ifdef UNSTABLE_DEVEL
56 #define MB8696X_DEBUG
57 #endif
58
59 #ifdef MB8696X_DEBUG
60 #define debug fatal
61 #endif
62
63 struct mb8696x_data {
64 int addr_mult;
65
66 /*
67 * Registers:
68 *
69 * reg contains 32 registers. However, registers 8..15 are bank-
70 * switched, based on a setting in FE_DLCR7. mar_8_15 are "multicast
71 * address registers", and bmpr_8_15 are "buffer memory port
72 * registers".
73 */
74 uint8_t reg[MB8696X_NREGS];
75 uint8_t mar_8_15[8];
76 uint8_t bmpr_8_15[8];
77
78 /* EEPROM contents and internal state during a read operation: */
79 uint8_t eeprom[FE_EEPROM_SIZE];
80 int eeprom_state;
81 uint8_t eeprom_bit_count;
82 uint8_t eeprom_command;
83 uint16_t eeprom_data;
84 };
85
86 #define EEPROM_STATE_NOTHING 0
87 #define EEPROM_STATE_READY 1 /* Waiting for start bit */
88 #define EEPROM_STATE_COMMAND 2 /* Waiting for 8 command bits */
89 #define EEPROM_STATE_READ 3
90
91
92 DEVICE_ACCESS(mb8696x)
93 {
94 struct mb8696x_data *d = (struct mb8696x_data *) extra;
95 uint64_t idata = 0, odata = 0;
96 uint8_t *reg_ptr;
97
98 if (writeflag == MEM_WRITE)
99 idata = memory_readmax64(cpu, data, len);
100
101 relative_addr /= d->addr_mult;
102
103 /*
104 * Default result on reads: (Note special treatment of banked regs.)
105 */
106 reg_ptr = &d->reg[relative_addr];
107 if (relative_addr >= 8 && relative_addr <= 15 &&
108 (d->reg[FE_DLCR7] & FE_D7_RBS) == FE_D7_RBS_MAR)
109 reg_ptr = &d->mar_8_15[relative_addr - 8];
110 if (relative_addr >= 8 && relative_addr <= 15 &&
111 (d->reg[FE_DLCR7] & FE_D7_RBS) == FE_D7_RBS_BMPR)
112 reg_ptr = &d->bmpr_8_15[relative_addr - 8];
113
114 odata = *reg_ptr;
115
116
117 switch (relative_addr) {
118
119 case FE_DLCR0: /* TX interrupt status */
120 case FE_DLCR1: /* RX interrupt status */
121 /* Write-1-to-clear: */
122 if (writeflag == MEM_WRITE)
123 (*reg_ptr) &= ~idata;
124
125 /* TODO: reassert interrupts */
126
127 break;
128
129 case FE_DLCR2: /* TX interrupt control */
130 case FE_DLCR3: /* RX interrupt control */
131 if (writeflag == MEM_WRITE)
132 (*reg_ptr) = idata;
133
134 /* TODO: reassert interrupts */
135
136 break;
137
138 case FE_DLCR6:
139 case FE_DLCR8: /* Ethernet addr byte 0 */
140 case FE_DLCR9: /* Ethernet addr byte 1 */
141 case FE_DLCR10: /* Ethernet addr byte 2 */
142 case FE_DLCR11: /* Ethernet addr byte 3 */
143 case FE_DLCR12: /* Ethernet addr byte 4 */
144 case FE_DLCR13: /* Ethernet addr byte 5 */
145 if (writeflag == MEM_WRITE)
146 (*reg_ptr) = idata;
147 break;
148
149 case FE_DLCR7:
150 if (writeflag == MEM_WRITE) {
151 /* Identification cannot be overwritten: */
152 (*reg_ptr) &= FE_D7_IDENT;
153 (*reg_ptr) |= (idata & ~FE_D7_IDENT);
154 }
155 break;
156
157 case FE_BMPR16:
158 /* EEPROM control */
159 if (writeflag == MEM_WRITE) {
160 if (idata & ~(FE_B16_DOUT | FE_B16_DIN |
161 FE_B16_SELECT | FE_B16_CLOCK)) {
162 fatal("mb8696x: UNIMPLEMENTED bits when "
163 "writing to FE_BMPR16: 0x%02x\n",
164 (int)idata);
165 exit(1);
166 }
167
168 /* Dropped out of select state? */
169 if (!(idata & FE_B16_SELECT))
170 d->eeprom_state = EEPROM_STATE_NOTHING;
171
172 /* Switching to select state? */
173 if (!((*reg_ptr) & FE_B16_SELECT) &&
174 idata & FE_B16_SELECT)
175 d->eeprom_state = EEPROM_STATE_READY;
176
177 /* Bit clock? */
178 if (!((*reg_ptr) & FE_B16_CLOCK) &&
179 idata & FE_B16_CLOCK) {
180 int bit = d->reg[FE_BMPR17] & FE_B17_DATA? 1:0;
181 switch (d->eeprom_state) {
182 case EEPROM_STATE_READY:
183 d->eeprom_state = EEPROM_STATE_COMMAND;
184 d->eeprom_bit_count = 0;
185 break;
186 case EEPROM_STATE_COMMAND:
187 d->eeprom_bit_count ++;
188 d->eeprom_command <<= 1;
189 d->eeprom_command |= bit;
190 if (d->eeprom_bit_count == 8) {
191 int addr = (d->eeprom_command
192 & 0x7f) << 1;
193 /* printf("COMMAND=%08x\n",
194 d->eeprom_command); */
195 if (!(d->eeprom_command&0x80)) {
196 fatal("WRITES to the "
197 "EEPROM are not yet"
198 " implemented.\n");
199 exit(1);
200 }
201 /* This is a read command. */
202 d->eeprom_bit_count = 0;
203 d->eeprom_state =
204 EEPROM_STATE_READ;
205 d->eeprom_data = d->eeprom[addr]
206 * 256 + d->eeprom[addr+1];
207 }
208 break;
209 case EEPROM_STATE_READ:
210 d->reg[FE_BMPR17] = 0;
211 if (d->eeprom_data & 0x8000)
212 d->reg[FE_BMPR17] = FE_B17_DATA;
213 d->eeprom_data <<= 1;
214 d->eeprom_bit_count ++;
215 if (d->eeprom_bit_count > 16)
216 fatal("[ WARNING: more than 16"
217 " bits of EEPROM data "
218 "read? ]\n");
219 break;
220 }
221 }
222
223 (*reg_ptr) = idata;
224 }
225 break;
226
227 case FE_BMPR17:
228 /* EEPROM data */
229 if (writeflag == MEM_WRITE) {
230 if (idata & ~FE_B17_DATA) {
231 fatal("mb8696x: UNIMPLEMENTED bits when "
232 "writing to FE_BMPR17: 0x%02x\n",
233 (int)idata);
234 exit(1);
235 }
236 (*reg_ptr) = idata;
237 }
238 break;
239
240 default:
241 {
242 char *bank = "";
243 if ((d->reg[FE_DLCR7] & FE_D7_RBS) == FE_D7_RBS_MAR)
244 bank = " (bank MAR)";
245 if ((d->reg[FE_DLCR7] & FE_D7_RBS) == FE_D7_RBS_BMPR)
246 bank = " (bank BMPR)";
247 if (writeflag == MEM_READ) {
248 fatal("[ mb8696x: read from UNIMPLEMENTED reg "
249 "%i%s ]\n", (int)relative_addr, bank);
250 } else {
251 fatal("[ mb8696x: write to UNIMPLEMENTED reg "
252 "%i%s: 0x%02x ]\n", (int)relative_addr,
253 bank, (int)idata);
254 }
255
256 #ifdef MB8696X_DEBUG
257 exit(1);
258 #endif
259 }
260 }
261
262 if (writeflag == MEM_READ)
263 memory_writemax64(cpu, data, len, odata);
264
265 return 1;
266 }
267
268
269 DEVINIT(mb8696x)
270 {
271 struct machine *machine = devinit->machine;
272 struct mb8696x_data *d = malloc(sizeof(struct mb8696x_data));
273 if (d == NULL) {
274 fprintf(stderr, "out of memory\n");
275 exit(1);
276 }
277 memset(d, 0, sizeof(struct mb8696x_data));
278 d->addr_mult = devinit->addr_mult;
279
280 memory_device_register(machine->memory, devinit->name, devinit->addr,
281 MB8696X_NREGS * d->addr_mult, dev_mb8696x_access, d,
282 DM_DEFAULT, NULL);
283
284 /* NetBSD/dreamcast expects ident = 86967. */
285 d->reg[FE_DLCR7] = FE_D7_IDENT_86967;
286
287 /*
288 * Generate the MAC address, both in the first 6 bytes of the
289 * EEPROM, and in DLCR8..13:
290 */
291 net_generate_unique_mac(machine, &d->eeprom[0]);
292 memcpy(&d->reg[FE_DLCR8], &d->eeprom[0], 6);
293
294 return 1;
295 }
296
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