src/devices/dev_m8820x.c

/*
 *  Copyright (C) 2007  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: dev_m8820x.c,v 1.9 2007/06/19 03:38:10 debug Exp $
 *
 *  COMMENT: M88200/M88204 CMMU (Cache/Memory Management Unit)
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "cpu.h"
#include "device.h"
#include "emul.h"
#include "machine.h"
#include "memory.h"
#include "misc.h"


#include "m8820x.h"
#include "m8820x_pte.h"

struct m8820x_data {
        int             cmmu_nr;
};


/*
 *  m8820x_command():
 *
 *  Handle M8820x commands written to the System Command Register.
 */
static void m8820x_command(struct cpu *cpu, struct m8820x_data *d)
{
        uint32_t *regs = cpu->cd.m88k.cmmu[d->cmmu_nr]->reg;
        int cmd = regs[CMMU_SCR];
        uint32_t sar = regs[CMMU_SAR];
        size_t i;
        uint32_t super, all;

        switch (cmd) {

        case CMMU_FLUSH_CACHE_CB_LINE:
        case CMMU_FLUSH_CACHE_INV_LINE:
        case CMMU_FLUSH_CACHE_INV_ALL:
        case CMMU_FLUSH_CACHE_CBI_LINE:
        case CMMU_FLUSH_CACHE_CBI_PAGE:
        case CMMU_FLUSH_CACHE_CBI_SEGMENT:
        case CMMU_FLUSH_CACHE_CBI_ALL:
                /*  TODO  */
                break;

        case CMMU_FLUSH_USER_ALL:
        case CMMU_FLUSH_USER_PAGE:
        case CMMU_FLUSH_SUPER_ALL:
        case CMMU_FLUSH_SUPER_PAGE:
                /*  TODO: Segment invalidation.  */

                all = super = 0;
                if (cmd == CMMU_FLUSH_USER_ALL ||
                    cmd == CMMU_FLUSH_SUPER_ALL)
                        all = 1;
                if (cmd == CMMU_FLUSH_SUPER_ALL ||
                    cmd == CMMU_FLUSH_SUPER_PAGE)
                        super = M8820X_PATC_SUPERVISOR_BIT;

                /*  TODO: Don't invalidate EVERYTHING like this!  */
                cpu->invalidate_translation_caches(cpu, 0, INVALIDATE_ALL);

                for (i=0; i<N_M88200_PATC_ENTRIES; i++) {
                        uint32_t v = cpu->cd.m88k.cmmu[d->cmmu_nr]
                            ->patc_v_and_control[i];
                        uint32_t p = cpu->cd.m88k.cmmu[d->cmmu_nr]
                            ->patc_p_and_supervisorbit[i];

                        /*  Already invalid? Then skip this entry.  */
                        if (!(v & PG_V))
                                continue;

                        /*  Super/user mismatch? Then skip the entry.  */
                        if ((p & M8820X_PATC_SUPERVISOR_BIT) != super)
                                continue;

                        /*  If not all pages are to be invalidated, there
                            must be a virtual address match:  */
                        if (!all && (sar & 0xfffff000) != (v & 0xfffff000))
                                continue;

                        /*  Finally, invalidate the entry:  */
                        cpu->cd.m88k.cmmu[d->cmmu_nr]->patc_v_and_control[i]
                            = v & ~PG_V;
                }

                break;

        default:
                fatal("[ m8820x_command: FATAL ERROR! unimplemented "
                    "command 0x%02x ]\n", cmd);
                exit(1);
        }
}


DEVICE_ACCESS(m8820x)
{
        uint64_t idata = 0, odata = 0;
        struct m8820x_data *d = extra;
        uint32_t *regs = cpu->cd.m88k.cmmu[d->cmmu_nr]->reg;
        uint32_t *batc = cpu->cd.m88k.cmmu[d->cmmu_nr]->batc;

        if (writeflag == MEM_WRITE)
                idata = memory_readmax64(cpu, data, len);

        if (writeflag == MEM_READ)
                odata = regs[relative_addr / sizeof(uint32_t)];

        switch (relative_addr / sizeof(uint32_t)) {

        case CMMU_IDR:
                if (writeflag == MEM_WRITE) {
                        fatal("m8820x: write to CMMU_IDR: TODO\n");
                        exit(1);
                }
                break;

        case CMMU_SCR:
                if (writeflag == MEM_READ) {
                        fatal("m8820x: read from CMMU_SCR: TODO\n");
                        exit(1);
                } else {
                        regs[relative_addr / sizeof(uint32_t)] = idata;
                        m8820x_command(cpu, d);
                }
                break;

        case CMMU_SSR:
                if (writeflag == MEM_WRITE) {
                        fatal("m8820x: write to CMMU_SSR: TODO\n");
                        exit(1);
                }
                break;

        case CMMU_PFSR:
        case CMMU_PFAR:
        case CMMU_SAR:
        case CMMU_SCTR:
        case CMMU_SAPR:         /*  TODO: Invalidate something for  */
        case CMMU_UAPR:         /*  SAPR and UAPR writes?  */
                /*  TODO: Don't invalidate everything.  */
                cpu->invalidate_translation_caches(cpu, 0, INVALIDATE_ALL);
                if (writeflag == MEM_WRITE)
                        regs[relative_addr / sizeof(uint32_t)] = idata;
                break;

        case CMMU_BWP0:
        case CMMU_BWP1:
        case CMMU_BWP2:
        case CMMU_BWP3:
        case CMMU_BWP4:
        case CMMU_BWP5:
        case CMMU_BWP6:
        case CMMU_BWP7:
                if (writeflag == MEM_WRITE) {
                        uint32_t old;

                        regs[relative_addr / sizeof(uint32_t)] = idata;

                        /*  Also write to the specific batc registers:  */
                        old = batc[(relative_addr / sizeof(uint32_t))
                            - CMMU_BWP0];
                        batc[(relative_addr / sizeof(uint32_t)) - CMMU_BWP0]
                            = idata;
                        if (old != idata) {
                                /*  TODO: Don't invalidate everything?  */
                                cpu->invalidate_translation_caches(
                                    cpu, 0, INVALIDATE_ALL);
                        }
                }
                break;

        case CMMU_CSSP0:
                /*  TODO: Actually care about cache details.  */
                break;

        default:fatal("[ m8820x: unimplemented %s offset 0x%x",
                    writeflag == MEM_WRITE? "write to" : "read from",
                    (int) relative_addr);
                if (writeflag == MEM_WRITE)
                        fatal(": 0x%x", (int)idata);
                fatal(" ]\n");
                exit(1);
        }

        if (writeflag == MEM_READ)
                memory_writemax64(cpu, data, len, odata);

        return 1;
}


DEVINIT(m8820x)
{
        struct m8820x_data *d;

        CHECK_ALLOCATION(d = malloc(sizeof(struct m8820x_data)));
        memset(d, 0, sizeof(struct m8820x_data));

        d->cmmu_nr = devinit->addr2;

        memory_device_register(devinit->machine->memory, devinit->name,
            devinit->addr, M8820X_LENGTH, dev_m8820x_access, (void *)d,
            DM_DEFAULT, NULL);

        return 1;
}

1	/*
2	* Copyright (C) 2007 Anders Gavare. All rights reserved.
3	*
4	* Redistribution and use in source and binary forms, with or without
5	* modification, are permitted provided that the following conditions are met:
6	*
7	* 1. Redistributions of source code must retain the above copyright
8	* notice, this list of conditions and the following disclaimer.
9	* 2. Redistributions in binary form must reproduce the above copyright
10	* notice, this list of conditions and the following disclaimer in the
11	* documentation and/or other materials provided with the distribution.
12	* 3. The name of the author may not be used to endorse or promote products
13	* derived from this software without specific prior written permission.
14	*
15	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25	* SUCH DAMAGE.
26	*
27	*
28	* $Id: dev_m8820x.c,v 1.9 2007/06/19 03:38:10 debug Exp $
29	*
30	* COMMENT: M88200/M88204 CMMU (Cache/Memory Management Unit)
31	*/
32
33	#include <stdio.h>
34	#include <stdlib.h>
35	#include <string.h>
36
37	#include "cpu.h"
38	#include "device.h"
39	#include "emul.h"
40	#include "machine.h"
41	#include "memory.h"
42	#include "misc.h"
43
44
45	#include "m8820x.h"
46	#include "m8820x_pte.h"
47
48	struct m8820x_data {
49	int cmmu_nr;
50	};
51
52
53	/*
54	* m8820x_command():
55	*
56	* Handle M8820x commands written to the System Command Register.
57	*/
58	static void m8820x_command(struct cpu cpu, struct m8820x_data d)
59	{
60	uint32_t *regs = cpu->cd.m88k.cmmu[d->cmmu_nr]->reg;
61	int cmd = regs[CMMU_SCR];
62	uint32_t sar = regs[CMMU_SAR];
63	size_t i;
64	uint32_t super, all;
65
66	switch (cmd) {
67
68	case CMMU_FLUSH_CACHE_CB_LINE:
69	case CMMU_FLUSH_CACHE_INV_LINE:
70	case CMMU_FLUSH_CACHE_INV_ALL:
71	case CMMU_FLUSH_CACHE_CBI_LINE:
72	case CMMU_FLUSH_CACHE_CBI_PAGE:
73	case CMMU_FLUSH_CACHE_CBI_SEGMENT:
74	case CMMU_FLUSH_CACHE_CBI_ALL:
75	/* TODO */
76	break;
77
78	case CMMU_FLUSH_USER_ALL:
79	case CMMU_FLUSH_USER_PAGE:
80	case CMMU_FLUSH_SUPER_ALL:
81	case CMMU_FLUSH_SUPER_PAGE:
82	/* TODO: Segment invalidation. */
83
84	all = super = 0;
85	if (cmd == CMMU_FLUSH_USER_ALL \|\|
86	cmd == CMMU_FLUSH_SUPER_ALL)
87	all = 1;
88	if (cmd == CMMU_FLUSH_SUPER_ALL \|\|
89	cmd == CMMU_FLUSH_SUPER_PAGE)
90	super = M8820X_PATC_SUPERVISOR_BIT;
91
92	/* TODO: Don't invalidate EVERYTHING like this! */
93	cpu->invalidate_translation_caches(cpu, 0, INVALIDATE_ALL);
94
95	for (i=0; i<N_M88200_PATC_ENTRIES; i++) {
96	uint32_t v = cpu->cd.m88k.cmmu[d->cmmu_nr]
97	->patc_v_and_control[i];
98	uint32_t p = cpu->cd.m88k.cmmu[d->cmmu_nr]
99	->patc_p_and_supervisorbit[i];
100
101	/* Already invalid? Then skip this entry. */
102	if (!(v & PG_V))
103	continue;
104
105	/* Super/user mismatch? Then skip the entry. */
106	if ((p & M8820X_PATC_SUPERVISOR_BIT) != super)
107	continue;
108
109	/* If not all pages are to be invalidated, there
110	must be a virtual address match: */
111	if (!all && (sar & 0xfffff000) != (v & 0xfffff000))
112	continue;
113
114	/* Finally, invalidate the entry: */
115	cpu->cd.m88k.cmmu[d->cmmu_nr]->patc_v_and_control[i]
116	= v & ~PG_V;
117	}
118
119	break;
120
121	default:
122	fatal("[ m8820x_command: FATAL ERROR! unimplemented "
123	"command 0x%02x ]\n", cmd);
124	exit(1);
125	}
126	}
127
128
129	DEVICE_ACCESS(m8820x)
130	{
131	uint64_t idata = 0, odata = 0;
132	struct m8820x_data *d = extra;
133	uint32_t *regs = cpu->cd.m88k.cmmu[d->cmmu_nr]->reg;
134	uint32_t *batc = cpu->cd.m88k.cmmu[d->cmmu_nr]->batc;
135
136	if (writeflag == MEM_WRITE)
137	idata = memory_readmax64(cpu, data, len);
138
139	if (writeflag == MEM_READ)
140	odata = regs[relative_addr / sizeof(uint32_t)];
141
142	switch (relative_addr / sizeof(uint32_t)) {
143
144	case CMMU_IDR:
145	if (writeflag == MEM_WRITE) {
146	fatal("m8820x: write to CMMU_IDR: TODO\n");
147	exit(1);
148	}
149	break;
150
151	case CMMU_SCR:
152	if (writeflag == MEM_READ) {
153	fatal("m8820x: read from CMMU_SCR: TODO\n");
154	exit(1);
155	} else {
156	regs[relative_addr / sizeof(uint32_t)] = idata;
157	m8820x_command(cpu, d);
158	}
159	break;
160
161	case CMMU_SSR:
162	if (writeflag == MEM_WRITE) {
163	fatal("m8820x: write to CMMU_SSR: TODO\n");
164	exit(1);
165	}
166	break;
167
168	case CMMU_PFSR:
169	case CMMU_PFAR:
170	case CMMU_SAR:
171	case CMMU_SCTR:
172	case CMMU_SAPR: /* TODO: Invalidate something for */
173	case CMMU_UAPR: /* SAPR and UAPR writes? */
174	/* TODO: Don't invalidate everything. */
175	cpu->invalidate_translation_caches(cpu, 0, INVALIDATE_ALL);
176	if (writeflag == MEM_WRITE)
177	regs[relative_addr / sizeof(uint32_t)] = idata;
178	break;
179
180	case CMMU_BWP0:
181	case CMMU_BWP1:
182	case CMMU_BWP2:
183	case CMMU_BWP3:
184	case CMMU_BWP4:
185	case CMMU_BWP5:
186	case CMMU_BWP6:
187	case CMMU_BWP7:
188	if (writeflag == MEM_WRITE) {
189	uint32_t old;
190
191	regs[relative_addr / sizeof(uint32_t)] = idata;
192
193	/* Also write to the specific batc registers: */
194	old = batc[(relative_addr / sizeof(uint32_t))
195	- CMMU_BWP0];
196	batc[(relative_addr / sizeof(uint32_t)) - CMMU_BWP0]
197	= idata;
198	if (old != idata) {
199	/* TODO: Don't invalidate everything? */
200	cpu->invalidate_translation_caches(
201	cpu, 0, INVALIDATE_ALL);
202	}
203	}
204	break;
205
206	case CMMU_CSSP0:
207	/* TODO: Actually care about cache details. */
208	break;
209
210	default:fatal("[ m8820x: unimplemented %s offset 0x%x",
211	writeflag == MEM_WRITE? "write to" : "read from",
212	(int) relative_addr);
213	if (writeflag == MEM_WRITE)
214	fatal(": 0x%x", (int)idata);
215	fatal(" ]\n");
216	exit(1);
217	}
218
219	if (writeflag == MEM_READ)
220	memory_writemax64(cpu, data, len, odata);
221
222	return 1;
223	}
224
225
226	DEVINIT(m8820x)
227	{
228	struct m8820x_data *d;
229
230	CHECK_ALLOCATION(d = malloc(sizeof(struct m8820x_data)));
231	memset(d, 0, sizeof(struct m8820x_data));
232
233	d->cmmu_nr = devinit->addr2;
234
235	memory_device_register(devinit->machine->memory, devinit->name,
236	devinit->addr, M8820X_LENGTH, dev_m8820x_access, (void *)d,
237	DM_DEFAULT, NULL);
238
239	return 1;
240	}
241