/[gxemul]/trunk/src/devices/dev_le.c
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Revision 12 - (show annotations)
Mon Oct 8 16:18:38 2007 UTC (12 years, 3 months ago) by dpavlin
File MIME type: text/plain
File size: 22527 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.905 2005/08/16 09:16:24 debug Exp $
20050628	Continuing the work on the ARM translation engine. end_of_page
		works. Experimenting with load/store translation caches
		(virtual -> physical -> host).
20050629	More ARM stuff (memory access translation cache, mostly). This
		might break a lot of stuff elsewhere, probably some MIPS-
		related translation things.
20050630	Many load/stores are now automatically generated and included
		into cpu_arm_instr.c; 1024 functions in total (!).
		Fixes based on feedback from Alec Voropay: only print 8 hex
		digits instead of 16 in some cases when emulating 32-bit
		machines; similar 8 vs 16 digit fix for breakpoint addresses;
		4Kc has 16 TLB entries, not 48; the MIPS config select1
		register is now printed with "reg ,0".
		Also changing many other occurances of 16 vs 8 digit output.
		Adding cache associativity fields to mips_cpu_types.h; updating
		some other cache fields; making the output of
		mips_cpu_dumpinfo() look nicer.
		Generalizing the bintrans stuff for device accesses to also
		work with the new translation system. (This might also break
		some MIPS things.)
		Adding multi-load/store instructions to the ARM disassembler
		and the translator, and some optimizations of various kinds.
20050701	Adding a simple dev_disk (it can read/write sectors from
		disk images).
20050712	Adding dev_ether (a simple ethernet send/receive device).
		Debugger command "ninstrs" for toggling show_nr_of_instructions
		during runtime.
		Removing the framebuffer logo.
20050713	Continuing on dev_ether.
		Adding a dummy cpu_alpha (again).
20050714	More work on cpu_alpha.
20050715	More work on cpu_alpha. Many instructions work, enough to run
		a simple framebuffer fill test (similar to the ARM test).
20050716	More Alpha stuff.
20050717	Minor updates (Alpha stuff).
20050718	Minor updates (Alpha stuff).
20050719	Generalizing some Alpha instructions.
20050720	More Alpha-related updates.
20050721	Continuing on cpu_alpha. Importing rpb.h from NetBSD/alpha.
20050722	Alpha-related updates: userland stuff (Hello World using
		write() compiled statically for FreeBSD/Alpha runs fine), and
		more instructions are now implemented.
20050723	Fixing ldq_u and stq_u.
		Adding more instructions (conditional moves, masks, extracts,
		shifts).
20050724	More FreeBSD/Alpha userland stuff, and adding some more
		instructions (inserts).
20050725	Continuing on the Alpha stuff. (Adding dummy ldt/stt.)
		Adding a -A command line option to turn off alignment checks
		in some cases (for translated code).
		Trying to remove the old bintrans code which updated the pc
		and nr_of_executed_instructions for every instruction.
20050726	Making another attempt att removing the pc/nr of instructions
		code. This time it worked, huge performance increase for
		artificial test code, but performance loss for real-world
		code :-( so I'm scrapping that code for now.
		Tiny performance increase on Alpha (by using ret instead of
		jmp, to play nice with the Alpha's branch prediction) for the
		old MIPS bintrans backend.
20050727	Various minor fixes and cleanups.
20050728	Switching from a 2-level virtual to host/physical translation
		system for ARM emulation, to a 1-level translation.
		Trying to switch from 2-level to 1-level for the MIPS bintrans
		system as well (Alpha only, so far), but there is at least one
		problem: caches and/or how they work with device mappings.
20050730	Doing the 2-level to 1-level conversion for the i386 backend.
		The cache/device bug is still there for R2K/3K :(
		Various other minor updates (Malta etc).
		The mc146818 clock now updates the UIP bit in a way which works
		better with Linux for at least sgimips and Malta emulation.
		Beginning the work on refactoring the dyntrans system.
20050731	Continuing the dyntrans refactoring.
		Fixing a small but serious host alignment bug in memory_rw.
		Adding support for big-endian load/stores to the i386 bintrans
		backend.
		Another minor i386 bintrans backend update: stores from the
		zero register are now one (or two) loads shorter.
		The slt and sltu instructions were incorrectly implemented for
		the i386 backend; only using them for 32-bit mode for now.
20050801	Continuing the dyntrans refactoring.
		Cleanup of the ns16550 serial controller (removing unnecessary
		code).
		Bugfix (memory corruption bug) in dev_gt, and a patch/hack from
		Alec Voropay for Linux/Malta.
20050802	More cleanup/refactoring of the dyntrans subsystem: adding
		phys_page pointers to the lookup tables, for quick jumps
		between translated pages.
		Better fix for the ns16550 device (but still no real FIFO
		functionality).
		Converting cpu_ppc to the new dyntrans system. This means that
		I will have to start from scratch with implementing each
		instruction, and figure out how to implement dual 64/32-bit
		modes etc.
		Removing the URISC CPU family, because it was useless.
20050803	When selecting a machine type, the main type can now be omitted
		if the subtype name is unique. (I.e. -E can be omitted.)
		Fixing a dyntrans/device update bug. (Writes to offset 0 of
		a device could sometimes go unnoticed.)
		Adding an experimental "instruction combination" hack for
		ARM for memset-like byte fill loops.
20050804	Minor progress on cpu_alpha and related things.
		Finally fixing the MIPS dmult/dmultu bugs.
		Fixing some minor TODOs.
20050805	Generalizing the 8259 PIC. It now also works with Cobalt
		and evbmips emulation, in addition to the x86 hack.
		Finally converting the ns16550 device to use devinit.
		Continuing the work on the dyntrans system. Thinking about
		how to add breakpoints.
20050806	More dyntrans updates. Breakpoints seem to work now.
20050807	Minor updates: cpu_alpha and related things; removing
		dev_malta (as it isn't used any more).
		Dyntrans: working on general "show trace tree" support.
		The trace tree stuff now works with both the old MIPS code and
		with newer dyntrans modes. :)
		Continuing on Alpha-related stuff (trying to get *BSD to boot
		a bit further, adding more instructions, etc).
20050808	Adding a dummy IA64 cpu family, and continuing the refactoring
		of the dyntrans system.
		Removing the regression test stuff, because it was more or
		less useless.
		Adding loadlinked/storeconditional type instructions to the
		Alpha emulation. (Needed for Linux/alpha. Not very well tested
		yet.)
20050809	The function call trace tree now prints a per-function nr of
		arguments. (Semi-meaningless, since that data isn't read yet
		from the ELFs; some hardcoded symbols such as memcpy() and
		strlen() work fine, though.)
		More dyntrans refactoring; taking out more of the things that
		are common to all cpu families.
20050810	Working on adding support for "dual mode" for PPC dyntrans
		(i.e. both 64-bit and 32-bit modes).
		(Re)adding some simple PPC instructions.
20050811	Adding a dummy M68K cpu family. The dyntrans system isn't ready
		for variable-length ISAs yet, so it's completely bogus so far.
		Re-adding more PPC instructions.
		Adding a hack to src/file.c which allows OpenBSD/mac68k a.out
		kernels to be loaded.
		Beginning to add PPC loads/stores. So far they only work in
		32-bit mode.
20050812	The configure file option "add_remote" now accepts symbolic
		host names, in addition to numeric IPv4 addresses.
		Re-adding more PPC instructions.
20050814	Continuing to port back more PPC instructions.
		Found and fixed the cache/device write-update bug for 32-bit
		MIPS bintrans. :-)
		Triggered a really weird and annoying bug in Compaq's C
		compiler; ccc sometimes outputs code which loads from an
		address _before_ checking whether the pointer was NULL or not.
		(I'm not sure how to handle this problem.)
20050815	Removing all of the old x86 instruction execution code; adding
		a new (dummy) dyntrans module for x86.
		Taking the first steps to extend the dyntrans system to support
		variable-length instructions.
		Slowly preparing for the next release.
20050816	Adding a dummy SPARC cpu module.
		Minor updates (documentation etc) for the release.

==============  RELEASE 0.3.5  ==============


1 /*
2 * Copyright (C) 2003-2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_le.c,v 1.43 2005/07/27 06:57:34 debug Exp $
29 *
30 * LANCE ethernet, as used in DECstations.
31 *
32 * This is based on "PMAD-AA TURBOchannel Ethernet Module Functional
33 * Specification". I've tried to keep symbol names in this file to what
34 * the specs use.
35 *
36 * This is what the memory layout looks like on a DECstation 5000/200:
37 *
38 * 0x000000 - 0x0fffff Ethernet SRAM buffer (should be 128KB)
39 * 0x100000 - 0x17ffff LANCE registers
40 * 0x1c0000 - 0x1fffff Ethernet Diagnostic ROM and Station
41 * Address ROM
42 *
43 * The length of the device is set to 0x1c0200, however, because Sprite
44 * tries to read TURBOchannel rom data from 0x1c03f0, and that is provided
45 * by the turbochannel device, not this device.
46 *
47 *
48 * TODO: Error conditions (such as when there are not enough receive
49 * buffers) are not emulated yet.
50 */
51
52 #include <stdio.h>
53 #include <stdlib.h>
54 #include <string.h>
55
56 #include "cpu.h"
57 #include "devices.h"
58 #include "emul.h"
59 #include "machine.h"
60 #include "memory.h"
61 #include "misc.h"
62 #include "net.h"
63
64 #include "if_lereg.h"
65
66
67 #define LE_TICK_SHIFT 14
68
69 /* #define LE_DEBUG */
70 /* #define debug fatal */
71
72 extern int quiet_mode;
73
74 #define LE_MODE_LOOP 4
75 #define LE_MODE_DTX 2
76 #define LE_MODE_DRX 1
77
78
79 #define N_REGISTERS 4
80 #define SRAM_SIZE (128*1024)
81 #define ROM_SIZE 32
82
83
84 struct le_data {
85 int irq_nr;
86
87 uint64_t buf_start;
88 uint64_t buf_end;
89 int len;
90
91 uint8_t rom[ROM_SIZE];
92
93 int reg_select;
94 uint16_t reg[N_REGISTERS];
95
96 unsigned char *sram;
97
98 /* Initialization block: */
99 uint32_t init_block_addr;
100
101 uint16_t mode;
102 uint64_t padr; /* MAC address */
103 uint64_t ladrf;
104 uint32_t rdra; /* receive descriptor ring address */
105 int rlen; /* nr of rx descriptors */
106 uint32_t tdra; /* transmit descriptor ring address */
107 int tlen; /* nr ot tx descriptors */
108
109 /* Current rx and tx descriptor indices: */
110 int rxp;
111 int txp;
112
113 unsigned char *tx_packet;
114 int tx_packet_len;
115
116 unsigned char *rx_packet;
117 int rx_packet_len;
118 int rx_packet_offset;
119 int rx_middle_bit;
120 };
121
122
123 /*
124 * le_read_16bit():
125 *
126 * Read a 16-bit word from the SRAM.
127 */
128 static uint64_t le_read_16bit(struct le_data *d, int addr)
129 {
130 /* TODO: This is for little endian only */
131 int x = d->sram[addr & (SRAM_SIZE-1)] +
132 (d->sram[(addr+1) & (SRAM_SIZE-1)] << 8);
133 return x;
134 }
135
136
137 /*
138 * le_write_16bit():
139 *
140 * Write a 16-bit word to the SRAM.
141 */
142 static void le_write_16bit(struct le_data *d, int addr, uint16_t x)
143 {
144 /* TODO: This is for little endian only */
145 d->sram[addr & (SRAM_SIZE-1)] = x & 0xff;
146 d->sram[(addr+1) & (SRAM_SIZE-1)] = (x >> 8) & 0xff;
147 }
148
149
150 /*
151 * le_chip_init():
152 *
153 * Initialize data structures by reading an 'initialization block' from the
154 * SRAM.
155 */
156 static void le_chip_init(struct le_data *d)
157 {
158 d->init_block_addr = (d->reg[1] & 0xffff) + ((d->reg[2] & 0xff) << 16);
159 if (d->init_block_addr & 1)
160 fatal("[ le: WARNING! initialization block address "
161 "not word aligned? ]\n");
162
163 debug("[ le: d->init_block_addr = 0x%06x ]\n", d->init_block_addr);
164
165 d->mode = le_read_16bit(d, d->init_block_addr + 0);
166 d->padr = le_read_16bit(d, d->init_block_addr + 2);
167 d->padr += (le_read_16bit(d, d->init_block_addr + 4) << 16);
168 d->padr += (le_read_16bit(d, d->init_block_addr + 6) << 32);
169 d->ladrf = le_read_16bit(d, d->init_block_addr + 8);
170 d->ladrf += (le_read_16bit(d, d->init_block_addr + 10) << 16);
171 d->ladrf += (le_read_16bit(d, d->init_block_addr + 12) << 32);
172 d->ladrf += (le_read_16bit(d, d->init_block_addr + 14) << 48);
173 d->rdra = le_read_16bit(d, d->init_block_addr + 16);
174 d->rdra += ((le_read_16bit(d, d->init_block_addr + 18) & 0xff) << 16);
175 d->rlen = 1 << ((le_read_16bit(d, d->init_block_addr + 18) >> 13) & 7);
176 d->tdra = le_read_16bit(d, d->init_block_addr + 20);
177 d->tdra += ((le_read_16bit(d, d->init_block_addr + 22) & 0xff) << 16);
178 d->tlen = 1 << ((le_read_16bit(d, d->init_block_addr + 22) >> 13) & 7);
179
180 debug("[ le: DEBUG: mode %04x ]\n", d->mode);
181 debug("[ le: DEBUG: padr %016llx ]\n", (long long)d->padr);
182 debug("[ le: DEBUG: ladrf %016llx ]\n", (long long)d->ladrf);
183 debug("[ le: DEBUG: rdra %06llx ]\n", d->rdra);
184 debug("[ le: DEBUG: rlen %3i ]\n", d->rlen);
185 debug("[ le: DEBUG: tdra %06llx ]\n", d->tdra);
186 debug("[ le: DEBUG: tlen %3i ]\n", d->tlen);
187
188 /* Set TXON and RXON, unless they are disabled by 'mode': */
189 if (d->mode & LE_MODE_DTX)
190 d->reg[0] &= ~LE_TXON;
191 else
192 d->reg[0] |= LE_TXON;
193
194 if (d->mode & LE_MODE_DRX)
195 d->reg[0] &= ~LE_RXON;
196 else
197 d->reg[0] |= LE_RXON;
198
199 /* Go to the start of the descriptor rings: */
200 d->rxp = d->txp = 0;
201
202 /* Set IDON and reset the INIT bit when we are done. */
203 d->reg[0] |= LE_IDON;
204 d->reg[0] &= ~LE_INIT;
205
206 /* Free any old packets: */
207 if (d->tx_packet != NULL)
208 free(d->tx_packet);
209 d->tx_packet = NULL;
210 d->tx_packet_len = 0;
211
212 if (d->rx_packet != NULL)
213 free(d->rx_packet);
214 d->rx_packet = NULL;
215 d->rx_packet_len = 0;
216 d->rx_packet_offset = 0;
217 d->rx_middle_bit = 0;
218 }
219
220
221 /*
222 * le_tx():
223 *
224 * Check the transmitter descriptor ring for buffers that are owned by the
225 * Lance chip (that is, buffers that are to be transmitted).
226 *
227 * This routine should only be called if TXON is enabled.
228 */
229 static void le_tx(struct net *net, struct le_data *d)
230 {
231 int start_txp = d->txp;
232 uint16_t tx_descr[4];
233 int stp, enp, i, cur_packet_offset;
234 uint32_t bufaddr, buflen;
235
236 /* TODO: This is just a guess: */
237 d->reg[0] &= ~LE_TDMD;
238
239 do {
240 /* Load the 8 descriptor bytes: */
241 tx_descr[0] = le_read_16bit(d, d->tdra + d->txp*8 + 0);
242 tx_descr[1] = le_read_16bit(d, d->tdra + d->txp*8 + 2);
243 tx_descr[2] = le_read_16bit(d, d->tdra + d->txp*8 + 4);
244 tx_descr[3] = le_read_16bit(d, d->tdra + d->txp*8 + 6);
245
246 bufaddr = tx_descr[0] + ((tx_descr[1] & 0xff) << 16);
247 stp = tx_descr[1] & LE_STP? 1 : 0;
248 enp = tx_descr[1] & LE_ENP? 1 : 0;
249 buflen = 4096 - (tx_descr[2] & 0xfff);
250
251 /*
252 * Check the OWN bit. If it is zero, then this buffer is
253 * not ready to be transmitted yet. Also check the '1111'
254 * mark, and make sure that byte-count is reasonable.
255 */
256 if (!(tx_descr[1] & LE_OWN))
257 return;
258 if ((tx_descr[2] & 0xf000) != 0xf000)
259 return;
260 if (buflen < 12 || buflen > 1900) {
261 fatal("[ le_tx(): buflen = %i ]\n", buflen);
262 return;
263 }
264
265 debug("[ le_tx(): descr %3i DUMP: 0x%04x 0x%04x 0x%04x 0x%04x "
266 "=> addr=0x%06x, len=%i bytes, STP=%i ENP=%i ]\n", d->txp,
267 tx_descr[0], tx_descr[1], tx_descr[2], tx_descr[3],
268 bufaddr, buflen, stp, enp);
269
270 if (d->tx_packet == NULL && !stp) {
271 fatal("[ le_tx(): !stp but tx_packet == NULL ]\n");
272 return;
273 }
274
275 if (d->tx_packet != NULL && stp) {
276 fatal("[ le_tx(): stp but tx_packet != NULL ]\n");
277 free(d->tx_packet);
278 d->tx_packet = NULL;
279 d->tx_packet_len = 0;
280 }
281
282 /* Where to write to in the tx_packet: */
283 cur_packet_offset = d->tx_packet_len;
284
285 /* Start of a new packet: */
286 if (stp) {
287 d->tx_packet_len = buflen;
288 d->tx_packet = malloc(buflen);
289 if (d->tx_packet == NULL) {
290 fprintf(stderr, "out of memory (1) in "
291 "le_tx()\n");
292 exit(1);
293 }
294 } else {
295 d->tx_packet_len += buflen;
296 d->tx_packet = realloc(d->tx_packet, d->tx_packet_len);
297 if (d->tx_packet == NULL) {
298 fprintf(stderr, "out of memory (2) in"
299 " le_tx()\n");
300 exit(1);
301 }
302 }
303
304 /* Copy data from SRAM into the tx packet: */
305 for (i=0; i<buflen; i++) {
306 unsigned char ch;
307 ch = d->sram[(bufaddr + i) & (SRAM_SIZE-1)];
308 d->tx_packet[cur_packet_offset + i] = ch;
309 }
310
311 /*
312 * Is this the last buffer in a packet? Then transmit
313 * it, cause an interrupt, and free the memory used by
314 * the packet.
315 */
316 if (enp) {
317 net_ethernet_tx(net, d, d->tx_packet, d->tx_packet_len);
318
319 free(d->tx_packet);
320 d->tx_packet = NULL;
321 d->tx_packet_len = 0;
322
323 d->reg[0] |= LE_TINT;
324 }
325
326 /* Clear the OWN bit: */
327 tx_descr[1] &= ~LE_OWN;
328
329 /* Write back the descriptor to SRAM: */
330 le_write_16bit(d, d->tdra + d->txp*8 + 2, tx_descr[1]);
331 le_write_16bit(d, d->tdra + d->txp*8 + 4, tx_descr[2]);
332 le_write_16bit(d, d->tdra + d->txp*8 + 6, tx_descr[3]);
333
334 /* Go to the next descriptor: */
335 d->txp ++;
336 if (d->txp >= d->tlen)
337 d->txp = 0;
338 } while (d->txp != start_txp);
339
340 /* We are here if all descriptors were taken care of. */
341 fatal("[ le_tx(): all TX descriptors used up? ]\n");
342 }
343
344
345 /*
346 * le_rx():
347 *
348 * This routine should only be called if RXON is enabled.
349 */
350 static void le_rx(struct net *net, struct le_data *d)
351 {
352 int i, start_rxp = d->rxp;
353 uint16_t rx_descr[4];
354 uint32_t bufaddr, buflen;
355
356 do {
357 if (d->rx_packet == NULL)
358 return;
359
360 /* Load the 8 descriptor bytes: */
361 rx_descr[0] = le_read_16bit(d, d->rdra + d->rxp*8 + 0);
362 rx_descr[1] = le_read_16bit(d, d->rdra + d->rxp*8 + 2);
363 rx_descr[2] = le_read_16bit(d, d->rdra + d->rxp*8 + 4);
364 rx_descr[3] = le_read_16bit(d, d->rdra + d->rxp*8 + 6);
365
366 bufaddr = rx_descr[0] + ((rx_descr[1] & 0xff) << 16);
367 buflen = 4096 - (rx_descr[2] & 0xfff);
368
369 /*
370 * Check the OWN bit. If it is zero, then this buffer is
371 * not ready to receive data yet. Also check the '1111'
372 * mark, and make sure that byte-count is reasonable.
373 */
374 if (!(rx_descr[1] & LE_OWN))
375 return;
376 if ((rx_descr[2] & 0xf000) != 0xf000)
377 return;
378 if (buflen < 12 || buflen > 1900) {
379 fatal("[ le_rx(): buflen = %i ]\n", buflen);
380 return;
381 }
382
383 debug("[ le_rx(): descr %3i DUMP: 0x%04x 0x%04x 0x%04x 0x%04x "
384 "=> addr=0x%06x, len=%i bytes ]\n", d->rxp,
385 rx_descr[0], rx_descr[1], rx_descr[2], rx_descr[3],
386 bufaddr, buflen);
387
388 /* Copy data from the packet into SRAM: */
389 for (i=0; i<buflen; i++) {
390 if (d->rx_packet_offset + i >= d->rx_packet_len)
391 break;
392 d->sram[(bufaddr + i) & (SRAM_SIZE-1)] =
393 d->rx_packet[d->rx_packet_offset + i];
394 }
395
396 /* Here, i is the number of bytes copied. */
397 d->rx_packet_offset += i;
398
399 /* Set the ENP bit if this was the end of a packet: */
400 if (d->rx_packet_offset >= d->rx_packet_len) {
401 rx_descr[1] |= LE_ENP;
402
403 /*
404 * NOTE: The Lance documentation that I have read
405 * says _NOTHING_ about the length being 4 more than
406 * the length of the data. You can guess how
407 * surprised I was when I saw the following in
408 * NetBSD (dev/ic/am7990.c):
409 *
410 * lance_read(sc, LE_RBUFADDR(sc, bix),
411 * (int)rmd.rmd3 - 4);
412 */
413 rx_descr[3] &= ~0xfff;
414 rx_descr[3] |= d->rx_packet_len + 4;
415
416 free(d->rx_packet);
417 d->rx_packet = NULL;
418 d->rx_packet_len = 0;
419 d->rx_packet_offset = 0;
420 d->rx_middle_bit = 0;
421
422 d->reg[0] |= LE_RINT;
423 }
424
425 /* Set the STP bit if this was the start of a packet: */
426 if (!d->rx_middle_bit) {
427 rx_descr[1] |= LE_STP;
428
429 /* Are we continuing on this packet? */
430 if (d->rx_packet != NULL)
431 d->rx_middle_bit = 1;
432 }
433
434 /* Clear the OWN bit: */
435 rx_descr[1] &= ~LE_OWN;
436
437 /* Write back the descriptor to SRAM: */
438 le_write_16bit(d, d->rdra + d->rxp*8 + 2, rx_descr[1]);
439 le_write_16bit(d, d->rdra + d->rxp*8 + 4, rx_descr[2]);
440 le_write_16bit(d, d->rdra + d->rxp*8 + 6, rx_descr[3]);
441
442 /* Go to the next descriptor: */
443 d->rxp ++;
444 if (d->rxp >= d->rlen)
445 d->rxp = 0;
446 } while (d->rxp != start_rxp);
447
448 /* We are here if all descriptors were taken care of. */
449 fatal("[ le_rx(): all RX descriptors used up? ]\n");
450 }
451
452
453 /*
454 * le_register_fix():
455 */
456 static void le_register_fix(struct net *net, struct le_data *d)
457 {
458 /* Init with new Initialization block, if needed. */
459 if (d->reg[0] & LE_INIT)
460 le_chip_init(d);
461
462 #ifdef LE_DEBUG
463 {
464 static int x = 1234;
465 if (x != d->reg[0]) {
466 debug("[ le reg[0] = 0x%04x ]\n", d->reg[0]);
467 x = d->reg[0];
468 }
469 }
470 #endif
471
472 /*
473 * If the receiver is on:
474 * If there is a current rx_packet, try to receive it into the
475 * Lance buffers. Then try to receive any additional packets.
476 */
477 if (d->reg[0] & LE_RXON) {
478 do {
479 if (d->rx_packet != NULL)
480 /* Try to receive the packet: */
481 le_rx(net, d);
482
483 if (d->rx_packet != NULL)
484 /* If the packet wasn't fully received,
485 then abort for now. */
486 break;
487
488 if (d->rx_packet == NULL &&
489 net_ethernet_rx_avail(net, d))
490 net_ethernet_rx(net, d,
491 &d->rx_packet, &d->rx_packet_len);
492 } while (d->rx_packet != NULL);
493 }
494
495 /* If the transmitter is on, check for outgoing buffers: */
496 if (d->reg[0] & LE_TXON)
497 le_tx(net, d);
498
499 /* SERR should be the OR of BABL, CERR, MISS, and MERR: */
500 d->reg[0] &= ~LE_SERR;
501 if (d->reg[0] & (LE_BABL | LE_CERR | LE_MISS | LE_MERR))
502 d->reg[0] |= LE_SERR;
503
504 /* INTR should be the OR of BABL, MISS, MERR, RINT, TINT, IDON: */
505 d->reg[0] &= ~LE_INTR;
506 if (d->reg[0] & (LE_BABL | LE_MISS | LE_MERR | LE_RINT |
507 LE_TINT | LE_IDON))
508 d->reg[0] |= LE_INTR;
509
510 /* The MERR bit clears some bits: */
511 if (d->reg[0] & LE_MERR)
512 d->reg[0] &= ~(LE_RXON | LE_TXON);
513
514 /* The STOP bit clears a lot of stuff: */
515 #if 0
516 /* According to the LANCE manual: (doesn't work with Ultrix) */
517 if (d->reg[0] & LE_STOP)
518 d->reg[0] &= ~(LE_SERR | LE_BABL | LE_CERR | LE_MISS | LE_MERR
519 | LE_RINT | LE_TINT | LE_IDON | LE_INTR | LE_INEA
520 | LE_RXON | LE_TXON | LE_TDMD);
521 #else
522 /* Works with Ultrix: */
523 if (d->reg[0] & LE_STOP)
524 d->reg[0] &= ~(LE_IDON);
525 #endif
526 }
527
528
529 /*
530 * dev_le_tick():
531 */
532 void dev_le_tick(struct cpu *cpu, void *extra)
533 {
534 struct le_data *d = (struct le_data *) extra;
535
536 le_register_fix(cpu->machine->emul->net, d);
537
538 if (d->reg[0] & LE_INTR && d->reg[0] & LE_INEA)
539 cpu_interrupt(cpu, d->irq_nr);
540 else
541 cpu_interrupt_ack(cpu, d->irq_nr);
542 }
543
544
545 /*
546 * le_register_write():
547 *
548 * This function is called when the value 'x' is written to register 'r'.
549 */
550 void le_register_write(struct le_data *d, int r, uint32_t x)
551 {
552 switch (r) {
553 case 0: /* CSR0: */
554 /* Some bits are write-one-to-clear: */
555 if (x & LE_BABL)
556 d->reg[r] &= ~LE_BABL;
557 if (x & LE_CERR)
558 d->reg[r] &= ~LE_CERR;
559 if (x & LE_MISS)
560 d->reg[r] &= ~LE_MISS;
561 if (x & LE_MERR)
562 d->reg[r] &= ~LE_MERR;
563 if (x & LE_RINT)
564 d->reg[r] &= ~LE_RINT;
565 if (x & LE_TINT)
566 d->reg[r] &= ~LE_TINT;
567 if (x & LE_IDON)
568 d->reg[r] &= ~LE_IDON;
569
570 /* Some bits are write-only settable, not clearable: */
571 if (x & LE_TDMD)
572 d->reg[r] |= LE_TDMD;
573 if (x & LE_STRT) {
574 d->reg[r] |= LE_STRT;
575 d->reg[r] &= ~LE_STOP;
576 }
577 if (x & LE_INIT) {
578 if (!(d->reg[r] & LE_STOP))
579 fatal("[ le: attempt to INIT before"
580 " STOPped! ]\n");
581 d->reg[r] |= LE_INIT;
582 d->reg[r] &= ~LE_STOP;
583 }
584 if (x & LE_STOP) {
585 d->reg[r] |= LE_STOP;
586 /* STOP takes precedence over STRT and INIT: */
587 d->reg[r] &= ~(LE_STRT | LE_INIT);
588 }
589
590 /* Some bits get through, both settable and clearable: */
591 d->reg[r] &= ~LE_INEA;
592 d->reg[r] |= (x & LE_INEA);
593 break;
594
595 default:
596 /* CSR1, CSR2, and CSR3: */
597 d->reg[r] = x;
598 }
599 }
600
601
602 /*
603 * dev_le_sram_access():
604 */
605 int dev_le_sram_access(struct cpu *cpu, struct memory *mem,
606 uint64_t relative_addr, unsigned char *data, size_t len,
607 int writeflag, void *extra)
608 {
609 int i, retval;
610 struct le_data *d = extra;
611
612 #ifdef LE_DEBUG
613 if (writeflag == MEM_WRITE) {
614 fatal("[ le_sram: write to addr 0x%06x: ", (int)relative_addr);
615 for (i=0; i<len; i++)
616 fatal("%02x ", data[i]);
617 fatal("]\n");
618 }
619 #endif
620
621 /* Read/write of the SRAM: */
622 if (relative_addr < SRAM_SIZE && relative_addr + len <= SRAM_SIZE) {
623 if (writeflag == MEM_READ) {
624 memcpy(data, d->sram + relative_addr, len);
625 if (!quiet_mode) {
626 debug("[ le: read from SRAM offset 0x%05x:",
627 relative_addr);
628 for (i=0; i<len; i++)
629 debug(" %02x", data[i]);
630 debug(" ]\n");
631 }
632 retval = 9; /* 9 cycles */
633 } else {
634 memcpy(d->sram + relative_addr, data, len);
635 if (!quiet_mode) {
636 debug("[ le: write to SRAM offset 0x%05x:",
637 relative_addr);
638 for (i=0; i<len; i++)
639 debug(" %02x", data[i]);
640 debug(" ]\n");
641 }
642 retval = 6; /* 6 cycles */
643 }
644 return retval;
645 }
646
647 return 0;
648 }
649
650
651 /*
652 * dev_le_access():
653 */
654 int dev_le_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr,
655 unsigned char *data, size_t len, int writeflag, void *extra)
656 {
657 uint64_t idata = 0, odata = 0;
658 int i, retval = 1;
659 struct le_data *d = extra;
660
661 idata = memory_readmax64(cpu, data, len);
662
663 #ifdef LE_DEBUG
664 if (writeflag == MEM_WRITE) {
665 fatal("[ le: write to addr 0x%06x: ", (int)relative_addr);
666 for (i=0; i<len; i++)
667 fatal("%02x ", data[i]);
668 fatal("]\n");
669 }
670 #endif
671
672 /* Read from station's ROM (ethernet address): */
673 if (relative_addr >= 0xc0000 && relative_addr <= 0xfffff) {
674 i = (relative_addr & 0xff) / 4;
675 i = d->rom[i & (ROM_SIZE-1)];
676
677 if (writeflag == MEM_READ) {
678 odata = (i << 24) + (i << 16) + (i << 8) + i;
679 } else {
680 fatal("[ le: WRITE to ethernet addr (%08lx):",
681 (long)relative_addr);
682 for (i=0; i<len; i++)
683 fatal(" %02x", data[i]);
684 fatal(" ]\n");
685 }
686
687 retval = 13; /* 13 cycles */
688 goto do_return;
689 }
690
691
692 switch (relative_addr) {
693
694 /* Register read/write: */
695 case 0:
696 if (writeflag==MEM_READ) {
697 odata = d->reg[d->reg_select];
698 if (!quiet_mode)
699 debug("[ le: read from register 0x%02x: 0x"
700 "%02x ]\n", d->reg_select, (int)odata);
701 /*
702 * A read from csr1..3 should return "undefined"
703 * result if the stop bit is set. However, Ultrix
704 * seems to do just that, so let's _not_ print
705 * a warning here.
706 */
707 } else {
708 if (!quiet_mode)
709 debug("[ le: write to register 0x%02x: 0x"
710 "%02x ]\n", d->reg_select, (int)idata);
711 /*
712 * A write to from csr1..3 when the stop bit is
713 * set should be ignored. However, Ultrix writes
714 * even if the stop bit is set, so let's _not_
715 * print a warning about it.
716 */
717 le_register_write(d, d->reg_select, idata);
718 }
719 break;
720
721 /* Register select: */
722 case 4:
723 if (writeflag==MEM_READ) {
724 odata = d->reg_select;
725 if (!quiet_mode)
726 debug("[ le: read from register select: "
727 "0x%02x ]\n", (int)odata);
728 } else {
729 if (!quiet_mode)
730 debug("[ le: write to register select: "
731 "0x%02x ]\n", (int)idata);
732 d->reg_select = idata & (N_REGISTERS - 1);
733 if (idata >= N_REGISTERS)
734 fatal("[ le: WARNING! register select %i "
735 "(max is %i) ]\n", idata, N_REGISTERS - 1);
736 }
737 break;
738
739 default:
740 if (writeflag==MEM_READ) {
741 fatal("[ le: read from UNIMPLEMENTED addr 0x%06x ]\n",
742 (int)relative_addr);
743 } else {
744 fatal("[ le: write to UNIMPLEMENTED addr 0x%06x: "
745 "0x%08x ]\n", (int)relative_addr, (int)idata);
746 }
747 }
748
749 do_return:
750 if (writeflag == MEM_READ) {
751 memory_writemax64(cpu, data, len, odata);
752 #ifdef LE_DEBUG
753 fatal("[ le: read from addr 0x%06x: 0x%08x ]\n",
754 relative_addr, odata);
755 #endif
756 }
757
758 dev_le_tick(cpu, extra);
759
760 return retval;
761 }
762
763
764 /*
765 * dev_le_init():
766 */
767 void dev_le_init(struct machine *machine, struct memory *mem, uint64_t baseaddr,
768 uint64_t buf_start, uint64_t buf_end, int irq_nr, int len)
769 {
770 char *name2;
771 size_t nlen = 55;
772 struct le_data *d = malloc(sizeof(struct le_data));
773
774 if (d == NULL) {
775 fprintf(stderr, "out of memory\n");
776 exit(1);
777 }
778
779 memset(d, 0, sizeof(struct le_data));
780 d->irq_nr = irq_nr;
781
782 d->sram = malloc(SRAM_SIZE);
783 if (d->sram == NULL) {
784 fprintf(stderr, "out of memory\n");
785 exit(1);
786 }
787 memset(d->sram, 0, SRAM_SIZE);
788
789 /* TODO: Are these actually used yet? */
790 d->len = len;
791 d->buf_start = buf_start;
792 d->buf_end = buf_end;
793
794 /* Initial register contents: */
795 d->reg[0] = LE_STOP;
796
797 d->tx_packet = NULL;
798 d->rx_packet = NULL;
799
800 /* ROM (including the MAC address): */
801 net_generate_unique_mac(machine, &d->rom[0]);
802
803 /*
804 * NOTE: According to the Lance documentation, the low order bit of
805 * a physical MAC address should be clear. However, NetBSD and
806 * Linux drop packets if the _first_ byte's lowest bit is not zero.
807 */
808 d->rom[0] &= ~1;
809 d->rom[5] &= ~1;
810
811 /* Copies of the MAC address and a test pattern: */
812 d->rom[10] = d->rom[21] = d->rom[5];
813 d->rom[11] = d->rom[20] = d->rom[4];
814 d->rom[12] = d->rom[19] = d->rom[3];
815 d->rom[7] = d->rom[8] = d->rom[23] =
816 d->rom[13] = d->rom[18] = d->rom[2];
817 d->rom[6] = d->rom[9] = d->rom[22] =
818 d->rom[14] = d->rom[17] = d->rom[1];
819 d->rom[15] = d->rom[16] = d->rom[0];
820 d->rom[24] = d->rom[28] = 0xff;
821 d->rom[25] = d->rom[29] = 0x00;
822 d->rom[26] = d->rom[30] = 0x55;
823 d->rom[27] = d->rom[31] = 0xaa;
824
825 memory_device_register(mem, "le_sram", baseaddr,
826 SRAM_SIZE, dev_le_sram_access, (void *)d,
827 MEM_DYNTRANS_OK | MEM_DYNTRANS_WRITE_OK
828 | MEM_READING_HAS_NO_SIDE_EFFECTS, d->sram);
829
830 name2 = malloc(nlen);
831 if (name2 == NULL) {
832 fprintf(stderr, "out of memory in dev_le_init()\n");
833 exit(1);
834 }
835 snprintf(name2, nlen, "le [%02x:%02x:%02x:%02x:%02x:%02x]",
836 d->rom[0], d->rom[1], d->rom[2], d->rom[3], d->rom[4], d->rom[5]);
837
838 memory_device_register(mem, name2, baseaddr + 0x100000,
839 len - 0x100000, dev_le_access, (void *)d, MEM_DEFAULT, NULL);
840
841 machine_add_tickfunction(machine, dev_le_tick, d, LE_TICK_SHIFT);
842
843 net_add_nic(machine->emul->net, d, &d->rom[0]);
844 }
845

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