/[gxemul]/trunk/src/devices/dev_lca.c
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Contents of /trunk/src/devices/dev_lca.c

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Revision 32 - (show annotations)
Mon Oct 8 16:20:58 2007 UTC (11 years, 11 months ago) by dpavlin
File MIME type: text/plain
File size: 8959 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1421 2006/11/06 05:32:37 debug Exp $
20060816	Adding a framework for emulated/virtual timers (src/timer.c),
		using only setitimer().
		Rewriting the mc146818 to use the new timer framework.
20060817	Adding a call to gettimeofday() every now and then (once every
		second, at the moment) to resynch the timer if it drifts.
		Beginning to convert the ISA timer interrupt mechanism (8253
		and 8259) to use the new timer framework.
		Removing the -I command line option.
20060819	Adding the -I command line option again, with new semantics.
		Working on Footbridge timer interrupts; NetBSD/NetWinder and
		NetBSD/CATS now run at correct speed, but unfortunately with
		HUGE delays during bootup.
20060821	Some minor m68k updates. Adding the first instruction: nop. :)
		Minor Alpha emulation updates.
20060822	Adding a FreeBSD development specific YAMON environment
		variable ("khz") (as suggested by Bruce M. Simpson).
		Moving YAMON environment variable initialization from
		machine_evbmips.c into promemul/yamon.c, and adding some more
		variables.
		Continuing on the LCA PCI bus controller (for Alpha machines).
20060823	Continuing on the timer stuff: experimenting with MIPS count/
		compare interrupts connected to the timer framework.
20060825	Adding bogus SCSI commands 0x51 (SCSICDROM_READ_DISCINFO) and
		0x52 (SCSICDROM_READ_TRACKINFO) to the SCSI emulation layer,
		to allow NetBSD/pmax 4.0_BETA to be installed from CDROM.
		Minor updates to the LCA PCI controller.
20060827	Implementing a CHIP8 cpu mode, and a corresponding CHIP8
		machine, for fun. Disassembly support for all instructions,
		and most of the common instructions have been implemented: mvi,
		mov_imm, add_imm, jmp, rand, cls, sprite, skeq_imm, jsr,
		skne_imm, bcd, rts, ldr, str, mov, or, and, xor, add, sub,
		font, ssound, sdelay, gdelay, bogus skup/skpr, skeq, skne.
20060828	Beginning to convert the CHIP8 cpu in the CHIP8 machine to a
		(more correct) RCA 180x cpu. (Disassembly for all 1802
		instructions has been implemented, but no execution yet, and
		no 1805 extended instructions.)
20060829	Minor Alpha emulation updates.
20060830	Beginning to experiment a little with PCI IDE for SGI O2.
		Fixing the cursor key mappings for MobilePro 770 emulation.
		Fixing the LK201 warning caused by recent NetBSD/pmax.
		The MIPS R41xx standby, suspend, and hibernate instructions now
		behave like the RM52xx/MIPS32/MIPS64 wait instruction.
		Fixing dev_wdc so it calculates correct (64-bit) offsets before
		giving them to diskimage_access().
20060831	Continuing on Alpha emulation (OSF1 PALcode).
20060901	Minor Alpha updates; beginning on virtual memory pagetables.
		Removed the limit for max nr of devices (in preparation for
		allowing devices' base addresses to be changed during runtime).
		Adding a hack for MIPS [d]mfc0 select 0 (except the count
		register), so that the coproc register is simply copied.
		The MIPS suspend instruction now exits the emulator, instead
		of being treated as a wait instruction (this causes NetBSD/
		hpcmips to get correct 'halt' behavior).
		The VR41xx RTC now returns correct time.
		Connecting the VR41xx timer to the timer framework (fixed at
		128 Hz, for now).
		Continuing on SPARC emulation, adding more instructions:
		restore, ba_xcc, ble. The rectangle drawing demo works :)
		Removing the last traces of the old ENABLE_CACHE_EMULATION
		MIPS stuff (not usable with dyntrans anyway).
20060902	Splitting up src/net.c into several smaller files in its own
		subdirectory (src/net/).
20060903	Cleanup of the files in src/net/, to make them less ugly.
20060904	Continuing on the 'settings' subsystem.
		Minor progress on the SPARC emulation mode.
20060905	Cleanup of various things, and connecting the settings
		infrastructure to various subsystems (emul, machine, cpu, etc).
		Changing the lk201 mouse update routine to not rely on any
		emulated hardware framebuffer cursor coordinates, but instead
		always do (semi-usable) relative movements.
20060906	Continuing on the lk201 mouse stuff. Mouse behaviour with
		multiple framebuffers (which was working in Ultrix) is now
		semi-broken (but it still works, in a way).
		Moving the documentation about networking into its own file
		(networking.html), and refreshing it a bit. Adding an example
		of how to use ethernet frame direct-access (udp_snoop).
20060907	Continuing on the settings infrastructure.
20060908	Minor updates to SH emulation: for 32-bit emulation: delay
		slots and the 'jsr @Rn' instruction. I'm putting 64-bit SH5 on
		ice, for now.
20060909-10	Implementing some more 32-bit SH instructions. Removing the
		64-bit mode completely. Enough has now been implemented to run
		the rectangle drawing demo. :-)
20060912	Adding more SH instructions.
20060916	Continuing on SH emulation (some more instructions: div0u,
		div1, rotcl/rotcr, more mov instructions, dt, braf, sets, sett,
		tst_imm, dmuls.l, subc, ldc_rm_vbr, movt, clrt, clrs, clrmac).
		Continuing on the settings subsystem (beginning on reading/
		writing settings, removing bugs, and connecting more cpus to
		the framework).
20060919	More work on SH emulation; adding an ldc banked instruction,
		and attaching a 640x480 framebuffer to the Dreamcast machine
		mode (NetBSD/dreamcast prints the NetBSD copyright banner :-),
		and then panics).
20060920	Continuing on the settings subsystem.
20060921	Fixing the Footbridge timer stuff so that NetBSD/cats and
		NetBSD/netwinder boot up without the delays.
20060922	Temporarily hardcoding MIPS timer interrupt to 100 Hz. With
		'wait' support disabled, NetBSD/malta and Linux/malta run at
		correct speed.
20060923	Connecting dev_gt to the timer framework, so that NetBSD/cobalt
		runs at correct speed.
		Moving SH4-specific memory mapped registers into its own
		device (dev_sh4.c).
		Running with -N now prints "idling" instead of bogus nr of
		instrs/second (which isn't valid anyway) while idling.
20060924	Algor emulation should now run at correct speed.
		Adding disassembly support for some MIPS64 revision 2
		instructions: ext, dext, dextm, dextu.
20060926	The timer framework now works also when the MIPS wait
		instruction is used.
20060928	Re-implementing checks for coprocessor availability for MIPS
		cop0 instructions. (Thanks to Carl van Schaik for noticing the
		lack of cop0 availability checks.)
20060929	Implementing an instruction combination hack which treats
		NetBSD/pmax' idle loop as a wait-like instruction.
20060930	The ENTRYHI_R_MASK was missing in (at least) memory_mips_v2p.c,
		causing TLB lookups to sometimes succeed when they should have
		failed. (A big thank you to Juli Mallett for noticing the
		problem.)
		Adding disassembly support for more MIPS64 revision 2 opcodes
		(seb, seh, wsbh, jalr.hb, jr.hb, synci, ins, dins, dinsu,
		dinsm, dsbh, dshd, ror, dror, rorv, drorv, dror32). Also
		implementing seb, seh, dsbh, dshd, and wsbh.
		Implementing an instruction combination hack for Linux/pmax'
		idle loop, similar to the NetBSD/pmax case.
20061001	Changing the NetBSD/sgimips install instructions to extract
		files from an iso image, instead of downloading them via ftp.
20061002	More-than-31-bit userland addresses in memory_mips_v2p.c were
		not actually working; applying a fix from Carl van Schaik to
		enable them to work + making some other updates (adding kuseg
		support).
		Fixing hpcmips (vr41xx) timer initialization.
		Experimenting with O(n)->O(1) reduction in the MIPS TLB lookup
		loop. Seems to work both for R3000 and non-R3000.
20061003	Continuing a little on SH emulation (adding more control
		registers; mini-cleanup of memory_sh.c).
20061004	Beginning on a dev_rtc, a clock/timer device for the test
		machines; also adding a demo, and some documentation.
		Fixing a bug in SH "mov.w @(disp,pc),Rn" (the result wasn't
		sign-extended), and adding the addc and ldtlb instructions.
20061005	Contining on SH emulation: virtual to physical address
		translation, and a skeleton exception mechanism.
20061006	Adding more SH instructions (various loads and stores, rte,
		negc, muls.w, various privileged register-move instructions).
20061007	More SH instructions: various move instructions, trapa, div0s,
		float, fdiv, ftrc.
		Continuing on dev_rtc; removing the rtc demo.
20061008	Adding a dummy Dreamcast PROM module. (Homebrew Dreamcast
		programs using KOS libs need this.)
		Adding more SH instructions: "stc vbr,rn", rotl, rotr, fsca,
		fmul, fadd, various floating-point moves, etc. A 256-byte
		demo for Dreamcast runs :-)
20061012	Adding the SH "lds Rm,pr" and bsr instructions.
20061013	More SH instructions: "sts fpscr,rn", tas.b, and some more
		floating point instructions, cmp/str, and more moves.
		Adding a dummy dev_pvr (Dreamcast graphics controller).
20061014	Generalizing the expression evaluator (used in the built-in
		debugger) to support parentheses and +-*/%^&|.
20061015	Removing the experimental tlb index hint code in
		mips_memory_v2p.c, since it didn't really have any effect.
20061017	Minor SH updates; adding the "sts pr,Rn", fcmp/gt, fneg,
		frchg, and some other instructions. Fixing missing sign-
		extension in an 8-bit load instruction.
20061019	Adding a simple dev_dreamcast_rtc.
		Implementing memory-mapped access to the SH ITLB/UTLB arrays.
20061021	Continuing on various SH and Dreamcast things: sh4 timers,
		debug messages for dev_pvr, fixing some virtual address
		translation bugs, adding the bsrf instruction.
		The NetBSD/dreamcast GENERIC_MD kernel now reaches userland :)
		Adding a dummy dev_dreamcast_asic.c (not really useful yet).
		Implementing simple support for Store Queues.
		Beginning on the PVR Tile Accelerator.
20061022	Generalizing the PVR framebuffer to support off-screen drawing,
		multiple bit-depths, etc. (A small speed penalty, but most
		likely worth it.)
		Adding more SH instructions (mulu.w, fcmp/eq, fsub, fmac,
		fschg, and some more); correcting bugs in "fsca" and "float".
20061024	Adding the SH ftrv (matrix * vector) instruction. Marcus
		Comstedt's "tatest" example runs :) (wireframe only).
		Correcting disassembly for SH floating point instructions that
		use the xd* registers.
		Adding the SH fsts instruction.
		In memory_device_dyntrans_access(), only the currently used
		range is now invalidated, and not the entire device range.
20061025	Adding a dummy AVR32 cpu mode skeleton.
20061026	Various Dreamcast updates; beginning on a Maple bus controller.
20061027	Continuing on the Maple bus. A bogus Controller, Keyboard, and
		Mouse can now be detected by NetBSD and KOS homebrew programs.
		Cleaning up the SH4 Timer Management Unit, and beginning on
		SH4 interrupts.
		Implementing the Dreamcast SYSASIC.
20061028	Continuing on the SYSASIC.
		Adding the SH fsqrt instruction.
		memory_sh.c now actually scans the ITLB.
		Fixing a bug in dev_sh4.c, related to associative writes into
		the memory-mapped UTLB array. NetBSD/dreamcast now reaches
		userland stably, and prints the "Terminal type?" message :-]
		Implementing enough of the Dreamcast keyboard to make NetBSD
		accept it for input.
		Enabling SuperH for stable (non-development) builds.
		Adding NetBSD/dreamcast to the documentation, although it
		doesn't support root-on-nfs yet.
20061029	Changing usleep(1) calls in the debugger to to usleep(10000)
		(according to Brian Foley, this makes GXemul run better on
		MacOS X).
		Making the Maple "Controller" do something (enough to barely
		interact with dcircus.elf).
20061030-31	Some progress on the PVR. More test programs start running (but
		with strange output).
		Various other SH4-related updates.
20061102	Various Dreamcast and SH4 updates; more KOS demos run now.
20061104	Adding a skeleton dev_mb8696x.c (the Dreamcast's LAN adapter).
20061105	Continuing on the MB8696x; NetBSD/dreamcast detects it as mbe0.
		Testing for the release.

==============  RELEASE 0.4.3  ==============


1 /*
2 * Copyright (C) 2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_lca.c,v 1.4 2006/08/29 15:55:10 debug Exp $
29 *
30 * LCA PCI bus (for Alpha machines).
31 */
32
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <string.h>
36
37 #include "bus_isa.h"
38 #include "bus_pci.h"
39 #include "cpu.h"
40 #include "device.h"
41 #include "emul.h"
42 #include "machine.h"
43 #include "memory.h"
44 #include "misc.h"
45
46
47 #include "alpha_lcareg.h"
48
49 #define LCA_ISA_BASE (LCA_PCI_SIO + 0x10000000)
50 #define LCA_ISA_MEMBASE (LCA_PCI_SIO + 0x18000000)
51
52
53 struct lca_data {
54 struct pci_data *pci_data;
55
56 uint64_t ioc_conf;
57 uint64_t tlb_enable;
58 uint64_t window_base_0;
59 uint64_t window_mask_0;
60 uint64_t window_t_base_0;
61 uint64_t window_base_1;
62 uint64_t window_mask_1;
63 uint64_t window_t_base_1;
64 };
65
66
67 DEVICE_ACCESS(lca_pci_conf)
68 {
69 uint64_t idata = 0, odata = 0;
70 int tag, bus, dev, func, reg;
71 struct lca_data *d = extra;
72
73 if (writeflag == MEM_WRITE)
74 idata = memory_readmax64(cpu, data, len);
75
76 /*
77 * 1. Decompose the address into a tag.
78 *
79 * According to NetBSD's lca_pci.c, the address is composed like this:
80 *
81 * addr = tag << 5 | (regoffset & ~0x03) << 5 | 0x3 << 3
82 */
83 reg = (relative_addr >> 5) & 0xfc;
84 tag = (relative_addr >> 5) & ~0xff;
85
86 /*
87 * 2. Decompose the tag into bus, dev, and func.
88 *
89 * The tag can be constructed in one of two ways. On the primary
90 * bus (nr 0):
91 *
92 * tag = (1 << (device + 11)) | (function << 8);
93 *
94 * and on other busses, the tag is a normal:
95 *
96 * tag = (bus << 16) | (device << 11) | (function << 8)
97 */
98 /* printf("tag = 0x%x\n", (int)tag); */
99 bus = d->ioc_conf & 1;
100
101 if (bus == 0) {
102 for (dev=0; dev<21; dev++)
103 if (tag & (0x800 << dev))
104 break;
105 if (dev >= 21) {
106 /* fatal("[ LCA: No bus 0 device? TODO ]\n");
107 exit(1); */
108 dev = 0;
109 }
110 } else {
111 fatal("TODO. Non-zero bus.\n");
112 exit(1);
113 }
114
115 func = (tag >> 8) & 7;
116 /* printf("bus=%i dev=%i func=%i reg=%i\n", bus,dev,func,reg); */
117
118 /* Pass PCI accesses onto bus_pci: */
119 bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
120 bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
121 &odata : &idata, len, writeflag);
122
123 if (writeflag == MEM_READ)
124 memory_writemax64(cpu, data, len, odata);
125
126 return 1;
127 }
128
129
130 DEVICE_ACCESS(lca_isa)
131 {
132 int ofs, i;
133 uint8_t byte;
134
135 relative_addr >>= 5;
136
137 ofs = relative_addr & 3;
138 if (ofs > len) {
139 fatal("[ ofs=%i len=%i in lca_isa access function. "
140 "aborting ]\n", ofs, len);
141 exit(1);
142 }
143
144 if (writeflag == MEM_WRITE) {
145 byte = data[ofs % len];
146 return cpu->memory_rw(cpu, cpu->mem, LCA_ISA_BASE +
147 relative_addr, &byte, 1, writeflag, CACHE_NONE);
148 }
149
150 cpu->memory_rw(cpu, cpu->mem, LCA_ISA_BASE + relative_addr,
151 &byte, 1, MEM_READ, CACHE_NONE);
152
153 for (i=0; i<len; i++)
154 data[i] = i == ofs? byte : 0x00;
155
156 return 1;
157 }
158
159
160 DEVICE_ACCESS(lca_ioc)
161 {
162 uint64_t idata = 0, odata = 0;
163 struct lca_data *d = extra;
164
165 if (writeflag == MEM_WRITE)
166 idata = memory_readmax64(cpu, data, len);
167
168 switch (relative_addr + LCA_IOC_BASE) {
169
170 case LCA_IOC_BASE:
171 /* Ignore? Linux reads from the base at startup. */
172 break;
173
174 case LCA_IOC_CONF:
175 if (writeflag == MEM_READ) {
176 odata = d->ioc_conf;
177 } else {
178 d->ioc_conf = idata;
179 /* Only bit 0 is implemented so far, the PCI bus 0 vs
180 bus non-0 selection bit. */
181 if (idata & ~1) {
182 fatal("TODO: Write to unimplemented bit of"
183 " IOC_CONF: 0x%x\n", (int)idata);
184 exit(1);
185 }
186 }
187 break;
188
189 case LCA_IOC_TBIA:
190 /* TLB Invalidate All. */
191 /* TODO: For now, let's just ignore it. */
192 break;
193
194 case LCA_IOC_TB_ENA:
195 if (writeflag == MEM_READ) {
196 odata = d->tlb_enable;
197 } else {
198 d->tlb_enable = idata;
199 /* TODO: Actually implement this. */
200 if (idata & ~IOC_TB_ENA_TEN) {
201 fatal("TODO: LCA_IOC_TB_ENA value "
202 " (0x%"PRIx64") has unimplemented "
203 "bits.\n", (uint64_t)idata);
204 exit(1);
205 }
206 }
207 break;
208
209 case LCA_IOC_W_BASE0:
210 if (writeflag == MEM_READ) {
211 odata = d->window_base_0;
212 } else {
213 d->window_base_0 = idata;
214 /* TODO: Actually implement this. */
215 if (idata != 0ULL && idata != 0x300800000ULL) {
216 fatal("TODO: LCA_IOC_W_BASE0 value differs"
217 " (0x%"PRIx64") from the only implemented"
218 " values\n", (uint64_t)idata);
219 exit(1);
220 }
221 }
222 break;
223
224 case LCA_IOC_W_MASK0:
225 if (writeflag == MEM_READ) {
226 odata = d->window_mask_0;
227 } else {
228 d->window_mask_0 = idata;
229 /* TODO: Actually implement this. */
230 if (idata != 0x700000ULL) {
231 fatal("TODO: LCA_IOC_W_MASK0 value differs"
232 " (0x%"PRIx64") from the only implemented"
233 " value\n", (uint64_t)idata);
234 exit(1);
235 }
236 }
237 break;
238
239 case LCA_IOC_W_T_BASE0:
240 if (writeflag == MEM_READ) {
241 odata = d->window_t_base_0;
242 } else {
243 d->window_t_base_0 = idata;
244 /* TODO: Actually implement this. */
245 }
246 break;
247
248 case LCA_IOC_W_BASE1:
249 if (writeflag == MEM_READ) {
250 odata = d->window_base_1;
251 } else {
252 d->window_base_1 = idata;
253 /* TODO: Actually implement this. */
254 if (idata != 0x240000000ULL) {
255 fatal("TODO: LCA_IOC_W_BASE1 value differs"
256 " (0x%"PRIx64") from the only implemented"
257 " value\n", (uint64_t)idata);
258 exit(1);
259 }
260 }
261 break;
262
263 case LCA_IOC_W_MASK1:
264 if (writeflag == MEM_READ) {
265 odata = d->window_mask_1;
266 } else {
267 d->window_mask_1 = idata;
268 /* TODO: Actually implement this. */
269 if (idata != 0x3ff00000ULL) {
270 fatal("TODO: LCA_IOC_W_MASK1 value differs"
271 " (0x%"PRIx64") from the only implemented"
272 " value\n", (uint64_t)idata);
273 exit(1);
274 }
275 }
276 break;
277
278 case LCA_IOC_W_T_BASE1:
279 if (writeflag == MEM_READ) {
280 odata = d->window_t_base_1;
281 } else {
282 d->window_t_base_1 = idata;
283 /* TODO: Actually implement this. */
284 }
285 break;
286
287 default:fatal("[ lca_ioc: unimplemented %s to offset 0x%x",
288 writeflag == MEM_WRITE? "write" : "read", (int)
289 relative_addr);
290 if (writeflag == MEM_WRITE)
291 fatal(": 0x%x", (int)idata);
292 fatal(" ]\n");
293 exit(1);
294 }
295
296 if (writeflag == MEM_READ)
297 memory_writemax64(cpu, data, len, odata);
298
299 return 1;
300 }
301
302
303 DEVINIT(lca)
304 {
305 struct lca_data *d = malloc(sizeof(struct lca_data));
306 if (d == NULL) {
307 fprintf(stderr, "out of memory\n");
308 exit(1);
309 }
310 memset(d, 0, sizeof(struct lca_data));
311
312 /* Register a PCI bus: */
313 d->pci_data = bus_pci_init(
314 devinit->machine,
315 0 /* pciirq: TODO */,
316 LCA_PCI_SIO, /* pci device io offset */
317 0x00000000, /* pci device mem offset: TODO */
318 0x00000000, /* PCI portbase: TODO */
319 0x00000000, /* PCI membase: TODO */
320 0x00000000, /* PCI irqbase: TODO */
321 LCA_ISA_BASE, /* ISA portbase */
322 LCA_ISA_MEMBASE, /* ISA membase */
323 8); /* ISA irqbase: TODO */
324
325 /* Add the "sio0" controller (as seen by NetBSD): */
326 bus_pci_add(devinit->machine, d->pci_data, devinit->machine->memory,
327 0, 7, 0, "i82378zb");
328
329 memory_device_register(devinit->machine->memory, "lca_pci_conf",
330 LCA_PCI_CONF, 0x20000000, dev_lca_pci_conf_access, (void *)d,
331 DM_DEFAULT, NULL);
332
333 memory_device_register(devinit->machine->memory, "lca_isa",
334 LCA_PCI_SIO, 0x10000 << 5, dev_lca_isa_access, (void *)d,
335 DM_DEFAULT, NULL);
336
337 memory_device_register(devinit->machine->memory, "lca_ioc",
338 LCA_IOC_BASE, 0x20000000, dev_lca_ioc_access, (void *)d,
339 DM_DEFAULT, NULL);
340
341 /* TODO: IRQs etc. */
342 bus_isa_init(devinit->machine, BUS_ISA_IDE0 | BUS_ISA_IDE1,
343 LCA_ISA_BASE, LCA_ISA_MEMBASE, 32, 48);
344
345 return 1;
346 }
347

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