/[gxemul]/trunk/src/devices/dev_lca.c
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Contents of /trunk/src/devices/dev_lca.c

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Revision 42 - (show annotations)
Mon Oct 8 16:22:32 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 9928 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1613 2007/06/15 20:11:26 debug Exp $
20070501	Continuing a little on m88k disassembly (control registers,
		more instructions).
		Adding a dummy mvme88k machine mode.
20070502	Re-adding MIPS load/store alignment exceptions.
20070503	Implementing more of the M88K disassembly code.
20070504	Adding disassembly of some more M88K load/store instructions.
		Implementing some relatively simple M88K instructions (br.n,
		xor[.u] imm, and[.u] imm).
20070505	Implementing M88K three-register and, or, xor, and jmp[.n],
		bsr[.n] including function call trace stuff.
		Applying a patch from Bruce M. Simpson which implements the
		SYSCON_BOARD_CPU_CLOCK_FREQ_ID object of the syscon call in
		the yamon PROM emulation.
20070506	Implementing M88K bb0[.n] and bb1[.n], and skeletons for
		ldcr and stcr (although no control regs are implemented yet).
20070509	Found and fixed the bug which caused Linux for QEMU_MIPS to
		stop working in 0.4.5.1: It was a faulty change to the MIPS
		'sc' and 'scd' instructions I made while going through gcc -W
		warnings on 20070428.
20070510	Updating the Linux/QEMU_MIPS section in guestoses.html to
		use mips-test-0.2.tar.gz instead of 0.1.
		A big thank you to Miod Vallat for sending me M88K manuals.
		Implementing more M88K instructions (addu, subu, div[u], mulu,
		ext[u], clr, set, cmp).
20070511	Fixing bugs in the M88K "and" and "and.u" instructions (found
		by comparing against the manual).
		Implementing more M88K instructions (mask[.u], mak, bcnd (auto-
		generated)) and some more control register details.
		Cleanup: Removing the experimental AVR emulation mode and
		corresponding devices; AVR emulation wasn't really meaningful.
		Implementing autogeneration of most M88K loads/stores. The
		rectangle drawing demo (with -O0) for M88K runs :-)
		Beginning on M88K exception handling.
		More M88K instructions: tb0, tb1, rte, sub, jsr[.n].
		Adding some skeleton MVME PROM ("BUG") emulation.
20070512	Fixing a bug in the M88K cmp instruction.
		Adding the M88K lda (scaled register) instruction.
		Fixing bugs in 64-bit (32-bit pairs) M88K loads/stores.
		Removing the unused tick_hz stuff from the machine struct.
		Implementing the M88K xmem instruction. OpenBSD/mvme88k gets
		far enough to display the Copyright banner :-)
		Implementing subu.co (guess), addu.co, addu.ci, ff0, and ff1.
		Adding a dev_mvme187, for MVME187-specific devices/registers.
		OpenBSD/mvme88k prints more boot messages. :)
20070515	Continuing on MVME187 emulation (adding more devices, beginning
		on the CMMUs, etc).
		Adding the M88K and.c, xor.c, and or.c instructions, and making
		sure that mul, div, etc cause exceptions if executed when SFD1
		is disabled.
20070517	Continuing on M88K and MVME187 emulation in general; moving
		the CMMU registers to the CPU struct, separating dev_pcc2 from
		dev_mvme187, and beginning on memory_m88k.c (BATC and PATC).
		Fixing a bug in 64-bit (32-bit pairs) M88K fast stores.
		Implementing the clock part of dev_mk48txx.
		Implementing the M88K fstcr and xcr instructions.
		Implementing m88k_cpu_tlbdump().
		Beginning on the implementation of a separate address space
		for M88K .usr loads/stores.
20070520	Removing the non-working (skeleton) Sandpoint, SonyNEWS, SHARK
		Dnard, and Zaurus machine modes.
		Experimenting with dyntrans to_be_translated read-ahead. It
		seems to give a very small performance increase for MIPS
		emulation, but a large performance degradation for SuperH. Hm.
20070522	Disabling correct SuperH ITLB emulation; it does not seem to be
		necessary in order to let SH4 guest OSes run, and it slows down
		userspace code.
		Implementing "samepage" branches for SuperH emulation, and some
		other minor speed hacks.
20070525	Continuing on M88K memory-related stuff: exceptions, memory
		transaction register contents, etc.
		Implementing the M88K subu.ci instruction.
		Removing the non-working (skeleton) Iyonix machine mode.
		OpenBSD/mvme88k reaches userland :-), starts executing
		/sbin/init's instructions, and issues a few syscalls, before
		crashing.
20070526	Fixing bugs in dev_mk48txx, so that OpenBSD/mvme88k detects
		the correct time-of-day.
		Implementing a generic IRQ controller for the test machines
		(dev_irqc), similar to a proposed patch from Petr Stepan.
		Experimenting some more with translation read-ahead.
		Adding an "expect" script for automated OpenBSD/landisk
		install regression/performance tests.
20070527	Adding a dummy mmEye (SH3) machine mode skeleton.
		FINALLY found the strange M88K bug I have been hunting: I had
		not emulated the SNIP value for exceptions occurring in
		branch delay slots correctly.
		Implementing correct exceptions for 64-bit M88K loads/stores.
		Address to symbol lookups are now disabled when M88K is
		running in usermode (because usermode addresses don't have
		anything to do with supervisor addresses).
20070531	Removing the mmEye machine mode skeleton.
20070604	Some minor code cleanup.
20070605	Moving src/useremul.c into a subdir (src/useremul/), and
		cleaning up some more legacy constructs.
		Adding -Wstrict-aliasing and -fstrict-aliasing detection to
		the configure script.
20070606	Adding a check for broken GCC on Solaris to the configure
		script. (GCC 3.4.3 on Solaris cannot handle static variables
		which are initialized to 0 or NULL. :-/)
		Removing the old (non-working) ARC emulation modes: NEC RD94,
		R94, R96, and R98, and the last traces of Olivetti M700 and
		Deskstation Tyne.
		Removing the non-working skeleton WDSC device (dev_wdsc).
20070607	Thinking about how to use the host's cc + ld at runtime to
		generate native code. (See experiments/native_cc_ld_test.i
		for an example.)
20070608	Adding a program counter sampling timer, which could be useful
		for native code generation experiments.
		The KN02_CSR_NRMMOD bit in the DECstation 5000/200 (KN02) CSR
		should always be set, to allow a 5000/200 PROM to boot.
20070609	Moving out breakpoint details from the machine struct into
		a helper struct, and removing the limit on max nr of
		breakpoints.
20070610	Moving out tick functions into a helper struct as well (which
		also gets rid of the max limit).
20070612	FINALLY figured out why Debian/DECstation stopped working when
		translation read-ahead was enabled: in src/memory_rw.c, the
		call to invalidate_code_translation was made also if the
		memory access was an instruction load (if the page was mapped
		as writable); it shouldn't be called in that case.
20070613	Implementing some more MIPS32/64 revision 2 instructions: di,
		ei, ext, dext, dextm, dextu, and ins.
20070614	Implementing an instruction combination for the NetBSD/arm
		idle loop (making the host not use any cpu if NetBSD/arm
		inside the emulator is not using any cpu).
		Increasing the nr of ARM VPH entries from 128 to 384.
20070615	Removing the ENABLE_arch stuff from the configure script, so
		that all included architectures are included in both release
		and development builds.
		Moving memory related helper functions from misc.c to memory.c.
		Adding preliminary instructions for netbooting NetBSD/pmppc to
		guestoses.html; it doesn't work yet, there are weird timeouts.
		Beginning a total rewrite of the userland emulation modes
		(removing all emulation modes, beginning from scratch with
		NetBSD/MIPS and FreeBSD/Alpha only).
20070616	After fixing a bug in the DEC21143 NIC (the TDSTAT_OWN bit was
		only cleared for the last segment when transmitting, not all
		segments), NetBSD/pmppc boots with root-on-nfs without the
		timeouts. Updating guestoses.html.
		Removing the skeleton PSP (Playstation Portable) mode.
		Moving X11-related stuff in the machine struct into a helper
		struct.
		Cleanup of out-of-memory checks, to use a new CHECK_ALLOCATION
		macro (which prints a meaningful error message).
		Adding a COMMENT to each machine and device (for automagic
		.index comment generation).
		Doing regression testing for the next release.

==============  RELEASE 0.4.6  ==============
1 /*
2 * Copyright (C) 2006-2007 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_lca.c,v 1.10 2007/06/15 19:11:15 debug Exp $
29 *
30 * COMMENT: LCA PCI bus, for Alpha machines
31 */
32
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <string.h>
36
37 #include "bus_isa.h"
38 #include "bus_pci.h"
39 #include "cpu.h"
40 #include "device.h"
41 #include "emul.h"
42 #include "interrupt.h"
43 #include "machine.h"
44 #include "memory.h"
45 #include "misc.h"
46
47
48 #include "alpha_lcareg.h"
49
50 #define LCA_ISA_BASE (LCA_PCI_SIO + 0x10000000)
51 #define LCA_ISA_MEMBASE (LCA_PCI_SIO + 0x18000000)
52
53
54 struct lca_data {
55 struct pci_data *pci_data;
56
57 uint64_t ioc_conf;
58 uint64_t tlb_enable;
59 uint64_t window_base_0;
60 uint64_t window_mask_0;
61 uint64_t window_t_base_0;
62 uint64_t window_base_1;
63 uint64_t window_mask_1;
64 uint64_t window_t_base_1;
65 };
66
67
68 /*
69 * lca_interrupt_assert():
70 *
71 * Line 0 = ISA interrupt.
72 */
73 void lca_interrupt_assert(struct interrupt *interrupt)
74 {
75 fatal("lca_interrupt_assert: TODO\n");
76 exit(1);
77 }
78
79
80 /*
81 * lca_interrupt_deassert():
82 *
83 * Line 0 = ISA interrupt.
84 */
85 void lca_interrupt_deassert(struct interrupt *interrupt)
86 {
87 fatal("lca_interrupt_deassert: TODO\n");
88 exit(1);
89 }
90
91
92 DEVICE_ACCESS(lca_pci_conf)
93 {
94 uint64_t idata = 0, odata = 0;
95 int tag, bus, dev, func, reg;
96 struct lca_data *d = extra;
97
98 if (writeflag == MEM_WRITE)
99 idata = memory_readmax64(cpu, data, len);
100
101 /*
102 * 1. Decompose the address into a tag.
103 *
104 * According to NetBSD's lca_pci.c, the address is composed like this:
105 *
106 * addr = tag << 5 | (regoffset & ~0x03) << 5 | 0x3 << 3
107 */
108 reg = (relative_addr >> 5) & 0xfc;
109 tag = (relative_addr >> 5) & ~0xff;
110
111 /*
112 * 2. Decompose the tag into bus, dev, and func.
113 *
114 * The tag can be constructed in one of two ways. On the primary
115 * bus (nr 0):
116 *
117 * tag = (1 << (device + 11)) | (function << 8);
118 *
119 * and on other busses, the tag is a normal:
120 *
121 * tag = (bus << 16) | (device << 11) | (function << 8)
122 */
123 /* printf("tag = 0x%x\n", (int)tag); */
124 bus = d->ioc_conf & 1;
125
126 if (bus == 0) {
127 for (dev=0; dev<21; dev++)
128 if (tag & (0x800 << dev))
129 break;
130 if (dev >= 21) {
131 /* fatal("[ LCA: No bus 0 device? TODO ]\n");
132 exit(1); */
133 dev = 0;
134 }
135 } else {
136 fatal("TODO. Non-zero bus.\n");
137 exit(1);
138 }
139
140 func = (tag >> 8) & 7;
141 /* printf("bus=%i dev=%i func=%i reg=%i\n", bus,dev,func,reg); */
142
143 /* Pass PCI accesses onto bus_pci: */
144 bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
145 bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
146 &odata : &idata, len, writeflag);
147
148 if (writeflag == MEM_READ)
149 memory_writemax64(cpu, data, len, odata);
150
151 return 1;
152 }
153
154
155 DEVICE_ACCESS(lca_isa)
156 {
157 unsigned int ofs, i;
158 uint8_t byte;
159
160 relative_addr >>= 5;
161
162 ofs = relative_addr & 3;
163 if (ofs > len) {
164 fatal("[ ofs=%i len=%i in lca_isa access function. "
165 "aborting ]\n", ofs, len);
166 exit(1);
167 }
168
169 if (writeflag == MEM_WRITE) {
170 byte = data[ofs % len];
171 return cpu->memory_rw(cpu, cpu->mem, LCA_ISA_BASE +
172 relative_addr, &byte, 1, writeflag, CACHE_NONE);
173 }
174
175 cpu->memory_rw(cpu, cpu->mem, LCA_ISA_BASE + relative_addr,
176 &byte, 1, MEM_READ, CACHE_NONE);
177
178 for (i=0; i<len; i++)
179 data[i] = i == ofs? byte : 0x00;
180
181 return 1;
182 }
183
184
185 DEVICE_ACCESS(lca_ioc)
186 {
187 uint64_t idata = 0, odata = 0;
188 struct lca_data *d = extra;
189
190 if (writeflag == MEM_WRITE)
191 idata = memory_readmax64(cpu, data, len);
192
193 switch (relative_addr + LCA_IOC_BASE) {
194
195 case LCA_IOC_BASE:
196 /* Ignore? Linux reads from the base at startup. */
197 break;
198
199 case LCA_IOC_CONF:
200 if (writeflag == MEM_READ) {
201 odata = d->ioc_conf;
202 } else {
203 d->ioc_conf = idata;
204 /* Only bit 0 is implemented so far, the PCI bus 0 vs
205 bus non-0 selection bit. */
206 if (idata & ~1) {
207 fatal("TODO: Write to unimplemented bit of"
208 " IOC_CONF: 0x%x\n", (int)idata);
209 exit(1);
210 }
211 }
212 break;
213
214 case LCA_IOC_TBIA:
215 /* TLB Invalidate All. */
216 /* TODO: For now, let's just ignore it. */
217 break;
218
219 case LCA_IOC_TB_ENA:
220 if (writeflag == MEM_READ) {
221 odata = d->tlb_enable;
222 } else {
223 d->tlb_enable = idata;
224 /* TODO: Actually implement this. */
225 if (idata & ~IOC_TB_ENA_TEN) {
226 fatal("TODO: LCA_IOC_TB_ENA value "
227 " (0x%"PRIx64") has unimplemented "
228 "bits.\n", (uint64_t)idata);
229 exit(1);
230 }
231 }
232 break;
233
234 case LCA_IOC_W_BASE0:
235 if (writeflag == MEM_READ) {
236 odata = d->window_base_0;
237 } else {
238 d->window_base_0 = idata;
239 /* TODO: Actually implement this. */
240 if (idata != 0ULL && idata != 0x300800000ULL) {
241 fatal("TODO: LCA_IOC_W_BASE0 value differs"
242 " (0x%"PRIx64") from the only implemented"
243 " values\n", (uint64_t)idata);
244 exit(1);
245 }
246 }
247 break;
248
249 case LCA_IOC_W_MASK0:
250 if (writeflag == MEM_READ) {
251 odata = d->window_mask_0;
252 } else {
253 d->window_mask_0 = idata;
254 /* TODO: Actually implement this. */
255 if (idata != 0x700000ULL) {
256 fatal("TODO: LCA_IOC_W_MASK0 value differs"
257 " (0x%"PRIx64") from the only implemented"
258 " value\n", (uint64_t)idata);
259 exit(1);
260 }
261 }
262 break;
263
264 case LCA_IOC_W_T_BASE0:
265 if (writeflag == MEM_READ) {
266 odata = d->window_t_base_0;
267 } else {
268 d->window_t_base_0 = idata;
269 /* TODO: Actually implement this. */
270 }
271 break;
272
273 case LCA_IOC_W_BASE1:
274 if (writeflag == MEM_READ) {
275 odata = d->window_base_1;
276 } else {
277 d->window_base_1 = idata;
278 /* TODO: Actually implement this. */
279 if (idata != 0x240000000ULL) {
280 fatal("TODO: LCA_IOC_W_BASE1 value differs"
281 " (0x%"PRIx64") from the only implemented"
282 " value\n", (uint64_t)idata);
283 exit(1);
284 }
285 }
286 break;
287
288 case LCA_IOC_W_MASK1:
289 if (writeflag == MEM_READ) {
290 odata = d->window_mask_1;
291 } else {
292 d->window_mask_1 = idata;
293 /* TODO: Actually implement this. */
294 if (idata != 0x3ff00000ULL) {
295 fatal("TODO: LCA_IOC_W_MASK1 value differs"
296 " (0x%"PRIx64") from the only implemented"
297 " value\n", (uint64_t)idata);
298 exit(1);
299 }
300 }
301 break;
302
303 case LCA_IOC_W_T_BASE1:
304 if (writeflag == MEM_READ) {
305 odata = d->window_t_base_1;
306 } else {
307 d->window_t_base_1 = idata;
308 /* TODO: Actually implement this. */
309 }
310 break;
311
312 default:fatal("[ lca_ioc: unimplemented %s to offset 0x%x",
313 writeflag == MEM_WRITE? "write" : "read", (int)
314 relative_addr);
315 if (writeflag == MEM_WRITE)
316 fatal(": 0x%x", (int)idata);
317 fatal(" ]\n");
318 exit(1);
319 }
320
321 if (writeflag == MEM_READ)
322 memory_writemax64(cpu, data, len, odata);
323
324 return 1;
325 }
326
327
328 DEVINIT(lca)
329 {
330 char *interrupt_path;
331 struct interrupt interrupt_template;
332 struct lca_data *d;
333
334 CHECK_ALLOCATION(d = malloc(sizeof(struct lca_data)));
335 memset(d, 0, sizeof(struct lca_data));
336
337 /* Register a PCI bus: */
338 d->pci_data = bus_pci_init(
339 devinit->machine,
340 "TODO: irq" /* pciirq: TODO */,
341 LCA_PCI_SIO, /* pci device io offset */
342 0x00000000, /* pci device mem offset: TODO */
343 0x00000000, /* PCI portbase: TODO */
344 0x00000000, /* PCI membase: TODO */
345 "TODO: pci irq base", /* PCI irqbase: TODO */
346 LCA_ISA_BASE, /* ISA portbase */
347 LCA_ISA_MEMBASE, /* ISA membase */
348 "TODO: irqbase isa"); /* ISA irqbase: TODO */
349
350 /* Add the "sio0" controller (as seen by NetBSD): */
351 bus_pci_add(devinit->machine, d->pci_data, devinit->machine->memory,
352 0, 7, 0, "i82378zb");
353
354 memory_device_register(devinit->machine->memory, "lca_pci_conf",
355 LCA_PCI_CONF, 0x20000000, dev_lca_pci_conf_access, (void *)d,
356 DM_DEFAULT, NULL);
357
358 memory_device_register(devinit->machine->memory, "lca_isa",
359 LCA_PCI_SIO, 0x10000 << 5, dev_lca_isa_access, (void *)d,
360 DM_DEFAULT, NULL);
361
362 memory_device_register(devinit->machine->memory, "lca_ioc",
363 LCA_IOC_BASE, 0x20000000, dev_lca_ioc_access, (void *)d,
364 DM_DEFAULT, NULL);
365
366 CHECK_ALLOCATION(interrupt_path =
367 malloc(strlen(devinit->machine->path) + 10));
368 snprintf(interrupt_path, strlen(devinit->machine->path) + 10,
369 "%s.lca", devinit->machine->path);
370
371 memset(&interrupt_template, 0, sizeof(interrupt_template));
372 interrupt_template.line = 0;
373 interrupt_template.name = interrupt_path;
374 interrupt_template.extra = d;
375 interrupt_template.interrupt_assert = lca_interrupt_assert;
376 interrupt_template.interrupt_deassert = lca_interrupt_deassert;
377 interrupt_handler_register(&interrupt_template);
378
379 bus_isa_init(devinit->machine, interrupt_path,
380 BUS_ISA_IDE0 | BUS_ISA_IDE1, LCA_ISA_BASE, LCA_ISA_MEMBASE);
381
382 return 1;
383 }
384
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