/[gxemul]/trunk/src/devices/dev_lca.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Revision 34 - (hide annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 6 months ago) by dpavlin
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File size: 9935 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============
1 dpavlin 24 /*
2 dpavlin 34 * Copyright (C) 2006-2007 Anders Gavare. All rights reserved.
3 dpavlin 24 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 34 * $Id: dev_lca.c,v 1.8 2006/12/30 13:30:58 debug Exp $
29 dpavlin 24 *
30 dpavlin 32 * LCA PCI bus (for Alpha machines).
31 dpavlin 24 */
32    
33     #include <stdio.h>
34     #include <stdlib.h>
35     #include <string.h>
36    
37     #include "bus_isa.h"
38 dpavlin 32 #include "bus_pci.h"
39 dpavlin 24 #include "cpu.h"
40     #include "device.h"
41     #include "emul.h"
42 dpavlin 34 #include "interrupt.h"
43 dpavlin 24 #include "machine.h"
44     #include "memory.h"
45     #include "misc.h"
46    
47    
48     #include "alpha_lcareg.h"
49    
50     #define LCA_ISA_BASE (LCA_PCI_SIO + 0x10000000)
51     #define LCA_ISA_MEMBASE (LCA_PCI_SIO + 0x18000000)
52    
53    
54     struct lca_data {
55 dpavlin 32 struct pci_data *pci_data;
56    
57     uint64_t ioc_conf;
58     uint64_t tlb_enable;
59     uint64_t window_base_0;
60     uint64_t window_mask_0;
61     uint64_t window_t_base_0;
62     uint64_t window_base_1;
63     uint64_t window_mask_1;
64     uint64_t window_t_base_1;
65 dpavlin 24 };
66    
67    
68 dpavlin 34 /*
69     * lca_interrupt_assert():
70     *
71     * Line 0 = ISA interrupt.
72     */
73     void lca_interrupt_assert(struct interrupt *interrupt)
74     {
75     fatal("lca_interrupt_assert: TODO\n");
76     exit(1);
77     }
78    
79    
80     /*
81     * lca_interrupt_deassert():
82     *
83     * Line 0 = ISA interrupt.
84     */
85     void lca_interrupt_deassert(struct interrupt *interrupt)
86     {
87     fatal("lca_interrupt_deassert: TODO\n");
88     exit(1);
89     }
90    
91    
92 dpavlin 32 DEVICE_ACCESS(lca_pci_conf)
93     {
94     uint64_t idata = 0, odata = 0;
95     int tag, bus, dev, func, reg;
96     struct lca_data *d = extra;
97    
98     if (writeflag == MEM_WRITE)
99     idata = memory_readmax64(cpu, data, len);
100    
101     /*
102     * 1. Decompose the address into a tag.
103     *
104     * According to NetBSD's lca_pci.c, the address is composed like this:
105     *
106     * addr = tag << 5 | (regoffset & ~0x03) << 5 | 0x3 << 3
107     */
108     reg = (relative_addr >> 5) & 0xfc;
109     tag = (relative_addr >> 5) & ~0xff;
110    
111     /*
112     * 2. Decompose the tag into bus, dev, and func.
113     *
114     * The tag can be constructed in one of two ways. On the primary
115     * bus (nr 0):
116     *
117     * tag = (1 << (device + 11)) | (function << 8);
118     *
119     * and on other busses, the tag is a normal:
120     *
121     * tag = (bus << 16) | (device << 11) | (function << 8)
122     */
123     /* printf("tag = 0x%x\n", (int)tag); */
124     bus = d->ioc_conf & 1;
125    
126     if (bus == 0) {
127     for (dev=0; dev<21; dev++)
128     if (tag & (0x800 << dev))
129     break;
130     if (dev >= 21) {
131     /* fatal("[ LCA: No bus 0 device? TODO ]\n");
132     exit(1); */
133     dev = 0;
134     }
135     } else {
136     fatal("TODO. Non-zero bus.\n");
137     exit(1);
138     }
139    
140     func = (tag >> 8) & 7;
141     /* printf("bus=%i dev=%i func=%i reg=%i\n", bus,dev,func,reg); */
142    
143     /* Pass PCI accesses onto bus_pci: */
144     bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
145     bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
146     &odata : &idata, len, writeflag);
147    
148     if (writeflag == MEM_READ)
149     memory_writemax64(cpu, data, len, odata);
150    
151     return 1;
152     }
153    
154    
155 dpavlin 24 DEVICE_ACCESS(lca_isa)
156     {
157     int ofs, i;
158     uint8_t byte;
159    
160     relative_addr >>= 5;
161    
162     ofs = relative_addr & 3;
163     if (ofs > len) {
164     fatal("[ ofs=%i len=%i in lca_isa access function. "
165     "aborting ]\n", ofs, len);
166     exit(1);
167     }
168    
169     if (writeflag == MEM_WRITE) {
170     byte = data[ofs % len];
171     return cpu->memory_rw(cpu, cpu->mem, LCA_ISA_BASE +
172     relative_addr, &byte, 1, writeflag, CACHE_NONE);
173     }
174    
175     cpu->memory_rw(cpu, cpu->mem, LCA_ISA_BASE + relative_addr,
176     &byte, 1, MEM_READ, CACHE_NONE);
177    
178     for (i=0; i<len; i++)
179     data[i] = i == ofs? byte : 0x00;
180    
181     return 1;
182     }
183    
184    
185 dpavlin 32 DEVICE_ACCESS(lca_ioc)
186     {
187     uint64_t idata = 0, odata = 0;
188     struct lca_data *d = extra;
189    
190     if (writeflag == MEM_WRITE)
191     idata = memory_readmax64(cpu, data, len);
192    
193     switch (relative_addr + LCA_IOC_BASE) {
194    
195     case LCA_IOC_BASE:
196     /* Ignore? Linux reads from the base at startup. */
197     break;
198    
199     case LCA_IOC_CONF:
200     if (writeflag == MEM_READ) {
201     odata = d->ioc_conf;
202     } else {
203     d->ioc_conf = idata;
204     /* Only bit 0 is implemented so far, the PCI bus 0 vs
205     bus non-0 selection bit. */
206     if (idata & ~1) {
207     fatal("TODO: Write to unimplemented bit of"
208     " IOC_CONF: 0x%x\n", (int)idata);
209     exit(1);
210     }
211     }
212     break;
213    
214     case LCA_IOC_TBIA:
215     /* TLB Invalidate All. */
216     /* TODO: For now, let's just ignore it. */
217     break;
218    
219     case LCA_IOC_TB_ENA:
220     if (writeflag == MEM_READ) {
221     odata = d->tlb_enable;
222     } else {
223     d->tlb_enable = idata;
224     /* TODO: Actually implement this. */
225     if (idata & ~IOC_TB_ENA_TEN) {
226     fatal("TODO: LCA_IOC_TB_ENA value "
227     " (0x%"PRIx64") has unimplemented "
228     "bits.\n", (uint64_t)idata);
229     exit(1);
230     }
231     }
232     break;
233    
234     case LCA_IOC_W_BASE0:
235     if (writeflag == MEM_READ) {
236     odata = d->window_base_0;
237     } else {
238     d->window_base_0 = idata;
239     /* TODO: Actually implement this. */
240     if (idata != 0ULL && idata != 0x300800000ULL) {
241     fatal("TODO: LCA_IOC_W_BASE0 value differs"
242     " (0x%"PRIx64") from the only implemented"
243     " values\n", (uint64_t)idata);
244     exit(1);
245     }
246     }
247     break;
248    
249     case LCA_IOC_W_MASK0:
250     if (writeflag == MEM_READ) {
251     odata = d->window_mask_0;
252     } else {
253     d->window_mask_0 = idata;
254     /* TODO: Actually implement this. */
255     if (idata != 0x700000ULL) {
256     fatal("TODO: LCA_IOC_W_MASK0 value differs"
257     " (0x%"PRIx64") from the only implemented"
258     " value\n", (uint64_t)idata);
259     exit(1);
260     }
261     }
262     break;
263    
264     case LCA_IOC_W_T_BASE0:
265     if (writeflag == MEM_READ) {
266     odata = d->window_t_base_0;
267     } else {
268     d->window_t_base_0 = idata;
269     /* TODO: Actually implement this. */
270     }
271     break;
272    
273     case LCA_IOC_W_BASE1:
274     if (writeflag == MEM_READ) {
275     odata = d->window_base_1;
276     } else {
277     d->window_base_1 = idata;
278     /* TODO: Actually implement this. */
279     if (idata != 0x240000000ULL) {
280     fatal("TODO: LCA_IOC_W_BASE1 value differs"
281     " (0x%"PRIx64") from the only implemented"
282     " value\n", (uint64_t)idata);
283     exit(1);
284     }
285     }
286     break;
287    
288     case LCA_IOC_W_MASK1:
289     if (writeflag == MEM_READ) {
290     odata = d->window_mask_1;
291     } else {
292     d->window_mask_1 = idata;
293     /* TODO: Actually implement this. */
294     if (idata != 0x3ff00000ULL) {
295     fatal("TODO: LCA_IOC_W_MASK1 value differs"
296     " (0x%"PRIx64") from the only implemented"
297     " value\n", (uint64_t)idata);
298     exit(1);
299     }
300     }
301     break;
302    
303     case LCA_IOC_W_T_BASE1:
304     if (writeflag == MEM_READ) {
305     odata = d->window_t_base_1;
306     } else {
307     d->window_t_base_1 = idata;
308     /* TODO: Actually implement this. */
309     }
310     break;
311    
312     default:fatal("[ lca_ioc: unimplemented %s to offset 0x%x",
313     writeflag == MEM_WRITE? "write" : "read", (int)
314     relative_addr);
315     if (writeflag == MEM_WRITE)
316     fatal(": 0x%x", (int)idata);
317     fatal(" ]\n");
318     exit(1);
319     }
320    
321     if (writeflag == MEM_READ)
322     memory_writemax64(cpu, data, len, odata);
323    
324     return 1;
325     }
326    
327    
328 dpavlin 24 DEVINIT(lca)
329     {
330 dpavlin 34 char *interrupt_path;
331     struct interrupt interrupt_template;
332 dpavlin 24 struct lca_data *d = malloc(sizeof(struct lca_data));
333     if (d == NULL) {
334     fprintf(stderr, "out of memory\n");
335     exit(1);
336     }
337     memset(d, 0, sizeof(struct lca_data));
338    
339 dpavlin 32 /* Register a PCI bus: */
340     d->pci_data = bus_pci_init(
341     devinit->machine,
342 dpavlin 34 "TODO: irq" /* pciirq: TODO */,
343 dpavlin 32 LCA_PCI_SIO, /* pci device io offset */
344     0x00000000, /* pci device mem offset: TODO */
345     0x00000000, /* PCI portbase: TODO */
346     0x00000000, /* PCI membase: TODO */
347 dpavlin 34 "TODO: pci irq base", /* PCI irqbase: TODO */
348 dpavlin 32 LCA_ISA_BASE, /* ISA portbase */
349     LCA_ISA_MEMBASE, /* ISA membase */
350 dpavlin 34 "TODO: irqbase isa"); /* ISA irqbase: TODO */
351 dpavlin 32
352     /* Add the "sio0" controller (as seen by NetBSD): */
353     bus_pci_add(devinit->machine, d->pci_data, devinit->machine->memory,
354     0, 7, 0, "i82378zb");
355    
356     memory_device_register(devinit->machine->memory, "lca_pci_conf",
357     LCA_PCI_CONF, 0x20000000, dev_lca_pci_conf_access, (void *)d,
358     DM_DEFAULT, NULL);
359    
360 dpavlin 24 memory_device_register(devinit->machine->memory, "lca_isa",
361     LCA_PCI_SIO, 0x10000 << 5, dev_lca_isa_access, (void *)d,
362     DM_DEFAULT, NULL);
363    
364 dpavlin 32 memory_device_register(devinit->machine->memory, "lca_ioc",
365     LCA_IOC_BASE, 0x20000000, dev_lca_ioc_access, (void *)d,
366     DM_DEFAULT, NULL);
367    
368 dpavlin 34 interrupt_path = malloc(strlen(devinit->machine->path) + 10);
369     snprintf(interrupt_path, strlen(devinit->machine->path) + 10,
370     "%s.lca", devinit->machine->path);
371 dpavlin 24
372 dpavlin 34 memset(&interrupt_template, 0, sizeof(interrupt_template));
373     interrupt_template.line = 0;
374     interrupt_template.name = interrupt_path;
375     interrupt_template.extra = d;
376     interrupt_template.interrupt_assert = lca_interrupt_assert;
377     interrupt_template.interrupt_deassert = lca_interrupt_deassert;
378     interrupt_handler_register(&interrupt_template);
379    
380     bus_isa_init(devinit->machine, interrupt_path,
381     BUS_ISA_IDE0 | BUS_ISA_IDE1, LCA_ISA_BASE, LCA_ISA_MEMBASE);
382    
383 dpavlin 24 return 1;
384     }
385    
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