/[gxemul]/trunk/src/devices/dev_kn02.c
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Diff of /trunk/src/devices/dev_kn02.c

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revision 41 by dpavlin, Mon Oct 8 16:21:17 2007 UTC revision 42 by dpavlin, Mon Oct 8 16:22:32 2007 UTC
# Line 25  Line 25 
25   *  SUCH DAMAGE.   *  SUCH DAMAGE.
26   *     *  
27   *   *
28   *  $Id: dev_kn02.c,v 1.26 2007/02/10 14:20:52 debug Exp $   *  $Id: dev_kn02.c,v 1.28 2007/06/15 19:11:15 debug Exp $
29   *     *  
30   *  KN02 mainbus (TurboChannel interrupt controller).   *  COMMENT: DEC KN02 mainbus (TurboChannel interrupt controller)
31   *   *
32   *  Used in DECstation type 2 ("3MAX").  See include/dec_kn02.h for more info.   *  Used in DECstation type 2 ("3MAX").  See include/dec_kn02.h for more info.
33   */   */
# Line 44  Line 44 
44  #include "misc.h"  #include "misc.h"
45    
46    
47    #include "dec_kn02.h"
48    
49  #define DEV_KN02_LENGTH         0x1000  #define DEV_KN02_LENGTH         0x1000
50    
51    
# Line 96  DEVICE_ACCESS(kn02) Line 98  DEVICE_ACCESS(kn02)
98                  if (writeflag==MEM_READ) {                  if (writeflag==MEM_READ) {
99                          odata = d->csr[0] + (d->csr[1] << 8) +                          odata = d->csr[0] + (d->csr[1] << 8) +
100                              (d->csr[2] << 16) + (d->csr[3] << 24);                              (d->csr[2] << 16) + (d->csr[3] << 24);
101    
102                          /* debug("[ kn02: read from CSR: 0x%08x ]\n", odata); */                          /* debug("[ kn02: read from CSR: 0x%08x ]\n", odata); */
103                  } else {                  } else {
104                          /*                          /*
# Line 146  DEVICE_ACCESS(kn02) Line 149  DEVICE_ACCESS(kn02)
149  DEVINIT(kn02)  DEVINIT(kn02)
150  {  {
151          struct kn02_data *d;          struct kn02_data *d;
152            uint32_t csr;
153          int i;          int i;
154    
155          d = malloc(sizeof(struct kn02_data));          CHECK_ALLOCATION(d = malloc(sizeof(struct kn02_data)));
         if (d == NULL) {  
                 fprintf(stderr, "out of memory\n");  
                 exit(1);  
         }  
156          memset(d, 0, sizeof(struct kn02_data));          memset(d, 0, sizeof(struct kn02_data));
157    
158          /*  Connect the KN02 to a specific MIPS CPU interrupt line:  */          /*  Connect the KN02 to a specific MIPS CPU interrupt line:  */
# Line 173  DEVINIT(kn02) Line 173  DEVINIT(kn02)
173                  interrupt_handler_register(&template);                  interrupt_handler_register(&template);
174          }          }
175    
176            /*
177             *  Set initial value of the CSR. Note: If the KN02_CSR_NRMMOD bit
178             *  is not set, the 5000/200 PROM image loops forever.
179             */
180            csr = KN02_CSR_NRMMOD;
181            d->csr[0] = csr;
182            d->csr[1] = csr >> 8;
183            d->csr[2] = csr >> 16;
184            d->csr[3] = csr >> 24;
185    
186          memory_device_register(devinit->machine->memory, devinit->name,          memory_device_register(devinit->machine->memory, devinit->name,
187              devinit->addr, DEV_KN02_LENGTH, dev_kn02_access, d,              devinit->addr, DEV_KN02_LENGTH, dev_kn02_access, d,
188              DM_DYNTRANS_OK, &d->csr[0]);              DM_DYNTRANS_OK, &d->csr[0]);
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