/[gxemul]/trunk/src/devices/dev_jazz.c
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Contents of /trunk/src/devices/dev_jazz.c

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Revision 24 - (show annotations)
Mon Oct 8 16:19:56 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 13579 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1256 2006/06/23 20:43:44 debug Exp $
20060219	Various minor updates. Removing the old MIPS16 skeleton code,
		because it will need to be rewritten for dyntrans anyway.
20060220-22	Removing the non-working dyntrans backend support.
		Continuing on the 64-bit dyntrans virtual memory generalization.
20060223	More work on the 64-bit vm generalization.
20060225	Beginning on MIPS dyntrans load/store instructions.
		Minor PPC updates (64-bit load/store, etc).
		Fixes for the variable-instruction-length framework, some
		minor AVR updates (a simple Hello World program works!).
		Beginning on a skeleton for automatically generating documen-
		tation (for devices etc.).
20060226	PPC updates (adding some more 64-bit instructions, etc).
		AVR updates (more instructions).
		FINALLY found and fixed the zs bug, making NetBSD/macppc
		accept the serial console.
20060301	Adding more AVR instructions.
20060304	Continuing on AVR-related stuff. Beginning on a framework for
		cycle-accurate device emulation. Adding an experimental "PAL
		TV" device (just a dummy so far).
20060305	Adding more AVR instructions.
		Adding a dummy epcom serial controller (for TS7200 emulation).
20060310	Removing the emul() command from configuration files, so only
		net() and machine() are supported.
		Minor progress on the MIPS dyntrans rewrite.
20060311	Continuing on the MIPS dyntrans rewrite (adding more
		instructions, etc).
20060315	Adding more instructions (sllv, srav, srlv, bgtz[l], blez[l],
		beql, bnel, slti[u], various loads and stores).
20060316	Removing the ALWAYS_SIGNEXTEND_32 option, since it was rarely
		used.
		Adding more MIPS dyntrans instructions, and fixing bugs.
20060318	Implementing fast loads/stores for MIPS dyntrans (big/little
		endian, 32-bit and 64-bit modes).
20060320	Making MIPS dyntrans the default configure option; use
		"--enable-oldmips" to use the old bintrans system.
		Adding MIPS dyntrans dmult[u]; minor updates.
20060322	Continuing... adding some more instructions.
		Adding a simple skeleton for demangling C++ "_ZN" symbols.
20060323	Moving src/debugger.c into a new directory (src/debugger/).
20060324	Fixing the hack used to load PPC ELFs (useful for relocated
		Linux/ppc kernels), and adding a dummy G3 machine mode.
20060325-26	Beginning to experiment with GDB remote serial protocol
		connections; adding a -G command line option for selecting
		which TCP port to listen to.
20060330	Beginning a major cleanup to replace things like "0x%016llx"
		with more correct "0x%016"PRIx64, etc.
		Continuing on the GDB remote serial protocol support.
20060331	More cleanup, and some minor GDB remote progress.
20060402	Adding a hack to the configure script, to allow compilation
		on systems that lack PRIx64 etc.
20060406	Removing the temporary FreeBSD/arm hack in dev_ns16550.c and
		replacing it with a better fix from Olivier Houchard.
20060407	A remote debugger (gdb or ddd) can now start and stop the
		emulator using the GDB remote serial protocol, and registers
		and memory can be read. MIPS only for now.
20060408	More GDB progress: single-stepping also works, and also adding
		support for ARM, PowerPC, and Alpha targets.
		Continuing on the delay-slot-across-page-boundary issue.
20060412	Minor update: beginning to add support for the SPARC target
		to the remote GDB functionality.
20060414	Various MIPS updates: adding more instructions for dyntrans
		(eret, add), and making some exceptions work. Fixing a bug
		in dmult[u].
		Implementing the first SPARC instructions (sethi, or).
20060415	Adding "magic trap" instructions so that PROM calls can be
		software emulated in MIPS dyntrans.
		Adding more MIPS dyntrans instructions (ddiv, dadd) and
		fixing another bug in dmult.
20060416	More MIPS dyntrans progress: adding [d]addi, movn, movz, dsllv,
		rfi, an ugly hack for supporting R2000/R3000 style faked caches,
		preliminary interrupt support, and various other updates and
		bugfixes.
20060417	Adding more SPARC instructions (add, sub, sll[x], sra[x],
		srl[x]), and useful SPARC header definitions.
		Adding the first (trivial) x86/AMD64 dyntrans instructions (nop,
		cli/sti, stc/clc, std/cld, simple mov, inc ax). Various other
		x86 updates related to variable instruction length stuff.
		Adding unaligned loads/stores to the MIPS dyntrans mode (but
		still using the pre-dyntrans (slow) imlementation).
20060419	Fixing a MIPS dyntrans exception-in-delay-slot bug.
		Removing the old "show opcode statistics" functionality, since
		it wasn't really useful and isn't implemented for dyntrans.
		Single-stepping (or running with instruction trace) now looks
		ok with dyntrans with delay-slot architectures.
20060420	Minor hacks (removing the -B command line option when compiled
		for non-bintrans, and some other very minor updates).
		Adding (slow) MIPS dyntrans load-linked/store-conditional.
20060422	Applying fixes for bugs discovered by Nils Weller's nwcc
		(static DEC memmap => now per machine, and adding an extern
		keyword in cpu_arm_instr.c).
		Finally found one of the MIPS dyntrans bugs that I've been
		looking for (copy/paste spelling error BIG vs LITTLE endian in
		cpu_mips_instr_loadstore.c for 16-bit fast stores).
		FINALLY found the major MIPS dyntrans bug: slti vs sltiu
		signed/unsigned code in cpu_mips_instr.c. :-)
		Adding more MIPS dyntrans instructions (lwc1, swc1, bgezal[l],
		ctc1, tlt[u], tge[u], tne, beginning on rdhwr).
		NetBSD/hpcmips can now reach userland when using dyntrans :-)
		Adding some more x86 dyntrans instructions.
		Finally removed the old Alpha-specific virtual memory code,
		and replaced it with the generic 64-bit version.
		Beginning to add disassembly support for SPECIAL3 MIPS opcodes.
20060423	Continuing on the delay-slot-across-page-boundary issue;
		adding an end_of_page2 ic slot (like I had planned before, but
		had removed for some reason).
		Adding a quick-and-dirty fallback to legacy coprocessor 1
		code (i.e. skipping dyntrans implementation for now).
		NetBSD/hpcmips and NetBSD/pmax (when running on an emulated
		R4400) can now be installed and run. :-)  (Many bugs left
		to fix, though.)
		Adding more MIPS dyntrans instructions: madd[u], msub[u].
		Cleaning up the SPECIAL2 vs R5900/TX79/C790 "MMI" opcode
		maps somewhat (disassembly and dyntrans instruction decoding).
20060424	Adding an isa_revision field to mips_cpu_types.h, and making
		sure that SPECIAL3 opcodes cause Reserved Instruction
		exceptions on MIPS32/64 revisions lower than 2.
		Adding the SPARC 'ba', 'call', 'jmpl/retl', 'and', and 'xor'
		instructions.
20060425	Removing the -m command line option ("run at most x 
		instructions") and -T ("single_step_on_bad_addr"), because
		they never worked correctly with dyntrans anyway.
		Freshening up the man page.
20060428	Adding more MIPS dyntrans instructions: bltzal[l], idle.
		Enabling MIPS dyntrans compare interrupts.
20060429	FINALLY found the weird dyntrans bug, causing NetBSD etc. to
		behave strangely: some floating point code (conditional
		coprocessor branches) could not be reused from the old
		non-dyntrans code. The "quick-and-dirty fallback" only appeared
		to work. Fixing by implementing bc1* for MIPS dyntrans.
		More MIPS instructions: [d]sub, sdc1, ldc1, dmtc1, dmfc1, cfc0.
		Freshening up MIPS floating point disassembly appearance.
20060430	Continuing on C790/R5900/TX79 disassembly; implementing 128-bit
		"por" and "pextlw".
20060504	Disabling -u (userland emulation) unless compiled as unstable
		development version.
		Beginning on freshening up the testmachine include files,
		to make it easier to reuse those files (placing them in
		src/include/testmachine/), and beginning on a set of "demos"
		or "tutorials" for the testmachine functionality.
		Minor updates to the MIPS GDB remote protocol stub.
		Refreshing doc/experiments.html and gdb_remote.html.
		Enabling Alpha emulation in the stable release configuration,
		even though no guest OSes for Alpha can run yet.
20060505	Adding a generic 'settings' object, which will contain
		references to settable variables (which will later be possible
		to access using the debugger).
20060506	Updating dev_disk and corresponding demo/documentation (and
		switching from SCSI to IDE disk types, so it actually works
		with current test machines :-).
20060510	Adding a -D_LARGEFILE_SOURCE hack for 64-bit Linux hosts,
		so that fseeko() doesn't give a warning.
		Updating the section about how dyntrans works (the "runnable
		IR") in doc/intro.html.
		Instruction updates (some x64=1 checks, some more R5900
		dyntrans stuff: better mul/mult separation from MIPS32/64,
		adding ei and di).
		Updating MIPS cpuregs.h to a newer one (from NetBSD).
		Adding more MIPS dyntrans instructions: deret, ehb.
20060514	Adding disassembly and beginning implementation of SPARC wr
		and wrpr instructions.
20060515	Adding a SUN SPARC machine mode, with dummy SS20 and Ultra1
		machines. Adding the 32-bit "rd psr" instruction.
20060517	Disassembly support for the general SPARC rd instruction.
		Partial implementation of the cmp (subcc) instruction.
		Some other minor updates (making sure that R5900 processors
		start up with the EIE bit enabled, otherwise Linux/playstation2
		receives no interrupts).
20060519	Minor MIPS updates/cleanups.
20060521	Moving the MeshCube machine into evbmips; this seems to work
		reasonably well with a snapshot of a NetBSD MeshCube kernel.
		Cleanup/fix of MIPS config0 register initialization.
20060529	Minor MIPS fixes, including a sign-extension fix to the
		unaligned load/store code, which makes NetBSD/pmax on R3000
		work better with dyntrans. (Ultrix and Linux/DECstation still
		don't work, though.)
20060530	Minor updates to the Alpha machine mode: adding an AlphaBook
		mode, an LCA bus (forwarding accesses to an ISA bus), etc.
20060531	Applying a bugfix for the MIPS dyntrans sc[d] instruction from
		Ondrej Palkovsky. (Many thanks.)
20060601	Minifix to allow ARM immediate msr instruction to not give
		an error for some valid values.
		More Alpha updates.
20060602	Some minor Alpha updates.
20060603	Adding the Alpha cmpbge instruction. NetBSD/alpha prints its
		first boot messages :-) on an emulated Alphabook 1.
20060612	Minor updates; adding a dev_ether.h include file for the
		testmachine ether device. Continuing the hunt for the dyntrans
		bug which makes Linux and Ultrix on DECstation behave
		strangely... FINALLY found it! It seems to be related to
		invalidation of the translation cache, on tlbw{r,i}. There
		also seems to be some remaining interrupt-related problems.
20060614	Correcting the implementation of ldc1/sdc1 for MIPS dyntrans
		(so that it uses 16 32-bit registers if the FR bit in the
		status register is not set).
20060616	REMOVING BINTRANS COMPLETELY!
		Removing the old MIPS interpretation mode.
		Removing the MFHILO_DELAY and instruction delay stuff, because
		they wouldn't work with dyntrans anyway.
20060617	Some documentation updates (adding "NetBSD-archive" to some
		URLs, and new Debian/DECstation installation screenshots).
		Removing the "tracenull" and "enable-caches" configure options.
		Improving MIPS dyntrans performance somewhat (only invalidate
		translations if necessary, on writes to the entryhi register,
		instead of doing it for all cop0 writes).
20060618	More cleanup after the removal of the old MIPS emulation.
		Trying to fix the MIPS dyntrans performance bugs/bottlenecks;
		only semi-successful so far (for R3000).
20060620	Minor update to allow clean compilation again on Tru64/Alpha.
20060622	MIPS cleanup and fixes (removing the pc_last stuff, which
		doesn't make sense with dyntrans anyway, and fixing a cross-
		page-delay-slot-with-exception case in end_of_page).
		Removing the old max_random_cycles_per_chunk stuff, and the
		concept of cycles vs instructions for MIPS emulation.
		FINALLY found and fixed the bug which caused NetBSD/pmax
		clocks to behave strangely (it was a load to the zero register,
		which was treated as a NOP; now it is treated as a load to a
		dummy scratch register).
20060623	Increasing the dyntrans chunk size back to
		N_SAFE_DYNTRANS_LIMIT, instead of N_SAFE_DYNTRANS_LIMIT/2.
		Preparing for a quick release, even though there are known
		bugs, and performance for non-R3000 MIPS emulation is very
		poor. :-/
		Reverting to half the dyntrans chunk size again, because
		NetBSD/cats seemed less stable with full size chunks. :(
		NetBSD/sgimips 3.0 can now run :-)  (With release 0.3.8, only
		NetBSD/sgimips 2.1 worked, not 3.0.)

==============  RELEASE 0.4.0  ==============


1 /*
2 * Copyright (C) 2004-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_jazz.c,v 1.24 2006/03/04 12:38:47 debug Exp $
29 *
30 * Microsoft Jazz-related stuff (Acer PICA-61, etc).
31 *
32 * TODO/NOTE: This is mostly a quick hack, it doesn't really implement
33 * much of the Jazz architecture. Also, the a0/20 isa-like stuff is
34 * not supposed to be here.
35 */
36
37 #include <stdio.h>
38 #include <stdlib.h>
39 #include <string.h>
40
41 #include "cpu.h"
42 #include "device.h"
43 #include "devices.h"
44 #include "machine.h"
45 #include "memory.h"
46 #include "misc.h"
47
48 #include "jazz_r4030_dma.h"
49 #include "pica.h"
50
51
52 #define DEV_JAZZ_TICKSHIFT 14
53
54 #define PICA_TIMER_IRQ 15
55
56
57 /*
58 * dev_jazz_dma_controller():
59 */
60 size_t dev_jazz_dma_controller(void *dma_controller_data,
61 unsigned char *data, size_t len, int writeflag)
62 {
63 struct jazz_data *d = (struct jazz_data *) dma_controller_data;
64 struct cpu *cpu = d->cpu;
65 int i, enab_writeflag;
66 int res, ncpy;
67 uint32_t dma_addr;
68 unsigned char tr[sizeof(uint32_t)];
69 uint32_t phys_addr;
70
71 #if 0
72 fatal("[ dev_jazz_dma_controller(): writeflag=%i, len=%i, data =",
73 writeflag, (int)len);
74 for (i=0; i<len; i++)
75 fatal(" %02x", data[i]);
76 fatal(" mode=%08x enable=%08x count=%08x addr=%08x",
77 d->dma0_mode, d->dma0_enable, d->dma0_count, d->dma0_addr);
78 fatal(" table=%08x",
79 d->dma_translation_table_base);
80 fatal(" ]\n");
81 #endif
82
83 if (!(d->dma0_enable & R4030_DMA_ENAB_RUN)) {
84 fatal("[ dev_jazz_dma_controller(): dma not enabled? ]\n");
85 /* return 0; */
86 }
87
88 /* R4030 "write" means write to the device, writeflag as the
89 argument to this function means write to memory. */
90 enab_writeflag = (d->dma0_enable & R4030_DMA_ENAB_WRITE)? 0 : 1;
91 if (enab_writeflag != writeflag) {
92 fatal("[ dev_jazz_dma_controller(): wrong direction? ]\n");
93 return 0;
94 }
95
96 dma_addr = d->dma0_addr;
97 i = 0;
98 while (dma_addr < d->dma0_addr + d->dma0_count && i < (int32_t)len) {
99
100 res = cpu->memory_rw(cpu, cpu->mem,
101 d->dma_translation_table_base + (dma_addr >> 12) * 8,
102 tr, sizeof(tr), 0, PHYSICAL | NO_EXCEPTIONS);
103
104 if (cpu->byte_order==EMUL_BIG_ENDIAN)
105 phys_addr = (tr[0] << 24) + (tr[1] << 16) +
106 (tr[2] << 8) + tr[3];
107 else
108 phys_addr = (tr[3] << 24) + (tr[2] << 16) +
109 (tr[1] << 8) + tr[0];
110 phys_addr &= ~0xfff; /* just in case */
111 phys_addr += (dma_addr & 0xfff);
112
113 /* fatal(" !!! dma_addr = %08x, phys_addr = %08x\n",
114 (int)dma_addr, (int)phys_addr); */
115
116 /* Speed up the copying by copying 16 or 256 bytes: */
117 ncpy = 1;
118 if ((phys_addr & 15) == 0 && i + 15 <= (int32_t)len)
119 ncpy = 15;
120 if ((phys_addr & 255) == 0 && i + 255 <= (int32_t)len)
121 ncpy = 255;
122
123 res = cpu->memory_rw(cpu, cpu->mem, phys_addr,
124 &data[i], ncpy, writeflag, PHYSICAL | NO_EXCEPTIONS);
125
126 dma_addr += ncpy;
127 i += ncpy;
128 }
129
130 /* TODO: Is this correct? */
131 d->dma0_count = 0;
132
133 return len;
134 }
135
136
137 /*
138 * dev_jazz_tick():
139 */
140 void dev_jazz_tick(struct cpu *cpu, void *extra)
141 {
142 struct jazz_data *d = extra;
143
144 /* Used by NetBSD/arc and OpenBSD/arc: */
145 if (d->interval_start > 0 && d->interval > 0
146 && (d->int_enable_mask & 2) /* Hm? */ ) {
147 d->interval -= 2;
148 if (d->interval <= 0) {
149 debug("[ jazz: interval timer interrupt ]\n");
150 cpu_interrupt(cpu, 8 + PICA_TIMER_IRQ);
151 }
152 }
153
154 /* Linux? */
155 if (d->jazz_timer_value != 0) {
156 d->jazz_timer_current -= 5;
157 if (d->jazz_timer_current < 1) {
158 d->jazz_timer_current = d->jazz_timer_value;
159 cpu_interrupt(cpu, 6);
160 }
161 }
162 }
163
164
165 /*
166 * dev_jazz_access():
167 */
168 DEVICE_ACCESS(jazz)
169 {
170 struct jazz_data *d = (struct jazz_data *) extra;
171 uint64_t idata = 0, odata = 0;
172 int regnr;
173
174 if (writeflag == MEM_WRITE)
175 idata = memory_readmax64(cpu, data, len);
176
177 regnr = relative_addr / sizeof(uint32_t);
178
179 switch (relative_addr) {
180 case R4030_SYS_CONFIG:
181 if (writeflag == MEM_WRITE) {
182 fatal("[ jazz: unimplemented write to R4030_SYS_CONFIG"
183 ", data=0x%08x ]\n", (int)idata);
184 } else {
185 /* Reading the config register should give
186 0x0104 or 0x0410. Why? TODO */
187 odata = 0x104;
188 }
189 break;
190 case R4030_SYS_TL_BASE:
191 if (writeflag == MEM_WRITE) {
192 d->dma_translation_table_base = idata;
193 } else {
194 odata = d->dma_translation_table_base;
195 }
196 break;
197 case R4030_SYS_TL_LIMIT:
198 if (writeflag == MEM_WRITE) {
199 d->dma_translation_table_limit = idata;
200 } else {
201 odata = d->dma_translation_table_limit;
202 }
203 break;
204 case R4030_SYS_TL_IVALID:
205 /* TODO: Does invalidation actually need to be implemented? */
206 break;
207 case R4030_SYS_DMA0_REGS:
208 if (writeflag == MEM_WRITE) {
209 d->dma0_mode = idata;
210 } else {
211 odata = d->dma0_mode;
212 }
213 break;
214 case R4030_SYS_DMA0_REGS + 0x8:
215 if (writeflag == MEM_WRITE) {
216 d->dma0_enable = idata;
217 } else {
218 odata = d->dma0_enable;
219 }
220 break;
221 case R4030_SYS_DMA0_REGS + 0x10:
222 if (writeflag == MEM_WRITE) {
223 d->dma0_count = idata;
224 } else {
225 odata = d->dma0_count;
226 }
227 break;
228 case R4030_SYS_DMA0_REGS + 0x18:
229 if (writeflag == MEM_WRITE) {
230 d->dma0_addr = idata;
231 } else {
232 odata = d->dma0_addr;
233 }
234 break;
235 case R4030_SYS_DMA1_REGS:
236 if (writeflag == MEM_WRITE) {
237 d->dma1_mode = idata;
238 } else {
239 odata = d->dma1_mode;
240 }
241 break;
242 case R4030_SYS_ISA_VECTOR:
243 /* ? */
244 printf("R4030_SYS_ISA_VECTOR: w=%i\n", writeflag);
245 {
246 uint32_t x = d->isa_int_asserted
247 & d->isa_int_enable_mask;
248 odata = 0;
249 while (odata < 16) {
250 if (x & (1 << odata))
251 break;
252 odata ++;
253 }
254 if (odata >= 16)
255 odata = 0;
256 }
257 break;
258 case R4030_SYS_IT_VALUE: /* Interval timer reload value */
259 if (writeflag == MEM_WRITE) {
260 d->interval_start = idata;
261 d->interval = d->interval_start;
262 } else
263 odata = d->interval_start;
264 break;
265 case R4030_SYS_IT_STAT:
266 /* Accessing this word seems to acknowledge interrupts? */
267 cpu_interrupt_ack(cpu, 8 + PICA_TIMER_IRQ);
268 if (writeflag == MEM_WRITE)
269 d->interval = idata;
270 else
271 odata = d->interval;
272 d->interval = d->interval_start;
273 break;
274 case R4030_SYS_EXT_IMASK:
275 if (writeflag == MEM_WRITE) {
276 d->int_enable_mask = idata;
277 /* Do a "nonsense" interrupt recalibration: */
278 cpu_interrupt_ack(cpu, 8);
279 } else
280 odata = d->int_enable_mask;
281 break;
282 default:
283 if (writeflag == MEM_WRITE) {
284 fatal("[ jazz: unimplemented write to address 0x%x"
285 ", data=0x%02x ]\n", (int)relative_addr,
286 (int)idata);
287 } else {
288 fatal("[ jazz: unimplemented read from address 0x%x"
289 " ]\n", (int)relative_addr);
290 }
291 }
292
293 if (writeflag == MEM_READ)
294 memory_writemax64(cpu, data, len, odata);
295
296 return 1;
297 }
298
299
300 /*
301 * dev_jazz_led_access():
302 */
303 DEVICE_ACCESS(jazz_led)
304 {
305 struct jazz_data *d = (struct jazz_data *) extra;
306 uint64_t idata = 0, odata = 0;
307 int regnr;
308
309 if (writeflag == MEM_WRITE)
310 idata = memory_readmax64(cpu, data, len);
311
312 regnr = relative_addr / sizeof(uint32_t);
313
314 switch (relative_addr) {
315 case 0:
316 if (writeflag == MEM_WRITE) {
317 d->led = idata;
318 debug("[ jazz_led: write to LED: 0x%02x ]\n",
319 (int)idata);
320 } else {
321 odata = d->led;
322 }
323 break;
324 default:
325 if (writeflag == MEM_WRITE) {
326 fatal("[ jazz_led: unimplemented write to address 0x%x"
327 ", data=0x%02x ]\n", (int)relative_addr,
328 (int)idata);
329 } else {
330 fatal("[ jazz_led: unimplemented read from address 0x%x"
331 " ]\n", (int)relative_addr);
332 }
333 }
334
335 if (writeflag == MEM_READ)
336 memory_writemax64(cpu, data, len, odata);
337
338 return 1;
339 }
340
341
342 /*
343 * dev_jazz_a0_access():
344 *
345 * ISA interrupt stuff, high 8 interrupts.
346 *
347 * TODO: use isa8 stuff instead!
348 */
349 DEVICE_ACCESS(jazz_a0)
350 {
351 struct jazz_data *d = (struct jazz_data *) extra;
352 uint64_t idata = 0, odata = 0;
353
354 if (writeflag == MEM_WRITE)
355 idata = memory_readmax64(cpu, data, len);
356
357 switch (relative_addr) {
358 case 0:
359 if (writeflag == MEM_WRITE) {
360 /* TODO: only if idata == 0x20? */
361 d->isa_int_asserted &= 0xff;
362 cpu_interrupt_ack(cpu, 8 + 0);
363 }
364 break;
365 case 1:
366 if (writeflag == MEM_WRITE) {
367 idata = ((idata ^ 0xff) & 0xff) << 8;
368 d->isa_int_enable_mask =
369 (d->isa_int_enable_mask & 0xff) | idata;
370 debug("[ jazz_isa_a0: setting isa_int_enable_mask "
371 "to 0x%04x ]\n", (int)d->isa_int_enable_mask);
372 /* Recompute interrupt stuff: */
373 cpu_interrupt_ack(cpu, 8 + 0);
374 } else
375 odata = d->isa_int_enable_mask;
376 break;
377 default:
378 if (writeflag == MEM_WRITE) {
379 fatal("[ jazz_isa_a0: unimplemented write to "
380 "address 0x%x, data=0x%02x ]\n",
381 (int)relative_addr, (int)idata);
382 } else {
383 fatal("[ jazz_isa_a0: unimplemented read from "
384 "address 0x%x ]\n", (int)relative_addr);
385 }
386 }
387
388 if (writeflag == MEM_READ)
389 memory_writemax64(cpu, data, len, odata);
390
391 return 1;
392 }
393
394
395 /*
396 * dev_jazz_20_access():
397 *
398 * ISA interrupt stuff, low 8 interrupts.
399 */
400 DEVICE_ACCESS(jazz_20)
401 {
402 struct jazz_data *d = (struct jazz_data *) extra;
403 uint64_t idata = 0, odata = 0;
404
405 if (writeflag == MEM_WRITE)
406 idata = memory_readmax64(cpu, data, len);
407
408 switch (relative_addr) {
409 case 0:
410 if (writeflag == MEM_WRITE) {
411 /* TODO: only if idata == 0x20? */
412 d->isa_int_asserted &= 0xff00;
413 cpu_interrupt_ack(cpu, 8 + 0);
414 }
415 break;
416 case 1:
417 if (writeflag == MEM_WRITE) {
418 idata = (idata ^ 0xff) & 0xff;
419 d->isa_int_enable_mask =
420 (d->isa_int_enable_mask & 0xff00) | idata;
421 debug("[ jazz_isa_20: setting isa_int_enable_mask "
422 "to 0x%04x ]\n", (int)d->isa_int_enable_mask);
423 /* Recompute interrupt stuff: */
424 cpu_interrupt_ack(cpu, 8 + 0);
425 } else
426 odata = d->isa_int_enable_mask;
427 break;
428 default:
429 if (writeflag == MEM_WRITE) {
430 fatal("[ jazz_isa_20: unimplemented write to "
431 "address 0x%x, data=0x%02x ]\n",
432 (int)relative_addr, (int)idata);
433 } else {
434 fatal("[ jazz_isa_20: unimplemented read from "
435 "address 0x%x ]\n", (int)relative_addr);
436 }
437 }
438
439 if (writeflag == MEM_READ)
440 memory_writemax64(cpu, data, len, odata);
441
442 return 1;
443 }
444
445
446 /*
447 * dev_jazz_jazzio_access():
448 *
449 * See jazzio_intr() in NetBSD's
450 * /usr/src/sys/arch/arc/jazz/jazzio.c for more info.
451 */
452 DEVICE_ACCESS(jazz_jazzio)
453 {
454 struct jazz_data *d = (struct jazz_data *) extra;
455 uint64_t idata = 0, odata = 0;
456 int i, v;
457
458 if (writeflag == MEM_WRITE)
459 idata = memory_readmax64(cpu, data, len);
460
461 switch (relative_addr) {
462 case 0:
463 v = 0;
464 for (i=0; i<15; i++) {
465 if (d->int_asserted & (1<<i)) {
466 v = i+1;
467 break;
468 }
469 }
470 odata = v << 2;
471 break;
472 case 2:
473 /* TODO: Should this be here?! */
474
475 if (writeflag == MEM_WRITE)
476 d->jazz_timer_value = idata;
477 else
478 odata = d->jazz_timer_value;
479 break;
480 default:
481 if (writeflag == MEM_WRITE) {
482 fatal("[ jazzio: unimplemented write to address 0x%x"
483 ", data=0x%02x ]\n", (int)relative_addr,
484 (int)idata);
485 } else {
486 fatal("[ jazzio: unimplemented read from address 0x%x"
487 " ]\n", (int)relative_addr);
488 }
489 }
490
491 /* This is needed by Windows NT during startup: */
492 cpu_interrupt_ack(cpu, 3);
493
494 if (writeflag == MEM_READ)
495 memory_writemax64(cpu, data, len, odata);
496
497 return 1;
498 }
499
500
501 DEVINIT(jazz)
502 {
503 struct jazz_data *d = malloc(sizeof(struct jazz_data));
504 if (d == NULL) {
505 fprintf(stderr, "out of memory\n");
506 exit(1);
507 }
508 memset(d, 0, sizeof(struct jazz_data));
509
510 d->cpu = devinit->machine->cpus[0]; /* TODO */
511
512 d->isa_int_enable_mask = 0xffff;
513
514 memory_device_register(devinit->machine->memory, "jazz",
515 devinit->addr, DEV_JAZZ_LENGTH,
516 dev_jazz_access, (void *)d, DM_DEFAULT, NULL);
517
518 /* At least for Magnum and Pica-61: */
519 memory_device_register(devinit->machine->memory, "jazz_led",
520 0x08000f000ULL, 4, dev_jazz_led_access, (void *)d,
521 DM_DEFAULT, NULL);
522
523 memory_device_register(devinit->machine->memory, "jazz_isa_20",
524 0x90000020ULL, 2, dev_jazz_20_access, (void *)d, DM_DEFAULT, NULL);
525
526 memory_device_register(devinit->machine->memory, "jazz_isa_a0",
527 0x900000a0ULL, 2, dev_jazz_a0_access, (void *)d, DM_DEFAULT, NULL);
528
529 memory_device_register(devinit->machine->memory, "pica_jazzio",
530 0xf0000000ULL, 4, dev_jazz_jazzio_access, (void *)d,
531 DM_DEFAULT, NULL);
532
533 machine_add_tickfunction(devinit->machine, dev_jazz_tick,
534 d, DEV_JAZZ_TICKSHIFT, 0.0);
535
536 devinit->return_ptr = d;
537
538 return 1;
539 }
540

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