/[gxemul]/trunk/src/devices/dev_igsfb.c
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Annotation of /trunk/src/devices/dev_igsfb.c

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Revision 34 - (hide annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 7 months ago) by dpavlin
File MIME type: text/plain
File size: 11333 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============
1 dpavlin 30 /*
2 dpavlin 34 * Copyright (C) 2006-2007 Anders Gavare. All rights reserved.
3 dpavlin 30 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 34 * $Id: dev_igsfb.c,v 1.5 2006/12/30 13:30:58 debug Exp $
29 dpavlin 30 *
30     * Integraphics Systems "igsfb" Framebuffer (graphics) card, used in at
31     * least the NetWinder.
32     *
33     * TODO: This is hardcoded to 1024x768x8 right now, and only supports the
34     * two acceleration commands used by NetBSD for scrolling the
35     * framebuffer. The cursor is hardcoded to 12x22 pixels, as that is
36     * what NetBSD/netwinder uses.
37     */
38    
39     #include <stdio.h>
40     #include <stdlib.h>
41     #include <string.h>
42    
43     #include "console.h"
44     #include "device.h"
45     #include "devices.h"
46     #include "machine.h"
47     #include "memory.h"
48     #include "misc.h"
49    
50     #include "igsfbreg.h"
51     #include "vga.h"
52    
53    
54     struct dev_igsfb_data {
55     int xres;
56     int yres;
57     int bitdepth;
58     struct vfb_data *vfb_data;
59    
60     /* VGA palette stuff: */
61     int palette_write_index;
62     int palette_write_subindex;
63    
64     /*
65     * Various graphics controller registers. See igsfbreg.h for a
66     * brief explanation of what these do.
67     */
68     int src_map_width;
69     int src2_map_width;
70     int dst_map_width;
71     int src_start;
72     int src2_start;
73     int dst_start;
74     int map_fmt;
75     int ctl;
76     int fg_mix;
77     int bg_mix;
78     int width;
79     int height;
80     int fg;
81     int bg;
82     int pixel_op_0;
83     int pixel_op_1;
84     int pixel_op_2;
85     int pixel_op_3;
86    
87     uint8_t ext_reg_select;
88     uint8_t ext_reg[256];
89     };
90    
91    
92     /*
93     * recalc_sprite_position():
94     *
95     * TODO: This is hardcoded for NetBSD/netwinder's 12x22 pixel cursor.
96     */
97     static void recalc_sprite_position(struct dev_igsfb_data *d)
98     {
99     int x = d->ext_reg[IGS_EXT_SPRITE_HSTART_LO] +
100     d->ext_reg[IGS_EXT_SPRITE_HSTART_HI] * 256;
101     int y = d->ext_reg[IGS_EXT_SPRITE_VSTART_LO] +
102     d->ext_reg[IGS_EXT_SPRITE_VSTART_HI] * 256;
103    
104     dev_fb_setcursor(d->vfb_data, x, y, 1, 12, 22);
105     }
106    
107    
108     /*
109     * dev_igsfb_op3_written():
110     *
111     * This function is called after the pixel_op_3 register has been written to.
112     * I guess this is what triggers accelerated functions to start executing.
113     *
114     * NOTE/TODO: Only those necessary to run NetBSD/netwinder have been
115     * implemented.
116     */
117     static void dev_igsfb_op3_written(struct dev_igsfb_data *d)
118     {
119     if (d->pixel_op_0 == 0x00 && d->pixel_op_1 == 0x80 &&
120     d->pixel_op_2 == 0x00 && d->pixel_op_3 == 0x28 &&
121     d->fg_mix == 0x03 && d->ctl == 0x00) {
122     /* NetBSD scroll-up */
123     framebuffer_blockcopyfill(d->vfb_data, 0, 0,0,0,
124     d->dst_start % d->xres, d->dst_start / d->xres,
125     d->dst_start % d->xres + d->width,
126     d->dst_start / d->xres + d->height,
127     d->src_start % d->xres, d->src_start / d->xres);
128     return;
129     }
130    
131     if (d->pixel_op_0 == 0x00 && d->pixel_op_1 == 0x80 &&
132     d->pixel_op_2 == 0x00 && d->pixel_op_3 == 0x08 &&
133     d->fg_mix == 0x03 && d->ctl == 0x00) {
134     /* NetBSD fill */
135     /* TODO: Color! */
136     framebuffer_blockcopyfill(d->vfb_data, 1, 0,0,0,
137     d->dst_start % d->xres, d->dst_start / d->xres,
138     d->dst_start % d->xres + d->width,
139     d->dst_start / d->xres + d->height,
140     0, 0);
141     return;
142     }
143    
144     fatal("\nUnimplemented igsfb accelerated framebuffer command:\n");
145     fatal("pixel_op_0 = 0x%02x\n", d->pixel_op_0);
146     fatal("pixel_op_1 = 0x%02x\n", d->pixel_op_1);
147     fatal("pixel_op_2 = 0x%02x\n", d->pixel_op_2);
148     fatal("pixel_op_3 = 0x%02x\n", d->pixel_op_3);
149     fatal("fg_mix = 0x%02x\n", d->fg_mix);
150     fatal("ctl = 0x%02x\n", d->ctl);
151     fatal("src_start = 0x%x\n", d->src_start);
152     fatal("dst_start = 0x%x\n", d->dst_start);
153     fatal("width = %i\n", d->width);
154     fatal("height = %i\n", d->height);
155     exit(1);
156     }
157    
158    
159     DEVICE_ACCESS(igsfb)
160     {
161     uint64_t idata = 0, odata = 0;
162     struct dev_igsfb_data *d = extra;
163    
164     if (writeflag == MEM_WRITE)
165     idata = memory_readmax64(cpu, data, len);
166    
167     if (relative_addr >= 0x3c0 && relative_addr <= 0x3df) {
168     switch (relative_addr - 0x3c0) {
169     case VGA_DAC_ADDR_WRITE: /* 0x08 */
170     if (writeflag == MEM_WRITE) {
171     d->palette_write_index = idata;
172     d->palette_write_subindex = 0;
173     } else {
174     fatal("[ igsdb: WARNING: Read from "
175     "VGA_DAC_ADDR_WRITE? ]\n");
176     odata = d->palette_write_index;
177     }
178     break;
179     case VGA_DAC_DATA: /* 0x09 */
180     if (writeflag == MEM_WRITE) {
181     /* Note: 8-bit color, not 6, so it isn't
182     exactly like normal VGA palette: */
183     int new = idata & 0xff;
184     int old = d->vfb_data->rgb_palette[d->
185     palette_write_index*3+d->
186     palette_write_subindex];
187     d->vfb_data->rgb_palette[d->palette_write_index
188     * 3 + d->palette_write_subindex] = new;
189     /* Redraw whole screen, if the
190     palette changed: */
191     if (new != old) {
192     d->vfb_data->update_x1 =
193     d->vfb_data->update_y1 = 0;
194     d->vfb_data->update_x2 = d->xres - 1;
195     d->vfb_data->update_y2 = d->yres - 1;
196     }
197     d->palette_write_subindex ++;
198     if (d->palette_write_subindex == 3) {
199     d->palette_write_index ++;
200     d->palette_write_subindex = 0;
201     }
202     }
203     /* Note/TODO: Reading from the palette isn't
204     implemented here. */
205     break;
206     case 0xe: /* IGSFB extended register select */
207     if (writeflag == MEM_WRITE)
208     d->ext_reg_select = idata;
209     else
210     odata = d->ext_reg_select;
211     break;
212     case 0xf: /* IGSFB extended register data */
213     if (writeflag == MEM_READ)
214     odata = d->ext_reg[d->ext_reg_select];
215     else {
216     d->ext_reg[d->ext_reg_select] = idata;
217     switch (d->ext_reg_select) {
218     /* case IGS_EXT_SPRITE_HSTART_LO:
219     case IGS_EXT_SPRITE_HSTART_HI:
220     case IGS_EXT_SPRITE_VSTART_LO: */
221     case IGS_EXT_SPRITE_VSTART_HI:
222     recalc_sprite_position(d);
223     break;
224     }
225     }
226     break;
227     }
228     return 1;
229     }
230    
231     if (relative_addr >= IGS_COP_BASE_A &&
232     relative_addr < IGS_COP_BASE_A + IGS_COP_SIZE) {
233     fatal("[ igsfb: BASE A not implemented yet, only BASE B ]\n");
234     exit(1);
235     }
236    
237     switch (relative_addr) {
238    
239     case IGS_VDO:
240     if (writeflag == MEM_WRITE) {
241     if (idata & ~(IGS_VDO_ENABLE | IGS_VDO_SETUP)) {
242     fatal("[ igsfb: Unimplemented IGS_VDO flags:"
243     " 0x%08x ]\n", (int)idata);
244     exit(1);
245     }
246     }
247     break;
248    
249     case IGS_VSE:
250     if (writeflag == MEM_WRITE) {
251     if (idata & ~(IGS_VSE_ENABLE)) {
252     fatal("[ igsfb: Unimplemented IGS_VSE flags:"
253     " 0x%08x ]\n", (int)idata);
254     exit(1);
255     }
256     }
257     break;
258    
259     case IGS_COP_BASE_B + IGS_COP_SRC_MAP_WIDTH_REG:
260     if (writeflag == MEM_WRITE)
261     d->src_map_width = idata & 0x3ff;
262     else
263     odata = d->src_map_width;
264     break;
265    
266     case IGS_COP_BASE_B + IGS_COP_SRC2_MAP_WIDTH_REG:
267     if (writeflag == MEM_WRITE)
268     d->src2_map_width = idata & 0x3ff;
269     else
270     odata = d->src2_map_width;
271     break;
272    
273     case IGS_COP_BASE_B + IGS_COP_DST_MAP_WIDTH_REG:
274     if (writeflag == MEM_WRITE)
275     d->dst_map_width = idata & 0x3ff;
276     else
277     odata = d->dst_map_width;
278     break;
279    
280     case IGS_COP_BASE_B + IGS_COP_MAP_FMT_REG:
281     if (writeflag == MEM_WRITE)
282     d->map_fmt = idata;
283     else
284     odata = d->map_fmt;
285     break;
286    
287     case IGS_COP_BASE_B + IGS_COP_CTL_REG:
288     if (writeflag == MEM_WRITE)
289     d->ctl = idata;
290     else
291     odata = d->ctl;
292     break;
293    
294     case IGS_COP_BASE_B + IGS_COP_FG_MIX_REG:
295     if (writeflag == MEM_WRITE)
296     d->fg_mix = idata;
297     else
298     odata = d->fg_mix;
299     break;
300    
301     case IGS_COP_BASE_B + IGS_COP_BG_MIX_REG:
302     if (writeflag == MEM_WRITE)
303     d->bg_mix = idata;
304     else
305     odata = d->bg_mix;
306     break;
307    
308     case IGS_COP_BASE_B + IGS_COP_WIDTH_REG:
309     if (writeflag == MEM_WRITE)
310     d->width = idata & 0x3ff;
311     else
312     odata = d->width;
313     break;
314    
315     case IGS_COP_BASE_B + IGS_COP_HEIGHT_REG:
316     if (writeflag == MEM_WRITE)
317     d->height = idata & 0x3ff;
318     else
319     odata = d->height;
320     break;
321    
322     case IGS_COP_BASE_B + IGS_COP_SRC_START_REG:
323     if (writeflag == MEM_WRITE)
324     d->src_start = idata & 0x3fffff;
325     else
326     odata = d->src_start;
327     break;
328    
329     case IGS_COP_BASE_B + IGS_COP_SRC2_START_REG:
330     if (writeflag == MEM_WRITE)
331     d->src2_start = idata & 0x3fffff;
332     else
333     odata = d->src2_start;
334     break;
335    
336     case IGS_COP_BASE_B + IGS_COP_DST_START_REG:
337     if (writeflag == MEM_WRITE)
338     d->dst_start = idata & 0x3fffff;
339     else
340     odata = d->dst_start;
341     break;
342    
343     case IGS_COP_BASE_B + IGS_COP_FG_REG:
344     if (writeflag == MEM_WRITE)
345     d->fg = idata;
346     else
347     odata = d->fg;
348     break;
349    
350     case IGS_COP_BASE_B + IGS_COP_BG_REG:
351     if (writeflag == MEM_WRITE)
352     d->bg = idata;
353     else
354     odata = d->bg;
355     break;
356    
357     case IGS_COP_BASE_B + IGS_COP_PIXEL_OP_0_REG:
358     if (writeflag == MEM_WRITE)
359     d->pixel_op_0 = idata;
360     else
361     odata = d->pixel_op_0;
362     break;
363    
364     case IGS_COP_BASE_B + IGS_COP_PIXEL_OP_1_REG:
365     if (writeflag == MEM_WRITE)
366     d->pixel_op_1 = idata;
367     else
368     odata = d->pixel_op_1;
369     break;
370    
371     case IGS_COP_BASE_B + IGS_COP_PIXEL_OP_2_REG:
372     if (writeflag == MEM_WRITE)
373     d->pixel_op_2 = idata;
374     else
375     odata = d->pixel_op_2;
376     break;
377    
378     case IGS_COP_BASE_B + IGS_COP_PIXEL_OP_3_REG:
379     if (writeflag == MEM_WRITE) {
380     d->pixel_op_3 = idata;
381     dev_igsfb_op3_written(d);
382     } else {
383     odata = d->pixel_op_3;
384     }
385     break;
386    
387     default:if (writeflag == MEM_WRITE) {
388     fatal("[ igsfb: unimplemented write to address 0x%x"
389     " data=0x%02x ]\n", (int)relative_addr, (int)idata);
390     } else {
391     fatal("[ igsfb: unimplemented read from address 0x%x "
392     "]\n", (int)relative_addr);
393     }
394     exit(1);
395     }
396    
397     if (writeflag == MEM_READ)
398     memory_writemax64(cpu, data, len, odata);
399    
400     return 1;
401     }
402    
403    
404     DEVINIT(igsfb)
405     {
406     struct dev_igsfb_data *d;
407     d = malloc(sizeof(struct dev_igsfb_data));
408     if (d == NULL) {
409     fprintf(stderr, "out of memory\n");
410     exit(1);
411     }
412     memset(d, 0, sizeof(struct dev_igsfb_data));
413    
414     d->xres = 1024;
415     d->yres = 768;
416     d->bitdepth = 8;
417     d->vfb_data = dev_fb_init(devinit->machine, devinit->machine->memory,
418     0x400000 + devinit->addr, VFB_GENERIC, d->xres, d->yres,
419     d->xres, d->yres, d->bitdepth, "igsfb");
420    
421     /* TODO: Palette control etc at 0x3c0 + IGS_MEM_MMIO_SELECT */
422    
423     memory_device_register(devinit->machine->memory, devinit->name,
424     devinit->addr + IGS_MEM_MMIO_SELECT, 0x100000,
425     dev_igsfb_access, d, DM_DEFAULT, NULL);
426    
427     return 1;
428     }
429    
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