/[gxemul]/trunk/src/devices/dev_i80321.c
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Contents of /trunk/src/devices/dev_i80321.c

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Revision 40 - (show annotations)
Mon Oct 8 16:22:11 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 10119 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1539 2007/05/01 04:03:51 debug Exp $
20070415	Landisk PCLOCK should be 33.33 MHz, not 50 MHz. (This makes
		the clock run at correct speed.)
		FINALLY found and fixed the bug which caused OpenBSD/landisk
		to randomly bug out: an &-sign was missing in the special case
		handling of FPSCR in the 'LDS.L @Rm+,FPSCR' instruction.
		Adding similar special case handling for 'LDC.L @Rm+,SR'
		(calling sh_update_sr() instead of just loading).
		Implementing the 'FCNVSD FPUL,DRn' and 'FCNVDS DRm,FPUL'
		SuperH instructions.
		The 'LDC Rm,SR' instruction now immediately breaks out of the
		dyntrans loop if an interrupt is to be triggered.
20070416	In memory_rw.c, if mapping a page as writable, make sure to
		invalidate code translations even if the data access was a
		read.
		Minor SuperH updates.
20070418	Removing the dummy M68K emulation mode.
		Minor SH update (turning unnecessary sts_mach_rn, sts_macl_rn,
		and sts_pr_rn instruction handlers into mov_rm_rn).
20070419	Beginning to add a skeleton for an M88K mode: Adding a hack to
		allow OpenBSD/m88k a.out binaries to be loaded, and disassembly
		of a few simple 88K instructions.
		Commenting out the 'LDC Rm,SR' fix from a few days ago, because
		it made Linux/dreamcast bug out.
		Adding a hack to dev_sh4.c (an extra translation cache
		invalidation), which allows OpenBSD/landisk to boot ok after
		an install. Upgrading the Landisk machine mode to stable,
		updating documentation, etc.
20070420	Experimenting with adding a PCI controller (pcic) to dev_sh4.
		Adding a dummy Realtek 8139C+ skeleton device (dev_rtl8139c).
		Implementing the first M88K instructions (br, or[.u] imm), and
		adding disassembly of some more instructions.
20070421	Continuing a little on dev_rtl8139c.
20070422	Implementing the 9346 EEPROM "read" command for dev_rtl8139c.
		Finally found and fixed an old bug in the log n symbol search
		(it sometimes missed symbols). Debug trace (-i, -t etc) should
		now show more symbols. :-)
20070423	Continuing a little on M88K disassembly.
20070428	Fixing a memset arg order bug in src/net/net.c (thanks to
		Nigel Horne for noticing the bug).
		Applying parts of a patch from Carl van Schaik to clear out
		bottom bits of MIPS addresses more correctly, when using large
		page sizes, and doing some other minor cleanup/refactoring.
		Fixing a couple of warnings given by gcc with the -W option (a
		few more warnings than just plain -Wall).
		Reducing SuperH dyntrans physical address space from 64-bit to
		32-bit (since SH5/SH64 isn't imlemented yet anyway).
		Adding address-to-symbol annotation to a few more instructions
		in the SuperH instruction trace output.
		Beginning regression testing for the next release.
		Reverting the value of SCIF_DELAYED_TX_VALUE from 1 to 2,
		because OpenBSD/landisk may otherwise hang randomly.
20070429	The ugly hack/workaround to get OpenBSD/landisk booting without
		crashing does NOT work anymore (with the April 21 snapshot
		of OpenBSD/landisk). Strangely enough, removing the hack
		completely causes OpenBSD/landisk to work (!).
		More regression testing (re-testing everything SuperH-related,
		and some other things).
		Cobalt interrupts were actually broken; fixing by commenting
		out the DEC21143s in the Cobalt machine.
20070430	More regression testing.
20070501	Updating the OpenBSD/landisk install instructions to use
		4.1 instead of the current snapshot.
		GAAAH! OpenBSD/landisk 4.1 _needs_ the ugly hack/workaround;
		reintroducing it again. (The 4.1 kernel is actually from
		2007-03-11.)
		Simplifying the NetBSD/evbarm install instructions a bit.
		More regression testing.

==============  RELEASE 0.4.5.1  ==============
1 /*
2 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_i80321.c,v 1.21 2007/04/28 09:19:52 debug Exp $
29 *
30 * Intel i80321 (ARM) core functionality.
31 *
32 * o) Interrupt controller
33 * o) Timer
34 * o) PCI controller
35 * o) Memory controller
36 *
37 * TODO:
38 * o) LOTS of things left to implement.
39 * o) This is hardcoded for little endian emulation.
40 */
41
42 #include <stdio.h>
43 #include <stdlib.h>
44 #include <string.h>
45
46 #include "bus_pci.h"
47 #include "cpu.h"
48 #include "device.h"
49 #include "machine.h"
50 #include "memory.h"
51 #include "misc.h"
52 #include "timer.h"
53
54
55 #include "i80321reg.h"
56
57 #define TICK_SHIFT 15
58 #define DEV_I80321_LENGTH VERDE_PMMR_SIZE
59
60 struct i80321_data {
61 /* Interrupt Controller */
62 struct interrupt irq;
63 uint32_t *status; /* Note: these point to i80321_isrc */
64 uint32_t *enable; /* and i80321_inten in the CPU! */
65
66 /* Timer: */
67 struct timer *timer;
68 double hz;
69 int pending_tmr0_interrupts;
70
71 /* PCI Controller: */
72 uint32_t pci_addr;
73 struct pci_data *pci_bus;
74
75 /* Memory Controller: */
76 uint32_t mcu_reg[0x100 / sizeof(uint32_t)];
77 };
78
79
80 static void i80321_assert(struct i80321_data *d, uint32_t linemask)
81 {
82 *d->status |= linemask;
83 if (*d->status & *d->enable)
84 INTERRUPT_ASSERT(d->irq);
85 }
86 static void i80321_deassert(struct i80321_data *d, uint32_t linemask)
87 {
88 *d->status &= ~linemask;
89 if (!(*d->status & *d->enable))
90 INTERRUPT_DEASSERT(d->irq);
91 }
92
93
94 /*
95 * i80321_interrupt_assert():
96 * i80321_interrupt_deassert():
97 *
98 * Called whenever an i80321 interrupt is asserted/deasserted.
99 */
100 void i80321_interrupt_assert(struct interrupt *interrupt)
101 { i80321_assert(interrupt->extra, interrupt->line); }
102 void i80321_interrupt_deassert(struct interrupt *interrupt)
103 {
104 struct i80321_data *d = interrupt->extra;
105
106 /* Ack. timer interrupts: */
107 if (interrupt->line == 1 << 9 &&
108 d->pending_tmr0_interrupts > 0)
109 d->pending_tmr0_interrupts --;
110
111 i80321_deassert(d, interrupt->line);
112 }
113
114
115 /* TMR0 ticks, called d->hz times per second. */
116 static void tmr0_tick(struct timer *t, void *extra)
117 {
118 struct i80321_data *d = extra;
119 d->pending_tmr0_interrupts ++;
120 }
121
122
123 DEVICE_TICK(i80321)
124 {
125 struct i80321_data *d = extra;
126
127 if (cpu->cd.arm.tmr0 & TMRx_ENABLE && d->pending_tmr0_interrupts > 0) {
128 i80321_assert(d, 1 << 9);
129 cpu->cd.arm.tisr |= TISR_TMR0;
130 } else {
131 i80321_deassert(d, 1 << 9);
132 cpu->cd.arm.tisr &= ~TISR_TMR0;
133 }
134 }
135
136
137 DEVICE_ACCESS(i80321)
138 {
139 struct i80321_data *d = extra;
140 uint64_t idata = 0, odata = 0;
141 char *n = NULL;
142 int bus, dev, func, reg;
143
144 if (writeflag == MEM_WRITE)
145 idata = memory_readmax64(cpu, data, len);
146
147 /* PCI configuration space: */
148 if (relative_addr >= 0x100 && relative_addr < 0x140) {
149 /* TODO */
150 goto ret;
151 }
152
153 /* MCU registers: */
154 if (relative_addr >= VERDE_MCU_BASE &&
155 relative_addr < VERDE_MCU_BASE + VERDE_MCU_SIZE) {
156 int regnr = (relative_addr - VERDE_MCU_BASE) / sizeof(uint32_t);
157 if (writeflag == MEM_WRITE)
158 d->mcu_reg[regnr] = idata;
159 else
160 odata = d->mcu_reg[regnr];
161 }
162
163
164 switch (relative_addr) {
165
166 /* Address Translation Unit: */
167 case VERDE_ATU_BASE + ATU_IALR0:
168 case VERDE_ATU_BASE + ATU_IATVR0:
169 case VERDE_ATU_BASE + ATU_IALR1:
170 case VERDE_ATU_BASE + ATU_IALR2:
171 case VERDE_ATU_BASE + ATU_IATVR2:
172 case VERDE_ATU_BASE + ATU_OIOWTVR:
173 case VERDE_ATU_BASE + ATU_OMWTVR0:
174 case VERDE_ATU_BASE + ATU_OUMWTVR0:
175 case VERDE_ATU_BASE + ATU_OMWTVR1:
176 case VERDE_ATU_BASE + ATU_OUMWTVR1:
177 /* Ignoring these for now. TODO */
178 break;
179 case VERDE_ATU_BASE + ATU_ATUCR:
180 /* ATU configuration register; ignored for now. TODO */
181 break;
182 case VERDE_ATU_BASE + ATU_PCSR:
183 /* TODO: Temporary hack to allow NetBSD/evbarm to
184 reboot itself. Should be rewritten as soon as possible! */
185 if (writeflag == MEM_WRITE && idata == 0x30) {
186 int j;
187 for (j=0; j<cpu->machine->ncpus; j++)
188 cpu->machine->cpus[j]->running = 0;
189 cpu->machine->exit_without_entering_debugger = 1;
190 }
191 break;
192 case VERDE_ATU_BASE + ATU_ATUIMR:
193 case VERDE_ATU_BASE + ATU_IABAR3:
194 case VERDE_ATU_BASE + ATU_IAUBAR3:
195 case VERDE_ATU_BASE + ATU_IALR3:
196 case VERDE_ATU_BASE + ATU_IATVR3:
197 /* Ignoring these for now. TODO */
198 break;
199 case VERDE_ATU_BASE + ATU_OCCAR:
200 /* PCI address */
201 if (writeflag == MEM_WRITE) {
202 d->pci_addr = idata;
203 bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
204 bus = 0; /* NOTE */
205 bus_pci_setaddr(cpu, d->pci_bus, bus, dev, func, reg);
206 } else {
207 odata = d->pci_addr;
208 }
209 break;
210 case VERDE_ATU_BASE + ATU_OCCDR:
211 case VERDE_ATU_BASE + ATU_OCCDR + 1:
212 case VERDE_ATU_BASE + ATU_OCCDR + 2:
213 case VERDE_ATU_BASE + ATU_OCCDR + 3:
214 /* PCI data */
215 if (writeflag == MEM_READ) {
216 uint64_t tmp;
217 bus_pci_data_access(cpu, d->pci_bus, &tmp,
218 sizeof(uint32_t), MEM_READ);
219 switch (relative_addr) {
220 case VERDE_ATU_BASE + ATU_OCCDR + 1:
221 odata = tmp >> 8; break;
222 case VERDE_ATU_BASE + ATU_OCCDR + 2:
223 odata = tmp >> 16; break;
224 case VERDE_ATU_BASE + ATU_OCCDR + 3:
225 odata = tmp >> 24; break;
226 default:odata = tmp;
227 }
228 } else {
229 uint64_t tmp;
230 unsigned int i;
231 int r = relative_addr - (VERDE_ATU_BASE + ATU_OCCDR);
232 bus_pci_data_access(cpu, d->pci_bus, &tmp,
233 sizeof(uint32_t), MEM_READ);
234 for (i=0; i<len; i++) {
235 uint8_t b = idata >> (i*8);
236 tmp &= ~(0xff << ((r+i)*8));
237 tmp |= b << ((r+i)*8);
238 }
239 tmp &= 0xffffffff; /* needed because << is 32-bit */
240 bus_pci_data_access(cpu, d->pci_bus, &tmp,
241 sizeof(uint32_t), MEM_WRITE);
242 }
243 break;
244 case VERDE_ATU_BASE + ATU_PCIXSR:
245 odata = 0; /* TODO */
246 break;
247
248 /* Memory Controller Unit: */
249 case VERDE_MCU_BASE + MCU_SDBR:
250 n = "MCU_SDBR";
251 break;
252 case VERDE_MCU_BASE + MCU_SBR0:
253 n = "MCU_SBR0";
254 break;
255 case VERDE_MCU_BASE + MCU_SBR1:
256 n = "MCU_SBR1";
257 break;
258
259 default:if (writeflag == MEM_READ) {
260 fatal("[ i80321: read from 0x%x ]\n",
261 (int)relative_addr);
262 } else {
263 fatal("[ i80321: write to 0x%x: 0x%llx ]\n",
264 (int)relative_addr, (long long)idata);
265 }
266 }
267
268 if (n != NULL) {
269 if (writeflag == MEM_READ) {
270 debug("[ i80321: read from %s ]\n", n);
271 } else {
272 debug("[ i80321: write to %s: 0x%llx ]\n",
273 n, (long long)idata);
274 }
275 }
276
277 ret:
278 if (writeflag == MEM_READ)
279 memory_writemax64(cpu, data, len, odata);
280
281 return 1;
282 }
283
284
285 DEVINIT(i80321)
286 {
287 struct i80321_data *d = malloc(sizeof(struct i80321_data));
288 uint32_t memsize = devinit->machine->physical_ram_in_mb * 1048576;
289 uint32_t base;
290 char tmpstr[300];
291 int i;
292 struct cpu *cpu = devinit->machine->cpus[devinit->
293 machine->bootstrap_cpu];
294
295 if (d == NULL) {
296 fprintf(stderr, "out of memory\n");
297 exit(1);
298 }
299 memset(d, 0, sizeof(struct i80321_data));
300
301 /* Connect to the CPU interrupt pin: */
302 INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
303
304 /* Register 32 i80321 interrupts: */
305 for (i=0; i<32; i++) {
306 struct interrupt template;
307 char tmpstr[300];
308 snprintf(tmpstr, sizeof(tmpstr), "%s.i80321.%i",
309 devinit->interrupt_path, i);
310 memset(&template, 0, sizeof(template));
311 template.line = 1 << i;
312 template.name = tmpstr;
313 template.extra = d;
314 template.interrupt_assert = i80321_interrupt_assert;
315 template.interrupt_deassert = i80321_interrupt_deassert;
316 interrupt_handler_register(&template);
317
318 /*
319 * Connect the CPU's TMR0 and TMR1 interrupts to these
320 * i80321 timer interrupts (nr 9 and 10):
321 */
322 if (i == 9)
323 INTERRUPT_CONNECT(tmpstr, cpu->cd.arm.tmr0_irq);
324 if (i == 10)
325 INTERRUPT_CONNECT(tmpstr, cpu->cd.arm.tmr1_irq);
326 }
327
328 d->status = &cpu->cd.arm.i80321_isrc;
329 d->enable = &cpu->cd.arm.i80321_inten;
330
331 d->mcu_reg[MCU_SDBR / sizeof(uint32_t)] = base = 0xa0000000;
332 d->mcu_reg[MCU_SBR0 / sizeof(uint32_t)] = (base + memsize) >> 25;
333 d->mcu_reg[MCU_SBR1 / sizeof(uint32_t)] = (base + memsize) >> 25;
334
335 snprintf(tmpstr, sizeof(tmpstr), "%s.i80321", devinit->interrupt_path);
336
337 d->pci_bus = bus_pci_init(devinit->machine,
338 tmpstr /* pciirq */,
339 0x90000000 /* TODO: pci_io_offset */,
340 0x90010000 /* TODO: pci_mem_offset */,
341 0xffff0000 /* TODO: pci_portbase */,
342 0x00000000 /* TODO: pci_membase */,
343 tmpstr /* pci_irqbase */,
344 0x90000000 /* TODO: isa_portbase */,
345 0x90010000 /* TODO: isa_membase */,
346 "TODO: isa_irqbase" /* TODO: isa_irqbase */);
347
348 memory_device_register(devinit->machine->memory, devinit->name,
349 devinit->addr, DEV_I80321_LENGTH,
350 dev_i80321_access, d, DM_DEFAULT, NULL);
351
352 /* TODO: Don't hardcode to 100 Hz! */
353 d->hz = 100;
354 d->timer = timer_add(d->hz, tmr0_tick, d);
355
356 machine_add_tickfunction(devinit->machine, dev_i80321_tick,
357 d, TICK_SHIFT, 0.0);
358
359 devinit->return_ptr = d->pci_bus;
360
361 return 1;
362 }
363
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