/[gxemul]/trunk/src/devices/dev_i80321.c
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Annotation of /trunk/src/devices/dev_i80321.c

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Revision 42 - (hide annotations)
Mon Oct 8 16:22:32 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 10074 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1613 2007/06/15 20:11:26 debug Exp $
20070501	Continuing a little on m88k disassembly (control registers,
		more instructions).
		Adding a dummy mvme88k machine mode.
20070502	Re-adding MIPS load/store alignment exceptions.
20070503	Implementing more of the M88K disassembly code.
20070504	Adding disassembly of some more M88K load/store instructions.
		Implementing some relatively simple M88K instructions (br.n,
		xor[.u] imm, and[.u] imm).
20070505	Implementing M88K three-register and, or, xor, and jmp[.n],
		bsr[.n] including function call trace stuff.
		Applying a patch from Bruce M. Simpson which implements the
		SYSCON_BOARD_CPU_CLOCK_FREQ_ID object of the syscon call in
		the yamon PROM emulation.
20070506	Implementing M88K bb0[.n] and bb1[.n], and skeletons for
		ldcr and stcr (although no control regs are implemented yet).
20070509	Found and fixed the bug which caused Linux for QEMU_MIPS to
		stop working in 0.4.5.1: It was a faulty change to the MIPS
		'sc' and 'scd' instructions I made while going through gcc -W
		warnings on 20070428.
20070510	Updating the Linux/QEMU_MIPS section in guestoses.html to
		use mips-test-0.2.tar.gz instead of 0.1.
		A big thank you to Miod Vallat for sending me M88K manuals.
		Implementing more M88K instructions (addu, subu, div[u], mulu,
		ext[u], clr, set, cmp).
20070511	Fixing bugs in the M88K "and" and "and.u" instructions (found
		by comparing against the manual).
		Implementing more M88K instructions (mask[.u], mak, bcnd (auto-
		generated)) and some more control register details.
		Cleanup: Removing the experimental AVR emulation mode and
		corresponding devices; AVR emulation wasn't really meaningful.
		Implementing autogeneration of most M88K loads/stores. The
		rectangle drawing demo (with -O0) for M88K runs :-)
		Beginning on M88K exception handling.
		More M88K instructions: tb0, tb1, rte, sub, jsr[.n].
		Adding some skeleton MVME PROM ("BUG") emulation.
20070512	Fixing a bug in the M88K cmp instruction.
		Adding the M88K lda (scaled register) instruction.
		Fixing bugs in 64-bit (32-bit pairs) M88K loads/stores.
		Removing the unused tick_hz stuff from the machine struct.
		Implementing the M88K xmem instruction. OpenBSD/mvme88k gets
		far enough to display the Copyright banner :-)
		Implementing subu.co (guess), addu.co, addu.ci, ff0, and ff1.
		Adding a dev_mvme187, for MVME187-specific devices/registers.
		OpenBSD/mvme88k prints more boot messages. :)
20070515	Continuing on MVME187 emulation (adding more devices, beginning
		on the CMMUs, etc).
		Adding the M88K and.c, xor.c, and or.c instructions, and making
		sure that mul, div, etc cause exceptions if executed when SFD1
		is disabled.
20070517	Continuing on M88K and MVME187 emulation in general; moving
		the CMMU registers to the CPU struct, separating dev_pcc2 from
		dev_mvme187, and beginning on memory_m88k.c (BATC and PATC).
		Fixing a bug in 64-bit (32-bit pairs) M88K fast stores.
		Implementing the clock part of dev_mk48txx.
		Implementing the M88K fstcr and xcr instructions.
		Implementing m88k_cpu_tlbdump().
		Beginning on the implementation of a separate address space
		for M88K .usr loads/stores.
20070520	Removing the non-working (skeleton) Sandpoint, SonyNEWS, SHARK
		Dnard, and Zaurus machine modes.
		Experimenting with dyntrans to_be_translated read-ahead. It
		seems to give a very small performance increase for MIPS
		emulation, but a large performance degradation for SuperH. Hm.
20070522	Disabling correct SuperH ITLB emulation; it does not seem to be
		necessary in order to let SH4 guest OSes run, and it slows down
		userspace code.
		Implementing "samepage" branches for SuperH emulation, and some
		other minor speed hacks.
20070525	Continuing on M88K memory-related stuff: exceptions, memory
		transaction register contents, etc.
		Implementing the M88K subu.ci instruction.
		Removing the non-working (skeleton) Iyonix machine mode.
		OpenBSD/mvme88k reaches userland :-), starts executing
		/sbin/init's instructions, and issues a few syscalls, before
		crashing.
20070526	Fixing bugs in dev_mk48txx, so that OpenBSD/mvme88k detects
		the correct time-of-day.
		Implementing a generic IRQ controller for the test machines
		(dev_irqc), similar to a proposed patch from Petr Stepan.
		Experimenting some more with translation read-ahead.
		Adding an "expect" script for automated OpenBSD/landisk
		install regression/performance tests.
20070527	Adding a dummy mmEye (SH3) machine mode skeleton.
		FINALLY found the strange M88K bug I have been hunting: I had
		not emulated the SNIP value for exceptions occurring in
		branch delay slots correctly.
		Implementing correct exceptions for 64-bit M88K loads/stores.
		Address to symbol lookups are now disabled when M88K is
		running in usermode (because usermode addresses don't have
		anything to do with supervisor addresses).
20070531	Removing the mmEye machine mode skeleton.
20070604	Some minor code cleanup.
20070605	Moving src/useremul.c into a subdir (src/useremul/), and
		cleaning up some more legacy constructs.
		Adding -Wstrict-aliasing and -fstrict-aliasing detection to
		the configure script.
20070606	Adding a check for broken GCC on Solaris to the configure
		script. (GCC 3.4.3 on Solaris cannot handle static variables
		which are initialized to 0 or NULL. :-/)
		Removing the old (non-working) ARC emulation modes: NEC RD94,
		R94, R96, and R98, and the last traces of Olivetti M700 and
		Deskstation Tyne.
		Removing the non-working skeleton WDSC device (dev_wdsc).
20070607	Thinking about how to use the host's cc + ld at runtime to
		generate native code. (See experiments/native_cc_ld_test.i
		for an example.)
20070608	Adding a program counter sampling timer, which could be useful
		for native code generation experiments.
		The KN02_CSR_NRMMOD bit in the DECstation 5000/200 (KN02) CSR
		should always be set, to allow a 5000/200 PROM to boot.
20070609	Moving out breakpoint details from the machine struct into
		a helper struct, and removing the limit on max nr of
		breakpoints.
20070610	Moving out tick functions into a helper struct as well (which
		also gets rid of the max limit).
20070612	FINALLY figured out why Debian/DECstation stopped working when
		translation read-ahead was enabled: in src/memory_rw.c, the
		call to invalidate_code_translation was made also if the
		memory access was an instruction load (if the page was mapped
		as writable); it shouldn't be called in that case.
20070613	Implementing some more MIPS32/64 revision 2 instructions: di,
		ei, ext, dext, dextm, dextu, and ins.
20070614	Implementing an instruction combination for the NetBSD/arm
		idle loop (making the host not use any cpu if NetBSD/arm
		inside the emulator is not using any cpu).
		Increasing the nr of ARM VPH entries from 128 to 384.
20070615	Removing the ENABLE_arch stuff from the configure script, so
		that all included architectures are included in both release
		and development builds.
		Moving memory related helper functions from misc.c to memory.c.
		Adding preliminary instructions for netbooting NetBSD/pmppc to
		guestoses.html; it doesn't work yet, there are weird timeouts.
		Beginning a total rewrite of the userland emulation modes
		(removing all emulation modes, beginning from scratch with
		NetBSD/MIPS and FreeBSD/Alpha only).
20070616	After fixing a bug in the DEC21143 NIC (the TDSTAT_OWN bit was
		only cleared for the last segment when transmitting, not all
		segments), NetBSD/pmppc boots with root-on-nfs without the
		timeouts. Updating guestoses.html.
		Removing the skeleton PSP (Playstation Portable) mode.
		Moving X11-related stuff in the machine struct into a helper
		struct.
		Cleanup of out-of-memory checks, to use a new CHECK_ALLOCATION
		macro (which prints a meaningful error message).
		Adding a COMMENT to each machine and device (for automagic
		.index comment generation).
		Doing regression testing for the next release.

==============  RELEASE 0.4.6  ==============
1 dpavlin 18 /*
2 dpavlin 34 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 dpavlin 18 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 42 * $Id: dev_i80321.c,v 1.23 2007/06/15 19:11:15 debug Exp $
29 dpavlin 18 *
30 dpavlin 42 * COMMENT: Intel i80321 (ARM) core functionality
31 dpavlin 22 *
32 dpavlin 34 * o) Interrupt controller
33     * o) Timer
34     * o) PCI controller
35     * o) Memory controller
36     *
37     * TODO:
38     * o) LOTS of things left to implement.
39     * o) This is hardcoded for little endian emulation.
40 dpavlin 18 */
41    
42     #include <stdio.h>
43     #include <stdlib.h>
44     #include <string.h>
45    
46 dpavlin 22 #include "bus_pci.h"
47 dpavlin 18 #include "cpu.h"
48     #include "device.h"
49     #include "machine.h"
50     #include "memory.h"
51     #include "misc.h"
52 dpavlin 34 #include "timer.h"
53 dpavlin 18
54    
55     #include "i80321reg.h"
56    
57 dpavlin 34 #define TICK_SHIFT 15
58 dpavlin 22 #define DEV_I80321_LENGTH VERDE_PMMR_SIZE
59 dpavlin 18
60 dpavlin 34 struct i80321_data {
61     /* Interrupt Controller */
62     struct interrupt irq;
63     uint32_t *status; /* Note: these point to i80321_isrc */
64     uint32_t *enable; /* and i80321_inten in the CPU! */
65 dpavlin 18
66 dpavlin 34 /* Timer: */
67     struct timer *timer;
68     double hz;
69     int pending_tmr0_interrupts;
70    
71     /* PCI Controller: */
72     uint32_t pci_addr;
73     struct pci_data *pci_bus;
74    
75     /* Memory Controller: */
76     uint32_t mcu_reg[0x100 / sizeof(uint32_t)];
77     };
78    
79    
80     static void i80321_assert(struct i80321_data *d, uint32_t linemask)
81 dpavlin 22 {
82 dpavlin 34 *d->status |= linemask;
83     if (*d->status & *d->enable)
84     INTERRUPT_ASSERT(d->irq);
85     }
86     static void i80321_deassert(struct i80321_data *d, uint32_t linemask)
87     {
88     *d->status &= ~linemask;
89     if (!(*d->status & *d->enable))
90     INTERRUPT_DEASSERT(d->irq);
91     }
92 dpavlin 18
93 dpavlin 22
94 dpavlin 34 /*
95     * i80321_interrupt_assert():
96     * i80321_interrupt_deassert():
97     *
98     * Called whenever an i80321 interrupt is asserted/deasserted.
99     */
100     void i80321_interrupt_assert(struct interrupt *interrupt)
101     { i80321_assert(interrupt->extra, interrupt->line); }
102     void i80321_interrupt_deassert(struct interrupt *interrupt)
103     {
104     struct i80321_data *d = interrupt->extra;
105    
106     /* Ack. timer interrupts: */
107     if (interrupt->line == 1 << 9 &&
108     d->pending_tmr0_interrupts > 0)
109     d->pending_tmr0_interrupts --;
110    
111     i80321_deassert(d, interrupt->line);
112     }
113    
114    
115     /* TMR0 ticks, called d->hz times per second. */
116     static void tmr0_tick(struct timer *t, void *extra)
117     {
118     struct i80321_data *d = extra;
119     d->pending_tmr0_interrupts ++;
120     }
121    
122    
123     DEVICE_TICK(i80321)
124     {
125     struct i80321_data *d = extra;
126    
127     if (cpu->cd.arm.tmr0 & TMRx_ENABLE && d->pending_tmr0_interrupts > 0) {
128     i80321_assert(d, 1 << 9);
129 dpavlin 22 cpu->cd.arm.tisr |= TISR_TMR0;
130     } else {
131 dpavlin 34 i80321_deassert(d, 1 << 9);
132 dpavlin 22 cpu->cd.arm.tisr &= ~TISR_TMR0;
133     }
134     }
135    
136    
137     DEVICE_ACCESS(i80321)
138 dpavlin 18 {
139     struct i80321_data *d = extra;
140     uint64_t idata = 0, odata = 0;
141     char *n = NULL;
142 dpavlin 40 int bus, dev, func, reg;
143 dpavlin 18
144     if (writeflag == MEM_WRITE)
145     idata = memory_readmax64(cpu, data, len);
146    
147 dpavlin 22 /* PCI configuration space: */
148     if (relative_addr >= 0x100 && relative_addr < 0x140) {
149     /* TODO */
150     goto ret;
151     }
152    
153     /* MCU registers: */
154 dpavlin 18 if (relative_addr >= VERDE_MCU_BASE &&
155     relative_addr < VERDE_MCU_BASE + VERDE_MCU_SIZE) {
156     int regnr = (relative_addr - VERDE_MCU_BASE) / sizeof(uint32_t);
157     if (writeflag == MEM_WRITE)
158     d->mcu_reg[regnr] = idata;
159     else
160     odata = d->mcu_reg[regnr];
161     }
162    
163 dpavlin 22
164 dpavlin 18 switch (relative_addr) {
165    
166 dpavlin 22 /* Address Translation Unit: */
167     case VERDE_ATU_BASE + ATU_IALR0:
168     case VERDE_ATU_BASE + ATU_IATVR0:
169     case VERDE_ATU_BASE + ATU_IALR1:
170     case VERDE_ATU_BASE + ATU_IALR2:
171     case VERDE_ATU_BASE + ATU_IATVR2:
172     case VERDE_ATU_BASE + ATU_OIOWTVR:
173     case VERDE_ATU_BASE + ATU_OMWTVR0:
174     case VERDE_ATU_BASE + ATU_OUMWTVR0:
175     case VERDE_ATU_BASE + ATU_OMWTVR1:
176     case VERDE_ATU_BASE + ATU_OUMWTVR1:
177     /* Ignoring these for now. TODO */
178     break;
179     case VERDE_ATU_BASE + ATU_ATUCR:
180     /* ATU configuration register; ignored for now. TODO */
181     break;
182     case VERDE_ATU_BASE + ATU_PCSR:
183     /* TODO: Temporary hack to allow NetBSD/evbarm to
184     reboot itself. Should be rewritten as soon as possible! */
185     if (writeflag == MEM_WRITE && idata == 0x30) {
186     int j;
187     for (j=0; j<cpu->machine->ncpus; j++)
188     cpu->machine->cpus[j]->running = 0;
189     cpu->machine->exit_without_entering_debugger = 1;
190     }
191     break;
192     case VERDE_ATU_BASE + ATU_ATUIMR:
193     case VERDE_ATU_BASE + ATU_IABAR3:
194     case VERDE_ATU_BASE + ATU_IAUBAR3:
195     case VERDE_ATU_BASE + ATU_IALR3:
196     case VERDE_ATU_BASE + ATU_IATVR3:
197     /* Ignoring these for now. TODO */
198     break;
199     case VERDE_ATU_BASE + ATU_OCCAR:
200     /* PCI address */
201     if (writeflag == MEM_WRITE) {
202     d->pci_addr = idata;
203     bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
204     bus = 0; /* NOTE */
205     bus_pci_setaddr(cpu, d->pci_bus, bus, dev, func, reg);
206     } else {
207     odata = d->pci_addr;
208     }
209     break;
210     case VERDE_ATU_BASE + ATU_OCCDR:
211     case VERDE_ATU_BASE + ATU_OCCDR + 1:
212     case VERDE_ATU_BASE + ATU_OCCDR + 2:
213     case VERDE_ATU_BASE + ATU_OCCDR + 3:
214     /* PCI data */
215     if (writeflag == MEM_READ) {
216     uint64_t tmp;
217     bus_pci_data_access(cpu, d->pci_bus, &tmp,
218     sizeof(uint32_t), MEM_READ);
219     switch (relative_addr) {
220     case VERDE_ATU_BASE + ATU_OCCDR + 1:
221     odata = tmp >> 8; break;
222     case VERDE_ATU_BASE + ATU_OCCDR + 2:
223     odata = tmp >> 16; break;
224     case VERDE_ATU_BASE + ATU_OCCDR + 3:
225     odata = tmp >> 24; break;
226     default:odata = tmp;
227     }
228     } else {
229     uint64_t tmp;
230 dpavlin 40 unsigned int i;
231 dpavlin 22 int r = relative_addr - (VERDE_ATU_BASE + ATU_OCCDR);
232     bus_pci_data_access(cpu, d->pci_bus, &tmp,
233     sizeof(uint32_t), MEM_READ);
234     for (i=0; i<len; i++) {
235     uint8_t b = idata >> (i*8);
236     tmp &= ~(0xff << ((r+i)*8));
237     tmp |= b << ((r+i)*8);
238     }
239     tmp &= 0xffffffff; /* needed because << is 32-bit */
240     bus_pci_data_access(cpu, d->pci_bus, &tmp,
241     sizeof(uint32_t), MEM_WRITE);
242     }
243     break;
244     case VERDE_ATU_BASE + ATU_PCIXSR:
245     odata = 0; /* TODO */
246     break;
247    
248     /* Memory Controller Unit: */
249 dpavlin 18 case VERDE_MCU_BASE + MCU_SDBR:
250     n = "MCU_SDBR";
251     break;
252     case VERDE_MCU_BASE + MCU_SBR0:
253     n = "MCU_SBR0";
254     break;
255     case VERDE_MCU_BASE + MCU_SBR1:
256     n = "MCU_SBR1";
257     break;
258    
259     default:if (writeflag == MEM_READ) {
260     fatal("[ i80321: read from 0x%x ]\n",
261     (int)relative_addr);
262     } else {
263     fatal("[ i80321: write to 0x%x: 0x%llx ]\n",
264     (int)relative_addr, (long long)idata);
265     }
266     }
267    
268     if (n != NULL) {
269     if (writeflag == MEM_READ) {
270     debug("[ i80321: read from %s ]\n", n);
271     } else {
272     debug("[ i80321: write to %s: 0x%llx ]\n",
273     n, (long long)idata);
274     }
275     }
276    
277 dpavlin 22 ret:
278 dpavlin 18 if (writeflag == MEM_READ)
279     memory_writemax64(cpu, data, len, odata);
280    
281     return 1;
282     }
283    
284    
285 dpavlin 22 DEVINIT(i80321)
286 dpavlin 18 {
287 dpavlin 42 struct i80321_data *d;
288 dpavlin 18 uint32_t memsize = devinit->machine->physical_ram_in_mb * 1048576;
289     uint32_t base;
290 dpavlin 34 char tmpstr[300];
291     struct cpu *cpu = devinit->machine->cpus[devinit->
292     machine->bootstrap_cpu];
293 dpavlin 42 int i;
294 dpavlin 18
295 dpavlin 42 CHECK_ALLOCATION(d = malloc(sizeof(struct i80321_data)));
296 dpavlin 18 memset(d, 0, sizeof(struct i80321_data));
297    
298 dpavlin 34 /* Connect to the CPU interrupt pin: */
299     INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
300    
301     /* Register 32 i80321 interrupts: */
302     for (i=0; i<32; i++) {
303     struct interrupt template;
304     char tmpstr[300];
305     snprintf(tmpstr, sizeof(tmpstr), "%s.i80321.%i",
306     devinit->interrupt_path, i);
307     memset(&template, 0, sizeof(template));
308     template.line = 1 << i;
309     template.name = tmpstr;
310     template.extra = d;
311     template.interrupt_assert = i80321_interrupt_assert;
312     template.interrupt_deassert = i80321_interrupt_deassert;
313     interrupt_handler_register(&template);
314    
315     /*
316     * Connect the CPU's TMR0 and TMR1 interrupts to these
317     * i80321 timer interrupts (nr 9 and 10):
318     */
319     if (i == 9)
320     INTERRUPT_CONNECT(tmpstr, cpu->cd.arm.tmr0_irq);
321     if (i == 10)
322     INTERRUPT_CONNECT(tmpstr, cpu->cd.arm.tmr1_irq);
323     }
324    
325     d->status = &cpu->cd.arm.i80321_isrc;
326     d->enable = &cpu->cd.arm.i80321_inten;
327    
328 dpavlin 18 d->mcu_reg[MCU_SDBR / sizeof(uint32_t)] = base = 0xa0000000;
329 dpavlin 22 d->mcu_reg[MCU_SBR0 / sizeof(uint32_t)] = (base + memsize) >> 25;
330     d->mcu_reg[MCU_SBR1 / sizeof(uint32_t)] = (base + memsize) >> 25;
331 dpavlin 18
332 dpavlin 34 snprintf(tmpstr, sizeof(tmpstr), "%s.i80321", devinit->interrupt_path);
333    
334 dpavlin 22 d->pci_bus = bus_pci_init(devinit->machine,
335 dpavlin 34 tmpstr /* pciirq */,
336     0x90000000 /* TODO: pci_io_offset */,
337     0x90010000 /* TODO: pci_mem_offset */,
338     0xffff0000 /* TODO: pci_portbase */,
339     0x00000000 /* TODO: pci_membase */,
340     tmpstr /* pci_irqbase */,
341     0x90000000 /* TODO: isa_portbase */,
342     0x90010000 /* TODO: isa_membase */,
343     "TODO: isa_irqbase" /* TODO: isa_irqbase */);
344 dpavlin 22
345 dpavlin 18 memory_device_register(devinit->machine->memory, devinit->name,
346     devinit->addr, DEV_I80321_LENGTH,
347 dpavlin 20 dev_i80321_access, d, DM_DEFAULT, NULL);
348 dpavlin 18
349 dpavlin 34 /* TODO: Don't hardcode to 100 Hz! */
350     d->hz = 100;
351     d->timer = timer_add(d->hz, tmr0_tick, d);
352    
353 dpavlin 22 machine_add_tickfunction(devinit->machine, dev_i80321_tick,
354 dpavlin 42 d, TICK_SHIFT);
355 dpavlin 22
356 dpavlin 34 devinit->return_ptr = d->pci_bus;
357 dpavlin 22
358 dpavlin 18 return 1;
359     }
360    
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