/[gxemul]/trunk/src/devices/dev_i80321.c
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Contents of /trunk/src/devices/dev_i80321.c

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Revision 34 - (show annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 10103 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============
1 /*
2 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_i80321.c,v 1.20 2007/02/05 16:49:21 debug Exp $
29 *
30 * Intel i80321 (ARM) core functionality.
31 *
32 * o) Interrupt controller
33 * o) Timer
34 * o) PCI controller
35 * o) Memory controller
36 *
37 * TODO:
38 * o) LOTS of things left to implement.
39 * o) This is hardcoded for little endian emulation.
40 */
41
42 #include <stdio.h>
43 #include <stdlib.h>
44 #include <string.h>
45
46 #include "bus_pci.h"
47 #include "cpu.h"
48 #include "device.h"
49 #include "machine.h"
50 #include "memory.h"
51 #include "misc.h"
52 #include "timer.h"
53
54
55 #include "i80321reg.h"
56
57 #define TICK_SHIFT 15
58 #define DEV_I80321_LENGTH VERDE_PMMR_SIZE
59
60 struct i80321_data {
61 /* Interrupt Controller */
62 struct interrupt irq;
63 uint32_t *status; /* Note: these point to i80321_isrc */
64 uint32_t *enable; /* and i80321_inten in the CPU! */
65
66 /* Timer: */
67 struct timer *timer;
68 double hz;
69 int pending_tmr0_interrupts;
70
71 /* PCI Controller: */
72 uint32_t pci_addr;
73 struct pci_data *pci_bus;
74
75 /* Memory Controller: */
76 uint32_t mcu_reg[0x100 / sizeof(uint32_t)];
77 };
78
79
80 static void i80321_assert(struct i80321_data *d, uint32_t linemask)
81 {
82 *d->status |= linemask;
83 if (*d->status & *d->enable)
84 INTERRUPT_ASSERT(d->irq);
85 }
86 static void i80321_deassert(struct i80321_data *d, uint32_t linemask)
87 {
88 *d->status &= ~linemask;
89 if (!(*d->status & *d->enable))
90 INTERRUPT_DEASSERT(d->irq);
91 }
92
93
94 /*
95 * i80321_interrupt_assert():
96 * i80321_interrupt_deassert():
97 *
98 * Called whenever an i80321 interrupt is asserted/deasserted.
99 */
100 void i80321_interrupt_assert(struct interrupt *interrupt)
101 { i80321_assert(interrupt->extra, interrupt->line); }
102 void i80321_interrupt_deassert(struct interrupt *interrupt)
103 {
104 struct i80321_data *d = interrupt->extra;
105
106 /* Ack. timer interrupts: */
107 if (interrupt->line == 1 << 9 &&
108 d->pending_tmr0_interrupts > 0)
109 d->pending_tmr0_interrupts --;
110
111 i80321_deassert(d, interrupt->line);
112 }
113
114
115 /* TMR0 ticks, called d->hz times per second. */
116 static void tmr0_tick(struct timer *t, void *extra)
117 {
118 struct i80321_data *d = extra;
119 d->pending_tmr0_interrupts ++;
120 }
121
122
123 DEVICE_TICK(i80321)
124 {
125 struct i80321_data *d = extra;
126
127 if (cpu->cd.arm.tmr0 & TMRx_ENABLE && d->pending_tmr0_interrupts > 0) {
128 i80321_assert(d, 1 << 9);
129 cpu->cd.arm.tisr |= TISR_TMR0;
130 } else {
131 i80321_deassert(d, 1 << 9);
132 cpu->cd.arm.tisr &= ~TISR_TMR0;
133 }
134 }
135
136
137 DEVICE_ACCESS(i80321)
138 {
139 struct i80321_data *d = extra;
140 uint64_t idata = 0, odata = 0;
141 char *n = NULL;
142 int i, bus, dev, func, reg;
143
144 if (writeflag == MEM_WRITE)
145 idata = memory_readmax64(cpu, data, len);
146
147 /* PCI configuration space: */
148 if (relative_addr >= 0x100 && relative_addr < 0x140) {
149 /* TODO */
150 goto ret;
151 }
152
153 /* MCU registers: */
154 if (relative_addr >= VERDE_MCU_BASE &&
155 relative_addr < VERDE_MCU_BASE + VERDE_MCU_SIZE) {
156 int regnr = (relative_addr - VERDE_MCU_BASE) / sizeof(uint32_t);
157 if (writeflag == MEM_WRITE)
158 d->mcu_reg[regnr] = idata;
159 else
160 odata = d->mcu_reg[regnr];
161 }
162
163
164 switch (relative_addr) {
165
166 /* Address Translation Unit: */
167 case VERDE_ATU_BASE + ATU_IALR0:
168 case VERDE_ATU_BASE + ATU_IATVR0:
169 case VERDE_ATU_BASE + ATU_IALR1:
170 case VERDE_ATU_BASE + ATU_IALR2:
171 case VERDE_ATU_BASE + ATU_IATVR2:
172 case VERDE_ATU_BASE + ATU_OIOWTVR:
173 case VERDE_ATU_BASE + ATU_OMWTVR0:
174 case VERDE_ATU_BASE + ATU_OUMWTVR0:
175 case VERDE_ATU_BASE + ATU_OMWTVR1:
176 case VERDE_ATU_BASE + ATU_OUMWTVR1:
177 /* Ignoring these for now. TODO */
178 break;
179 case VERDE_ATU_BASE + ATU_ATUCR:
180 /* ATU configuration register; ignored for now. TODO */
181 break;
182 case VERDE_ATU_BASE + ATU_PCSR:
183 /* TODO: Temporary hack to allow NetBSD/evbarm to
184 reboot itself. Should be rewritten as soon as possible! */
185 if (writeflag == MEM_WRITE && idata == 0x30) {
186 int j;
187 for (j=0; j<cpu->machine->ncpus; j++)
188 cpu->machine->cpus[j]->running = 0;
189 cpu->machine->exit_without_entering_debugger = 1;
190 }
191 break;
192 case VERDE_ATU_BASE + ATU_ATUIMR:
193 case VERDE_ATU_BASE + ATU_IABAR3:
194 case VERDE_ATU_BASE + ATU_IAUBAR3:
195 case VERDE_ATU_BASE + ATU_IALR3:
196 case VERDE_ATU_BASE + ATU_IATVR3:
197 /* Ignoring these for now. TODO */
198 break;
199 case VERDE_ATU_BASE + ATU_OCCAR:
200 /* PCI address */
201 if (writeflag == MEM_WRITE) {
202 d->pci_addr = idata;
203 bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
204 bus = 0; /* NOTE */
205 bus_pci_setaddr(cpu, d->pci_bus, bus, dev, func, reg);
206 } else {
207 odata = d->pci_addr;
208 }
209 break;
210 case VERDE_ATU_BASE + ATU_OCCDR:
211 case VERDE_ATU_BASE + ATU_OCCDR + 1:
212 case VERDE_ATU_BASE + ATU_OCCDR + 2:
213 case VERDE_ATU_BASE + ATU_OCCDR + 3:
214 /* PCI data */
215 if (writeflag == MEM_READ) {
216 uint64_t tmp;
217 bus_pci_data_access(cpu, d->pci_bus, &tmp,
218 sizeof(uint32_t), MEM_READ);
219 switch (relative_addr) {
220 case VERDE_ATU_BASE + ATU_OCCDR + 1:
221 odata = tmp >> 8; break;
222 case VERDE_ATU_BASE + ATU_OCCDR + 2:
223 odata = tmp >> 16; break;
224 case VERDE_ATU_BASE + ATU_OCCDR + 3:
225 odata = tmp >> 24; break;
226 default:odata = tmp;
227 }
228 } else {
229 uint64_t tmp;
230 int r = relative_addr - (VERDE_ATU_BASE + ATU_OCCDR);
231 bus_pci_data_access(cpu, d->pci_bus, &tmp,
232 sizeof(uint32_t), MEM_READ);
233 for (i=0; i<len; i++) {
234 uint8_t b = idata >> (i*8);
235 tmp &= ~(0xff << ((r+i)*8));
236 tmp |= b << ((r+i)*8);
237 }
238 tmp &= 0xffffffff; /* needed because << is 32-bit */
239 bus_pci_data_access(cpu, d->pci_bus, &tmp,
240 sizeof(uint32_t), MEM_WRITE);
241 }
242 break;
243 case VERDE_ATU_BASE + ATU_PCIXSR:
244 odata = 0; /* TODO */
245 break;
246
247 /* Memory Controller Unit: */
248 case VERDE_MCU_BASE + MCU_SDBR:
249 n = "MCU_SDBR";
250 break;
251 case VERDE_MCU_BASE + MCU_SBR0:
252 n = "MCU_SBR0";
253 break;
254 case VERDE_MCU_BASE + MCU_SBR1:
255 n = "MCU_SBR1";
256 break;
257
258 default:if (writeflag == MEM_READ) {
259 fatal("[ i80321: read from 0x%x ]\n",
260 (int)relative_addr);
261 } else {
262 fatal("[ i80321: write to 0x%x: 0x%llx ]\n",
263 (int)relative_addr, (long long)idata);
264 }
265 }
266
267 if (n != NULL) {
268 if (writeflag == MEM_READ) {
269 debug("[ i80321: read from %s ]\n", n);
270 } else {
271 debug("[ i80321: write to %s: 0x%llx ]\n",
272 n, (long long)idata);
273 }
274 }
275
276 ret:
277 if (writeflag == MEM_READ)
278 memory_writemax64(cpu, data, len, odata);
279
280 return 1;
281 }
282
283
284 DEVINIT(i80321)
285 {
286 struct i80321_data *d = malloc(sizeof(struct i80321_data));
287 uint32_t memsize = devinit->machine->physical_ram_in_mb * 1048576;
288 uint32_t base;
289 char tmpstr[300];
290 int i;
291 struct cpu *cpu = devinit->machine->cpus[devinit->
292 machine->bootstrap_cpu];
293
294 if (d == NULL) {
295 fprintf(stderr, "out of memory\n");
296 exit(1);
297 }
298 memset(d, 0, sizeof(struct i80321_data));
299
300 /* Connect to the CPU interrupt pin: */
301 INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
302
303 /* Register 32 i80321 interrupts: */
304 for (i=0; i<32; i++) {
305 struct interrupt template;
306 char tmpstr[300];
307 snprintf(tmpstr, sizeof(tmpstr), "%s.i80321.%i",
308 devinit->interrupt_path, i);
309 memset(&template, 0, sizeof(template));
310 template.line = 1 << i;
311 template.name = tmpstr;
312 template.extra = d;
313 template.interrupt_assert = i80321_interrupt_assert;
314 template.interrupt_deassert = i80321_interrupt_deassert;
315 interrupt_handler_register(&template);
316
317 /*
318 * Connect the CPU's TMR0 and TMR1 interrupts to these
319 * i80321 timer interrupts (nr 9 and 10):
320 */
321 if (i == 9)
322 INTERRUPT_CONNECT(tmpstr, cpu->cd.arm.tmr0_irq);
323 if (i == 10)
324 INTERRUPT_CONNECT(tmpstr, cpu->cd.arm.tmr1_irq);
325 }
326
327 d->status = &cpu->cd.arm.i80321_isrc;
328 d->enable = &cpu->cd.arm.i80321_inten;
329
330 d->mcu_reg[MCU_SDBR / sizeof(uint32_t)] = base = 0xa0000000;
331 d->mcu_reg[MCU_SBR0 / sizeof(uint32_t)] = (base + memsize) >> 25;
332 d->mcu_reg[MCU_SBR1 / sizeof(uint32_t)] = (base + memsize) >> 25;
333
334 snprintf(tmpstr, sizeof(tmpstr), "%s.i80321", devinit->interrupt_path);
335
336 d->pci_bus = bus_pci_init(devinit->machine,
337 tmpstr /* pciirq */,
338 0x90000000 /* TODO: pci_io_offset */,
339 0x90010000 /* TODO: pci_mem_offset */,
340 0xffff0000 /* TODO: pci_portbase */,
341 0x00000000 /* TODO: pci_membase */,
342 tmpstr /* pci_irqbase */,
343 0x90000000 /* TODO: isa_portbase */,
344 0x90010000 /* TODO: isa_membase */,
345 "TODO: isa_irqbase" /* TODO: isa_irqbase */);
346
347 memory_device_register(devinit->machine->memory, devinit->name,
348 devinit->addr, DEV_I80321_LENGTH,
349 dev_i80321_access, d, DM_DEFAULT, NULL);
350
351 /* TODO: Don't hardcode to 100 Hz! */
352 d->hz = 100;
353 d->timer = timer_add(d->hz, tmr0_tick, d);
354
355 machine_add_tickfunction(devinit->machine, dev_i80321_tick,
356 d, TICK_SHIFT, 0.0);
357
358 devinit->return_ptr = d->pci_bus;
359
360 return 1;
361 }
362
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