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/* |
/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: dev_i80321.c,v 1.14 2006/02/18 17:55:25 debug Exp $ |
* $Id: dev_i80321.c,v 1.21 2007/04/28 09:19:52 debug Exp $ |
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* |
* |
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* Intel i80321 (ARM) core functionality. |
* Intel i80321 (ARM) core functionality. |
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* |
* |
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* TODO: This is mostly just a dummy device. |
* o) Interrupt controller |
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* TODO 2: This is hardcoded for little endian emulation. |
* o) Timer |
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* o) PCI controller |
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* o) Memory controller |
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* |
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* TODO: |
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* o) LOTS of things left to implement. |
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* o) This is hardcoded for little endian emulation. |
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*/ |
*/ |
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#include <stdio.h> |
#include <stdio.h> |
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#include "bus_pci.h" |
#include "bus_pci.h" |
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#include "cpu.h" |
#include "cpu.h" |
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#include "device.h" |
#include "device.h" |
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#include "devices.h" |
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#include "machine.h" |
#include "machine.h" |
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#include "memory.h" |
#include "memory.h" |
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#include "misc.h" |
#include "misc.h" |
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#include "timer.h" |
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#include "i80321reg.h" |
#include "i80321reg.h" |
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#define TICK_SHIFT 20 |
#define TICK_SHIFT 15 |
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#define DEV_I80321_LENGTH VERDE_PMMR_SIZE |
#define DEV_I80321_LENGTH VERDE_PMMR_SIZE |
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struct i80321_data { |
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/* Interrupt Controller */ |
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struct interrupt irq; |
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uint32_t *status; /* Note: these point to i80321_isrc */ |
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uint32_t *enable; /* and i80321_inten in the CPU! */ |
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/* Timer: */ |
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struct timer *timer; |
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double hz; |
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int pending_tmr0_interrupts; |
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/* PCI Controller: */ |
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uint32_t pci_addr; |
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struct pci_data *pci_bus; |
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/* Memory Controller: */ |
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uint32_t mcu_reg[0x100 / sizeof(uint32_t)]; |
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}; |
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void dev_i80321_tick(struct cpu *cpu, void *extra) |
static void i80321_assert(struct i80321_data *d, uint32_t linemask) |
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{ |
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*d->status |= linemask; |
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if (*d->status & *d->enable) |
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INTERRUPT_ASSERT(d->irq); |
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} |
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static void i80321_deassert(struct i80321_data *d, uint32_t linemask) |
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{ |
{ |
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/* struct i80321_data *d = extra; */ |
*d->status &= ~linemask; |
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int do_timer_interrupt = 0; |
if (!(*d->status & *d->enable)) |
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INTERRUPT_DEASSERT(d->irq); |
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} |
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/* |
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* i80321_interrupt_assert(): |
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* i80321_interrupt_deassert(): |
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* |
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* Called whenever an i80321 interrupt is asserted/deasserted. |
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*/ |
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void i80321_interrupt_assert(struct interrupt *interrupt) |
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{ i80321_assert(interrupt->extra, interrupt->line); } |
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void i80321_interrupt_deassert(struct interrupt *interrupt) |
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{ |
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struct i80321_data *d = interrupt->extra; |
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/* Ack. timer interrupts: */ |
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if (interrupt->line == 1 << 9 && |
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d->pending_tmr0_interrupts > 0) |
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d->pending_tmr0_interrupts --; |
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i80321_deassert(d, interrupt->line); |
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} |
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if (cpu->cd.arm.tmr0 & TMRx_ENABLE) { |
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do_timer_interrupt = 1; |
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} |
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if (do_timer_interrupt) { |
/* TMR0 ticks, called d->hz times per second. */ |
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cpu_interrupt(cpu, 9); |
static void tmr0_tick(struct timer *t, void *extra) |
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{ |
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struct i80321_data *d = extra; |
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d->pending_tmr0_interrupts ++; |
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} |
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DEVICE_TICK(i80321) |
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{ |
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struct i80321_data *d = extra; |
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if (cpu->cd.arm.tmr0 & TMRx_ENABLE && d->pending_tmr0_interrupts > 0) { |
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i80321_assert(d, 1 << 9); |
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cpu->cd.arm.tisr |= TISR_TMR0; |
cpu->cd.arm.tisr |= TISR_TMR0; |
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} else { |
} else { |
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cpu_interrupt_ack(cpu, 9); |
i80321_deassert(d, 1 << 9); |
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cpu->cd.arm.tisr &= ~TISR_TMR0; |
cpu->cd.arm.tisr &= ~TISR_TMR0; |
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} |
} |
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} |
} |
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struct i80321_data *d = extra; |
struct i80321_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
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char *n = NULL; |
char *n = NULL; |
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int i, bus, dev, func, reg; |
int bus, dev, func, reg; |
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if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
idata = memory_readmax64(cpu, data, len); |
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} |
} |
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} else { |
} else { |
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uint64_t tmp; |
uint64_t tmp; |
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unsigned int i; |
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int r = relative_addr - (VERDE_ATU_BASE + ATU_OCCDR); |
int r = relative_addr - (VERDE_ATU_BASE + ATU_OCCDR); |
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bus_pci_data_access(cpu, d->pci_bus, &tmp, |
bus_pci_data_access(cpu, d->pci_bus, &tmp, |
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sizeof(uint32_t), MEM_READ); |
sizeof(uint32_t), MEM_READ); |
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struct i80321_data *d = malloc(sizeof(struct i80321_data)); |
struct i80321_data *d = malloc(sizeof(struct i80321_data)); |
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uint32_t memsize = devinit->machine->physical_ram_in_mb * 1048576; |
uint32_t memsize = devinit->machine->physical_ram_in_mb * 1048576; |
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uint32_t base; |
uint32_t base; |
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char tmpstr[300]; |
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int i; |
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struct cpu *cpu = devinit->machine->cpus[devinit-> |
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machine->bootstrap_cpu]; |
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if (d == NULL) { |
if (d == NULL) { |
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fprintf(stderr, "out of memory\n"); |
fprintf(stderr, "out of memory\n"); |
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} |
} |
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memset(d, 0, sizeof(struct i80321_data)); |
memset(d, 0, sizeof(struct i80321_data)); |
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/* Connect to the CPU interrupt pin: */ |
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INTERRUPT_CONNECT(devinit->interrupt_path, d->irq); |
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/* Register 32 i80321 interrupts: */ |
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for (i=0; i<32; i++) { |
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struct interrupt template; |
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char tmpstr[300]; |
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snprintf(tmpstr, sizeof(tmpstr), "%s.i80321.%i", |
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devinit->interrupt_path, i); |
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memset(&template, 0, sizeof(template)); |
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template.line = 1 << i; |
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template.name = tmpstr; |
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template.extra = d; |
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template.interrupt_assert = i80321_interrupt_assert; |
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template.interrupt_deassert = i80321_interrupt_deassert; |
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interrupt_handler_register(&template); |
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/* |
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* Connect the CPU's TMR0 and TMR1 interrupts to these |
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* i80321 timer interrupts (nr 9 and 10): |
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*/ |
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if (i == 9) |
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INTERRUPT_CONNECT(tmpstr, cpu->cd.arm.tmr0_irq); |
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if (i == 10) |
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INTERRUPT_CONNECT(tmpstr, cpu->cd.arm.tmr1_irq); |
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} |
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d->status = &cpu->cd.arm.i80321_isrc; |
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d->enable = &cpu->cd.arm.i80321_inten; |
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d->mcu_reg[MCU_SDBR / sizeof(uint32_t)] = base = 0xa0000000; |
d->mcu_reg[MCU_SDBR / sizeof(uint32_t)] = base = 0xa0000000; |
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d->mcu_reg[MCU_SBR0 / sizeof(uint32_t)] = (base + memsize) >> 25; |
d->mcu_reg[MCU_SBR0 / sizeof(uint32_t)] = (base + memsize) >> 25; |
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d->mcu_reg[MCU_SBR1 / sizeof(uint32_t)] = (base + memsize) >> 25; |
d->mcu_reg[MCU_SBR1 / sizeof(uint32_t)] = (base + memsize) >> 25; |
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snprintf(tmpstr, sizeof(tmpstr), "%s.i80321", devinit->interrupt_path); |
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d->pci_bus = bus_pci_init(devinit->machine, |
d->pci_bus = bus_pci_init(devinit->machine, |
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0 /* TODO: pciirq */, |
tmpstr /* pciirq */, |
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0x90000000 /* TODO: pci_io_offset */, |
0x90000000 /* TODO: pci_io_offset */, |
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0x90010000 /* TODO: pci_mem_offset */, |
0x90010000 /* TODO: pci_mem_offset */, |
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0xffff0000 /* TODO: pci_portbase */, |
0xffff0000 /* TODO: pci_portbase */, |
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0x00000000 /* TODO: pci_membase */, |
0x00000000 /* TODO: pci_membase */, |
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29 /* TODO: pci_irqbase */, |
tmpstr /* pci_irqbase */, |
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0x90000000 /* TODO: isa_portbase */, |
0x90000000 /* TODO: isa_portbase */, |
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0x90010000 /* TODO: isa_membase */, |
0x90010000 /* TODO: isa_membase */, |
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0 /* TODO: isa_irqbase */); |
"TODO: isa_irqbase" /* TODO: isa_irqbase */); |
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memory_device_register(devinit->machine->memory, devinit->name, |
memory_device_register(devinit->machine->memory, devinit->name, |
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devinit->addr, DEV_I80321_LENGTH, |
devinit->addr, DEV_I80321_LENGTH, |
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dev_i80321_access, d, DM_DEFAULT, NULL); |
dev_i80321_access, d, DM_DEFAULT, NULL); |
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/* TODO: Don't hardcode to 100 Hz! */ |
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d->hz = 100; |
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d->timer = timer_add(d->hz, tmr0_tick, d); |
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machine_add_tickfunction(devinit->machine, dev_i80321_tick, |
machine_add_tickfunction(devinit->machine, dev_i80321_tick, |
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d, TICK_SHIFT); |
d, TICK_SHIFT, 0.0); |
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devinit->return_ptr = d; |
devinit->return_ptr = d->pci_bus; |
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return 1; |
return 1; |
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} |
} |