/[gxemul]/trunk/src/devices/dev_i80321.c
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Contents of /trunk/src/devices/dev_i80321.c

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Revision 22 - (show annotations)
Mon Oct 8 16:19:37 2007 UTC (16 years, 5 months ago) by dpavlin
File MIME type: text/plain
File size: 7436 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============


1 /*
2 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_i80321.c,v 1.14 2006/02/18 17:55:25 debug Exp $
29 *
30 * Intel i80321 (ARM) core functionality.
31 *
32 * TODO: This is mostly just a dummy device.
33 * TODO 2: This is hardcoded for little endian emulation.
34 */
35
36 #include <stdio.h>
37 #include <stdlib.h>
38 #include <string.h>
39
40 #include "bus_pci.h"
41 #include "cpu.h"
42 #include "device.h"
43 #include "devices.h"
44 #include "machine.h"
45 #include "memory.h"
46 #include "misc.h"
47
48
49 #include "i80321reg.h"
50
51 #define TICK_SHIFT 20
52 #define DEV_I80321_LENGTH VERDE_PMMR_SIZE
53
54
55 void dev_i80321_tick(struct cpu *cpu, void *extra)
56 {
57 /* struct i80321_data *d = extra; */
58 int do_timer_interrupt = 0;
59
60 if (cpu->cd.arm.tmr0 & TMRx_ENABLE) {
61 do_timer_interrupt = 1;
62 }
63
64 if (do_timer_interrupt) {
65 cpu_interrupt(cpu, 9);
66 cpu->cd.arm.tisr |= TISR_TMR0;
67 } else {
68 cpu_interrupt_ack(cpu, 9);
69 cpu->cd.arm.tisr &= ~TISR_TMR0;
70 }
71 }
72
73
74 DEVICE_ACCESS(i80321)
75 {
76 struct i80321_data *d = extra;
77 uint64_t idata = 0, odata = 0;
78 char *n = NULL;
79 int i, bus, dev, func, reg;
80
81 if (writeflag == MEM_WRITE)
82 idata = memory_readmax64(cpu, data, len);
83
84 /* PCI configuration space: */
85 if (relative_addr >= 0x100 && relative_addr < 0x140) {
86 /* TODO */
87 goto ret;
88 }
89
90 /* MCU registers: */
91 if (relative_addr >= VERDE_MCU_BASE &&
92 relative_addr < VERDE_MCU_BASE + VERDE_MCU_SIZE) {
93 int regnr = (relative_addr - VERDE_MCU_BASE) / sizeof(uint32_t);
94 if (writeflag == MEM_WRITE)
95 d->mcu_reg[regnr] = idata;
96 else
97 odata = d->mcu_reg[regnr];
98 }
99
100
101 switch (relative_addr) {
102
103 /* Address Translation Unit: */
104 case VERDE_ATU_BASE + ATU_IALR0:
105 case VERDE_ATU_BASE + ATU_IATVR0:
106 case VERDE_ATU_BASE + ATU_IALR1:
107 case VERDE_ATU_BASE + ATU_IALR2:
108 case VERDE_ATU_BASE + ATU_IATVR2:
109 case VERDE_ATU_BASE + ATU_OIOWTVR:
110 case VERDE_ATU_BASE + ATU_OMWTVR0:
111 case VERDE_ATU_BASE + ATU_OUMWTVR0:
112 case VERDE_ATU_BASE + ATU_OMWTVR1:
113 case VERDE_ATU_BASE + ATU_OUMWTVR1:
114 /* Ignoring these for now. TODO */
115 break;
116 case VERDE_ATU_BASE + ATU_ATUCR:
117 /* ATU configuration register; ignored for now. TODO */
118 break;
119 case VERDE_ATU_BASE + ATU_PCSR:
120 /* TODO: Temporary hack to allow NetBSD/evbarm to
121 reboot itself. Should be rewritten as soon as possible! */
122 if (writeflag == MEM_WRITE && idata == 0x30) {
123 int j;
124 for (j=0; j<cpu->machine->ncpus; j++)
125 cpu->machine->cpus[j]->running = 0;
126 cpu->machine->exit_without_entering_debugger = 1;
127 }
128 break;
129 case VERDE_ATU_BASE + ATU_ATUIMR:
130 case VERDE_ATU_BASE + ATU_IABAR3:
131 case VERDE_ATU_BASE + ATU_IAUBAR3:
132 case VERDE_ATU_BASE + ATU_IALR3:
133 case VERDE_ATU_BASE + ATU_IATVR3:
134 /* Ignoring these for now. TODO */
135 break;
136 case VERDE_ATU_BASE + ATU_OCCAR:
137 /* PCI address */
138 if (writeflag == MEM_WRITE) {
139 d->pci_addr = idata;
140 bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
141 bus = 0; /* NOTE */
142 bus_pci_setaddr(cpu, d->pci_bus, bus, dev, func, reg);
143 } else {
144 odata = d->pci_addr;
145 }
146 break;
147 case VERDE_ATU_BASE + ATU_OCCDR:
148 case VERDE_ATU_BASE + ATU_OCCDR + 1:
149 case VERDE_ATU_BASE + ATU_OCCDR + 2:
150 case VERDE_ATU_BASE + ATU_OCCDR + 3:
151 /* PCI data */
152 if (writeflag == MEM_READ) {
153 uint64_t tmp;
154 bus_pci_data_access(cpu, d->pci_bus, &tmp,
155 sizeof(uint32_t), MEM_READ);
156 switch (relative_addr) {
157 case VERDE_ATU_BASE + ATU_OCCDR + 1:
158 odata = tmp >> 8; break;
159 case VERDE_ATU_BASE + ATU_OCCDR + 2:
160 odata = tmp >> 16; break;
161 case VERDE_ATU_BASE + ATU_OCCDR + 3:
162 odata = tmp >> 24; break;
163 default:odata = tmp;
164 }
165 } else {
166 uint64_t tmp;
167 int r = relative_addr - (VERDE_ATU_BASE + ATU_OCCDR);
168 bus_pci_data_access(cpu, d->pci_bus, &tmp,
169 sizeof(uint32_t), MEM_READ);
170 for (i=0; i<len; i++) {
171 uint8_t b = idata >> (i*8);
172 tmp &= ~(0xff << ((r+i)*8));
173 tmp |= b << ((r+i)*8);
174 }
175 tmp &= 0xffffffff; /* needed because << is 32-bit */
176 bus_pci_data_access(cpu, d->pci_bus, &tmp,
177 sizeof(uint32_t), MEM_WRITE);
178 }
179 break;
180 case VERDE_ATU_BASE + ATU_PCIXSR:
181 odata = 0; /* TODO */
182 break;
183
184 /* Memory Controller Unit: */
185 case VERDE_MCU_BASE + MCU_SDBR:
186 n = "MCU_SDBR";
187 break;
188 case VERDE_MCU_BASE + MCU_SBR0:
189 n = "MCU_SBR0";
190 break;
191 case VERDE_MCU_BASE + MCU_SBR1:
192 n = "MCU_SBR1";
193 break;
194
195 default:if (writeflag == MEM_READ) {
196 fatal("[ i80321: read from 0x%x ]\n",
197 (int)relative_addr);
198 } else {
199 fatal("[ i80321: write to 0x%x: 0x%llx ]\n",
200 (int)relative_addr, (long long)idata);
201 }
202 }
203
204 if (n != NULL) {
205 if (writeflag == MEM_READ) {
206 debug("[ i80321: read from %s ]\n", n);
207 } else {
208 debug("[ i80321: write to %s: 0x%llx ]\n",
209 n, (long long)idata);
210 }
211 }
212
213 ret:
214 if (writeflag == MEM_READ)
215 memory_writemax64(cpu, data, len, odata);
216
217 return 1;
218 }
219
220
221 DEVINIT(i80321)
222 {
223 struct i80321_data *d = malloc(sizeof(struct i80321_data));
224 uint32_t memsize = devinit->machine->physical_ram_in_mb * 1048576;
225 uint32_t base;
226
227 if (d == NULL) {
228 fprintf(stderr, "out of memory\n");
229 exit(1);
230 }
231 memset(d, 0, sizeof(struct i80321_data));
232
233 d->mcu_reg[MCU_SDBR / sizeof(uint32_t)] = base = 0xa0000000;
234 d->mcu_reg[MCU_SBR0 / sizeof(uint32_t)] = (base + memsize) >> 25;
235 d->mcu_reg[MCU_SBR1 / sizeof(uint32_t)] = (base + memsize) >> 25;
236
237 d->pci_bus = bus_pci_init(devinit->machine,
238 0 /* TODO: pciirq */,
239 0x90000000 /* TODO: pci_io_offset */,
240 0x90010000 /* TODO: pci_mem_offset */,
241 0xffff0000 /* TODO: pci_portbase */,
242 0x00000000 /* TODO: pci_membase */,
243 29 /* TODO: pci_irqbase */,
244 0x90000000 /* TODO: isa_portbase */,
245 0x90010000 /* TODO: isa_membase */,
246 0 /* TODO: isa_irqbase */);
247
248 memory_device_register(devinit->machine->memory, devinit->name,
249 devinit->addr, DEV_I80321_LENGTH,
250 dev_i80321_access, d, DM_DEFAULT, NULL);
251
252 machine_add_tickfunction(devinit->machine, dev_i80321_tick,
253 d, TICK_SHIFT);
254
255 devinit->return_ptr = d;
256
257 return 1;
258 }
259

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