--- trunk/src/devices/dev_gt.c	2007/10/08 16:19:16	19
+++ trunk/src/devices/dev_gt.c	2007/10/08 16:19:23	20
@@ -25,7 +25,7 @@
  *  SUCH DAMAGE.
  *   
  *
- *  $Id: dev_gt.c,v 1.28 2005/10/26 14:37:04 debug Exp $
+ *  $Id: dev_gt.c,v 1.35 2005/11/21 09:17:26 debug Exp $
  *  
  *  Galileo Technology GT-64xxx PCI controller.
  *
@@ -53,9 +53,8 @@
 
 /*  #define debug fatal  */
 
-#define PCI_VENDOR_GALILEO           0x11ab    /* Galileo Technology */
-#define PCI_PRODUCT_GALILEO_GT64011  0x4146    /* GT-64011 System Controller */
-#define	PCI_PRODUCT_GALILEO_GT64120  0x4620    /* GT-64120 */
+#define PCI_PRODUCT_GALILEO_GT64011  0x4146    /*  GT-64011  */
+#define	PCI_PRODUCT_GALILEO_GT64120  0x4620    /*  GT-64120  */
 
 struct gt_data {
 	int	irqnr;
@@ -84,7 +83,7 @@
 	unsigned char *data, size_t len, int writeflag, void *extra)
 {
 	uint64_t idata = 0, odata = 0;
-	int i, asserted;
+	int i;
 	struct gt_data *d = extra;
 
 	if (writeflag == MEM_WRITE)
@@ -117,48 +116,37 @@
 			return 1;
 		} else {
 			odata = 0xffffffffULL;
-			/*  ???  interrupt something...  */
-
-/*
- *  TODO: Remove this hack when things have stabilized.
- */
-odata = 0x00000100;	/*  netbsd/cobalt cobalt/machdep.c:cpu_intr()  */
+			/*
+			 *  ???  interrupt something...
+			 *
+			 *  TODO: Remove this hack when things have stabilized.
+			 */
+			odata = 0x00000100;
+			/*  netbsd/cobalt cobalt/machdep.c:cpu_intr()  */
 
-cpu_interrupt_ack(cpu, d->irqnr);
+			cpu_interrupt_ack(cpu, d->irqnr);
 
 			debug("[ gt: read from 0xc18 (0x%08x) ]\n", (int)odata);
 		}
 		break;
 
 	case 0xc34:	/*  GT_PCI0_INTR_ACK  */
-		/*
-		 *  Ugly hack, which works for at least evbmips/Malta:
-		 */
-		asserted =
-		    (cpu->machine->isa_pic_data.pic1->irr &
-		    ~cpu->machine->isa_pic_data.pic1->ier) |
-		    ((cpu->machine->isa_pic_data.pic2->irr &
-		     ~cpu->machine->isa_pic_data.pic2->ier) << 8);
-		odata = 7;	/*  "Spurious interrupt" defaults to 7.  */
-		for (i=0; i<16; i++)
-			if ((asserted >> i) & 1) {
-				odata = i;
-				break;
-			}
+		odata = cpu->machine->isa_pic_data.last_int;
+		cpu_interrupt_ack(cpu, 8 + odata);
 		break;
 
 	case 0xcf8:	/*  PCI ADDR  */
 	case 0xcfc:	/*  PCI DATA  */
 		if (writeflag == MEM_WRITE) {
 			bus_pci_access(cpu, mem, relative_addr, &idata,
-			    writeflag, d->pci_data);
+			    len, writeflag, d->pci_data);
 		} else {
 			bus_pci_access(cpu, mem, relative_addr, &odata,
-			    writeflag, d->pci_data);
+			    len, writeflag, d->pci_data);
 		}
 		break;
 	default:
-		if (writeflag==MEM_READ) {
+		if (writeflag == MEM_READ) {
 			debug("[ gt: read from addr 0x%x ]\n",
 			    (int)relative_addr);
 		} else {
@@ -177,46 +165,6 @@
 
 
 /*
- *  pci_gt_rr_011():
- */
-static uint32_t pci_gt_rr_011(int reg)
-{
-	switch (reg) {
-	case 0x00:
-		return PCI_VENDOR_GALILEO + (PCI_PRODUCT_GALILEO_GT64011 << 16);
-	case 0x08:
-		return 0x06000001;	/*  Revision 1  */
-	default:
-		return 0;
-	}
-}
-
-
-/*
- *  pci_gt_rr_120():
- */
-static uint32_t pci_gt_rr_120(int reg)
-{
-	switch (reg) {
-	case 0x00:
-		return PCI_VENDOR_GALILEO + (PCI_PRODUCT_GALILEO_GT64120 << 16);
-	case 0x08:
-		return 0x06000002;	/*  Revision 2?  */
-	default:
-		return 0;
-	}
-}
-
-
-/*
- *  pci_gt_init():
- */
-void pci_gt_init(struct machine *machine, struct memory *mem)
-{
-}
-
-
-/*
  *  dev_gt_init():
  *
  *  Initialize a GT device.  Return a pointer to the pci_data used, so that
@@ -227,6 +175,10 @@
 	uint64_t baseaddr, int irq_nr, int pciirq, int type)
 {
 	struct gt_data *d;
+	uint64_t pci_portbase = 0, pci_membase = 0;
+	uint64_t isa_portbase = 0, isa_membase = 0;
+	int isa_irqbase = 0, pci_irqbase = 0;
+	uint64_t pci_io_offset = 0, pci_mem_offset = 0;
 
 	d = malloc(sizeof(struct gt_data));
 	if (d == NULL) {
@@ -236,30 +188,51 @@
 	memset(d, 0, sizeof(struct gt_data));
 	d->irqnr    = irq_nr;
 	d->pciirq   = pciirq;
-	d->pci_data = bus_pci_init(pciirq);
 
 	switch (type) {
 	case 11:
+		/*  Cobalt:  */
 		d->type = PCI_PRODUCT_GALILEO_GT64011;
+		pci_io_offset = 0;
+		pci_mem_offset = 0;
+		pci_portbase = 0x10000000ULL;
+		pci_membase = 0x10100000ULL;
+		pci_irqbase = 0;
+		isa_portbase = 0x10000000ULL;
+		isa_membase = 0x10100000ULL;
+		isa_irqbase = 8;
 		break;
 	case 120:
+		/*  EVBMIPS (Malta):  */
 		d->type = PCI_PRODUCT_GALILEO_GT64120;
+		pci_io_offset = 0;
+		pci_mem_offset = 0;
+		pci_portbase = 0x18000000ULL;
+		pci_membase = 0x10000000ULL;
+		pci_irqbase = 8;
+		isa_portbase = 0x18000000ULL;
+		isa_membase = 0x10000000ULL;
+		isa_irqbase = 8;
 		break;
 	default:fatal("dev_gt_init(): type must be 11 or 120.\n");
 		exit(1);
 	}
 
+	d->pci_data = bus_pci_init(
+	    pciirq, pci_io_offset, pci_mem_offset,
+	    pci_portbase, pci_membase, pci_irqbase,
+	    isa_portbase, isa_membase, isa_irqbase);
+
 	/*
 	 *  According to NetBSD/cobalt:
 	 *  pchb0 at pci0 dev 0 function 0: Galileo GT-64011
 	 *  System Controller, rev 1
 	 */
-	bus_pci_add(machine, d->pci_data, mem, 0, 0, 0, pci_gt_init,
-	    d->type == PCI_PRODUCT_GALILEO_GT64011?
-	    pci_gt_rr_011 : pci_gt_rr_120);
+	bus_pci_add(machine, d->pci_data, mem, 0, 0, 0,
+	    d->type == PCI_PRODUCT_GALILEO_GT64011? "gt64011" : "gt64120");
 
 	memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH,
-	    dev_gt_access, d, MEM_DEFAULT, NULL);
+	    dev_gt_access, d, DM_DEFAULT, NULL);
 	machine_add_tickfunction(machine, dev_gt_tick, d, TICK_SHIFT);
 
 	return d->pci_data;