/[gxemul]/trunk/src/devices/dev_gt.c
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Contents of /trunk/src/devices/dev_gt.c

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Revision 44 - (show annotations)
Mon Oct 8 16:22:56 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 8216 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1632 2007/09/11 21:46:35 debug Exp $
20070616	Implementing the MIPS32/64 revision 2 "ror" instruction.
20070617	Adding a struct for each physpage which keeps track of which
		ranges within that page (base offset, length) that are
		continuously translatable. When running with native code
		generation enabled (-b), a range is added after each read-
		ahead loop.
		Experimenting with using the physical program counter sample
		data (implemented 20070608) together with the "translatable
		range" information, to figure out which physical address ranges
		would be worth translating to native code (if the number of
		samples falling within a range is above a certain threshold).
20070618	Adding automagic building of .index comment files for
		src/file/, src/promemul/, src src/useremul/ as well.
		Adding a "has been translated" bit to the ranges, so that only
		not-yet-translated ranges will be sampled.
20070619	Moving src/cpu.c and src/memory_rw.c into src/cpus/,
		src/device.c into src/devices/, and src/machine.c into
		src/machines/.
		Creating a skeleton cc/ld native backend module; beginning on
		the function which will detect cc command line, etc.
20070620	Continuing on the native code generation infrastructure.
20070621	Moving src/x11.c and src/console.c into a new src/console/
		subdir (for everything that is console or framebuffer related).
		Moving src/symbol*.c into a new src/symbol/, which should
		contain anything that is symbol handling related.
20070624	Making the program counter sampling threshold a "settings
		variable" (sampling_threshold), i.e. it can now be changed
		during runtime.
		Switching the RELEASE notes format from plain text to HTML.
		If the TMPDIR environment variable is set, it is used instead
		of "/tmp" for temporary files.
		Continuing on the cc/ld backend: simple .c code is generated,
		the compiler and linker are called, etc.
		Adding detection of host architecture to the configure script
		(again), and adding icache invalidation support (only
		implemented for Alpha hosts so far).
20070625	Simplifying the program counter sampling mechanism.
20070626	Removing the cc/ld native code generation stuff, program
		counter sampling, etc; it would not have worked well in the
		general case.
20070627	Removing everything related to native code generation.
20070629	Removing the (practically unusable) support for multiple
		emulations. (The single emulation allowed now still supports
		multiple simultaneous machines, as before.)
		Beginning on PCCTWO and M88K interrupts.
20070723	Adding a dummy skeleton for emulation of M32R processors.
20070901	Fixing a warning found by "gcc version 4.3.0 20070817
		(experimental)" on amd64.
20070905	Removing some more traces of the old "multiple emulations"
		code.
		Also looking in /usr/local/include and /usr/local/lib for
		X11 libs, when running configure.
20070909	Minor updates to the guest OS install instructions, in
		preparation for the NetBSD 4.0 release.
20070918	More testing of NetBSD 4.0 RC1.
1 /*
2 * Copyright (C) 2003-2007 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_gt.c,v 1.53 2007/06/16 05:09:55 debug Exp $
29 *
30 * COMMENT: Galileo Technology GT-64xxx PCI controller
31 *
32 * GT-64011 Used in Cobalt machines.
33 * GT-64120 Used in evbmips machines (Malta).
34 * GT-64260 Used in mvmeppc machines.
35 */
36
37 #include <stdio.h>
38 #include <stdlib.h>
39 #include <string.h>
40
41 #include "bus_pci.h"
42 #include "cpu.h"
43 #include "devices.h"
44 #include "interrupt.h"
45 #include "machine.h"
46 #include "memory.h"
47 #include "misc.h"
48 #include "timer.h"
49
50 #include "gtreg.h"
51
52
53 #define TICK_SHIFT 14
54
55 /* #define debug fatal */
56
57 #define PCI_PRODUCT_GALILEO_GT64011 0x4146 /* GT-64011 */
58 #define PCI_PRODUCT_GALILEO_GT64120 0x4620 /* GT-64120 */
59 #define PCI_PRODUCT_GALILEO_GT64260 0x6430 /* GT-64260 */
60
61
62 struct gt_data {
63 int type;
64
65 struct timer *timer;
66 struct interrupt timer0_irq;
67 int interrupt_hz;
68 int pending_timer0_interrupts;
69
70 /* Address decode registers: */
71 uint32_t decode[GT_N_DECODE_REGS];
72
73 struct pci_data *pci_data;
74 };
75
76
77 /*
78 * timer_tick():
79 *
80 * Called d->interrupt_hz times per (real-world) second.
81 */
82 static void timer_tick(struct timer *timer, void *extra)
83 {
84 struct gt_data *d = extra;
85 d->pending_timer0_interrupts ++;
86 }
87
88
89 DEVICE_TICK(gt)
90 {
91 struct gt_data *d = extra;
92 if (d->pending_timer0_interrupts > 0)
93 INTERRUPT_ASSERT(d->timer0_irq);
94 }
95
96
97 DEVICE_ACCESS(gt)
98 {
99 struct gt_data *d = extra;
100 uint64_t idata = 0, odata = 0;
101 int bus, dev, func, reg;
102 size_t i;
103
104 if (writeflag == MEM_WRITE)
105 idata = memory_readmax64(cpu, data, len);
106
107 switch (relative_addr) {
108
109 case GT_PCI0IOLD_OFS:
110 case GT_PCI0IOHD_OFS:
111 case GT_PCI0M0LD_OFS:
112 case GT_PCI0M0HD_OFS:
113 case GT_PCI0M1LD_OFS:
114 case GT_PCI0M1HD_OFS:
115 case GT_PCI0IOREMAP_OFS:
116 case GT_PCI0M0REMAP_OFS:
117 case GT_PCI0M1REMAP_OFS:
118 if (writeflag == MEM_READ) {
119 odata = d->decode[relative_addr / 8];
120 debug("[ gt: read from offset 0x%x: 0x%x ]\n",
121 (int)relative_addr, (int)odata);
122 } else {
123 d->decode[relative_addr / 8] = idata;
124 fatal("[ gt: write to offset 0x%x: 0x%x (TODO) ]\n",
125 (int)relative_addr, (int)idata);
126 }
127 break;
128
129 case GT_PCI0_CMD_OFS:
130 if (writeflag == MEM_WRITE) {
131 debug("[ gt: write to GT_PCI0_CMD: 0x%08x (TODO) ]\n",
132 (int)idata);
133 } else {
134 debug("[ gt: read from GT_PCI0_CMD (0x%08x) (TODO) ]\n",
135 (int)odata);
136 }
137 break;
138
139 case GT_INTR_CAUSE:
140 if (writeflag == MEM_WRITE) {
141 debug("[ gt: write to GT_INTR_CAUSE: 0x%08x ]\n",
142 (int)idata);
143 return 1;
144 } else {
145 odata = GTIC_T0EXP;
146 INTERRUPT_DEASSERT(d->timer0_irq);
147
148 if (d->pending_timer0_interrupts > 0)
149 d->pending_timer0_interrupts --;
150
151 debug("[ gt: read from GT_INTR_CAUSE (0x%08x) ]\n",
152 (int)odata);
153 }
154 break;
155
156 case GT_PCI0_INTR_ACK:
157 odata = cpu->machine->isa_pic_data.last_int;
158 /* TODO: Actually ack the interrupt? */
159 break;
160
161 case GT_TIMER_CTRL:
162 if (writeflag == MEM_WRITE) {
163 if (idata & ENTC0) {
164 /* TODO: Don't hardcode this. */
165 d->interrupt_hz = 100;
166 if (d->timer == NULL)
167 d->timer = timer_add(d->interrupt_hz,
168 timer_tick, d);
169 else
170 timer_update_frequency(d->timer,
171 d->interrupt_hz);
172 }
173 }
174 break;
175
176 case GT_PCI0_CFG_ADDR:
177 if (cpu->byte_order != EMUL_LITTLE_ENDIAN) {
178 fatal("[ gt: TODO: big endian PCI access ]\n");
179 exit(1);
180 }
181 bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
182 bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
183 break;
184
185 case GT_PCI0_CFG_DATA:
186 if (cpu->byte_order != EMUL_LITTLE_ENDIAN) {
187 fatal("[ gt: TODO: big endian PCI access ]\n");
188 exit(1);
189 }
190 bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
191 &odata : &idata, len, writeflag);
192 break;
193
194 default:
195 if (writeflag == MEM_READ) {
196 debug("[ gt: read from addr 0x%x ]\n",
197 (int)relative_addr);
198 } else {
199 debug("[ gt: write to addr 0x%x:", (int)relative_addr);
200 for (i=0; i<len; i++)
201 debug(" %02x", data[i]);
202 debug(" ]\n");
203 }
204 }
205
206 if (writeflag == MEM_READ)
207 memory_writemax64(cpu, data, len, odata);
208
209 return 1;
210 }
211
212
213 /*
214 * dev_gt_init():
215 *
216 * Initialize a Gallileo PCI controller device. First, the controller itself
217 * is added to the bus, then a pointer to the bus is returned.
218 */
219 struct pci_data *dev_gt_init(struct machine *machine, struct memory *mem,
220 uint64_t baseaddr, char *timer_irq_path, char *isa_irq_path, int type)
221 {
222 struct gt_data *d;
223 uint64_t pci_portbase = 0, pci_membase = 0;
224 uint64_t isa_portbase = 0, isa_membase = 0;
225 uint64_t pci_io_offset = 0, pci_mem_offset = 0;
226 char *gt_name = "NO";
227
228 CHECK_ALLOCATION(d = malloc(sizeof(struct gt_data)));
229 memset(d, 0, sizeof(struct gt_data));
230
231 INTERRUPT_CONNECT(timer_irq_path, d->timer0_irq);
232
233 switch (type) {
234 case 11:
235 /* Cobalt: */
236 d->type = PCI_PRODUCT_GALILEO_GT64011;
237 gt_name = "gt64011";
238 pci_io_offset = 0;
239 pci_mem_offset = 0;
240 pci_portbase = 0x10000000ULL;
241 pci_membase = 0x10100000ULL;
242 isa_portbase = 0x10000000ULL;
243 isa_membase = 0x10100000ULL;
244 break;
245 case 120:
246 /* EVBMIPS (Malta): */
247 d->type = PCI_PRODUCT_GALILEO_GT64120;
248 gt_name = "gt64120";
249 pci_io_offset = 0;
250 pci_mem_offset = 0;
251 pci_portbase = 0x18000000ULL;
252 pci_membase = 0x10000000ULL;
253 isa_portbase = 0x18000000ULL;
254 isa_membase = 0x10000000ULL;
255 break;
256 case 260:
257 /* MVMEPPC (mvme5500): */
258 d->type = PCI_PRODUCT_GALILEO_GT64260;
259 gt_name = "gt64260";
260 pci_io_offset = 0;
261 pci_mem_offset = 0;
262 pci_portbase = 0x18000000ULL;
263 pci_membase = 0x10000000ULL;
264 isa_portbase = 0x18000000ULL;
265 isa_membase = 0x10000000ULL;
266 break;
267 default:fatal("dev_gt_init(): unimplemented GT type (%i).\n", type);
268 exit(1);
269 }
270
271
272 /*
273 * TODO: FIX THESE! Hardcoded numbers = bad.
274 */
275 d->decode[GT_PCI0IOLD_OFS / 8] = pci_portbase >> 21;
276 d->decode[GT_PCI0IOHD_OFS / 8] = 0x40;
277 d->decode[GT_PCI0M0LD_OFS / 8] = 0x80;
278 d->decode[GT_PCI0M0HD_OFS / 8] = 0x3f;
279 d->decode[GT_PCI0M1LD_OFS / 8] = 0xc1;
280 d->decode[GT_PCI0M1HD_OFS / 8] = 0x5e;
281 d->decode[GT_PCI0IOREMAP_OFS / 8] = d->decode[GT_PCI0IOLD_OFS / 8];
282 d->decode[GT_PCI0M0REMAP_OFS / 8] = d->decode[GT_PCI0M0LD_OFS / 8];
283 d->decode[GT_PCI0M1REMAP_OFS / 8] = d->decode[GT_PCI0M1LD_OFS / 8];
284
285 d->pci_data = bus_pci_init(machine,
286 "TODO_gt_irq", pci_io_offset, pci_mem_offset,
287 pci_portbase, pci_membase, "TODO_pci_irqbase",
288 isa_portbase, isa_membase, isa_irq_path);
289
290 /*
291 * According to NetBSD/cobalt:
292 * pchb0 at pci0 dev 0 function 0: Galileo GT-64011
293 * System Controller, rev 1
294 */
295 bus_pci_add(machine, d->pci_data, mem, 0, 0, 0, gt_name);
296
297 memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH,
298 dev_gt_access, d, DM_DEFAULT, NULL);
299 machine_add_tickfunction(machine, dev_gt_tick, d, TICK_SHIFT);
300
301 return d->pci_data;
302 }
303
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