/[gxemul]/trunk/src/devices/dev_gt.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Contents of /trunk/src/devices/dev_gt.c

Parent Directory Parent Directory | Revision Log Revision Log


Revision 28 - (show annotations)
Mon Oct 8 16:20:26 2007 UTC (13 years, 1 month ago) by dpavlin
File MIME type: text/plain
File size: 7351 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1298 2006/07/22 11:27:46 debug Exp $
20060626	Continuing on SPARC emulation (beginning on the 'save'
		instruction, register windows, etc).
20060629	Planning statistics gathering (new -s command line option),
		and renaming speed_tricks to allow_instruction_combinations.
20060630	Some minor manual page updates.
		Various cleanups.
		Implementing the -s command line option.
20060701	FINALLY found the bug which prevented Linux and Ultrix from
		running without the ugly hack in the R2000/R3000 cache isol
		code; it was the phystranslation hint array which was buggy.
		Removing the phystranslation hint code completely, for now.
20060702	Minor dyntrans cleanups; invalidation of physpages now only
		invalidate those parts of a page that have actually been
		translated. (32 parts per page.)
		Some MIPS non-R3000 speed fixes.
		Experimenting with MIPS instruction combination for some
		addiu+bne+sw loops, and sw+sw+sw.
		Adding support (again) for larger-than-4KB pages in MIPS tlbw*.
		Continuing on SPARC emulation: adding load/store instructions.
20060704	Fixing a virtual vs physical page shift bug in the new tlbw*
		implementation. Problem noticed by Jakub Jermar. (Many thanks.)
		Moving rfe and eret to cpu_mips_instr.c, since that is the
		only place that uses them nowadays.
20060705	Removing the BSD license from the "testmachine" include files,
		placing them in the public domain instead; this enables the
		testmachine stuff to be used from projects which are
		incompatible with the BSD license for some reason.
20060707	Adding instruction combinations for the R2000/R3000 L1
		I-cache invalidation code used by NetBSD/pmax 3.0, lui+addiu,
		various branches followed by addiu or nop, and jr ra followed
		by addiu. The time it takes to perform a full NetBSD/pmax R3000
		install on the laptop has dropped from 573 seconds to 539. :-)
20060708	Adding a framebuffer controller device (dev_fbctrl), which so
		far can be used to change the fb resolution during runtime, but
		in the future will also be useful for accelerated block fill/
		copy, and possibly also simplified character output.
		Adding an instruction combination for NetBSD/pmax' strlen.
20060709	Minor fixes: reading raw files in src/file.c wasn't memblock
		aligned, removing buggy multi_sw MIPS instruction combination,
		etc.
20060711	Adding a machine_qemu.c, which contains a "qemu_mips" machine.
		(It mimics QEMU's MIPS machine mode, so that a test kernel
		made for QEMU_MIPS also can run in GXemul... at least to some
		extent.)  Adding a short section about how to run this mode to
		doc/guestoses.html.
20060714	Misc. minor code cleanups.
20060715	Applying a patch which adds getchar() to promemul/yamon.c
		(from Oleksandr Tymoshenko).
		Adding yamon.h from NetBSD, and rewriting yamon.c to use it
		(instead of ugly hardcoded numbers) + some cleanup.
20060716	Found and fixed the bug which broke single-stepping of 64-bit
		programs between 0.4.0 and 0.4.0.1 (caused by too quick
		refactoring and no testing). Hopefully this fix will not
		break too many other things.
20060718	Continuing on the 8253 PIT; it now works with Linux/QEMU_MIPS.
		Re-adding the sw+sw+sw instr comb (the problem was that I had
		ignored endian issues); however, it doesn't seem to give any
		big performance gain.
20060720	Adding a dummy Transputer mode (T414, T800 etc) skeleton (only
		the 'j' and 'ldc' instructions are implemented so far). :-}
20060721	Adding gtreg.h from NetBSD, updating dev_gt.c to use it, plus
		misc. other updates to get Linux 2.6 for evbmips/malta working
		(thanks to Alec Voropay for the details).
		FINALLY found and fixed the bug which made tlbw* for non-R3000
		buggy; it was a reference count problem in the dyntrans core.
20060722	Testing stuff; things seem stable enough for a new release.

==============  RELEASE 0.4.1  ==============


1 /*
2 * Copyright (C) 2003-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_gt.c,v 1.42 2006/07/21 16:55:41 debug Exp $
29 *
30 * Galileo Technology GT-64xxx PCI controller.
31 *
32 * GT-64011 Used in Cobalt machines.
33 * GT-64120 Used in evbmips machines (Malta).
34 * GT-64260 Used in mvmeppc machines.
35 *
36 * TODO: This more or less just a dummy device, so far. It happens to work
37 * with some NetBSD ports in some cases, and perhaps with Linux too,
38 * but it is not really working for anything else.
39 */
40
41 #include <stdio.h>
42 #include <stdlib.h>
43 #include <string.h>
44
45 #include "bus_pci.h"
46 #include "cpu.h"
47 #include "devices.h"
48 #include "machine.h"
49 #include "memory.h"
50 #include "misc.h"
51
52 #include "gtreg.h"
53
54
55 #define TICK_SHIFT 14
56
57 /* #define debug fatal */
58
59 #define PCI_PRODUCT_GALILEO_GT64011 0x4146 /* GT-64011 */
60 #define PCI_PRODUCT_GALILEO_GT64120 0x4620 /* GT-64120 */
61 #define PCI_PRODUCT_GALILEO_GT64260 0x6430 /* GT-64260 */
62
63
64 struct gt_data {
65 int timer0_irqnr;
66 int pci_irqbase;
67 int type;
68
69 uint32_t pci0_iold; /* I/O Low Decode address */
70 uint32_t pci0_iohd; /* I/O High Decode address */
71
72 struct pci_data *pci_data;
73 };
74
75
76 DEVICE_TICK(gt)
77 {
78 struct gt_data *gt_data = extra;
79
80 /* TODO: Implement real timer interrupts. */
81
82 cpu_interrupt(cpu, gt_data->timer0_irqnr);
83 }
84
85
86 DEVICE_ACCESS(gt)
87 {
88 uint64_t idata = 0, odata = 0;
89 int bus, dev, func, reg;
90 size_t i;
91 struct gt_data *d = extra;
92
93 if (writeflag == MEM_WRITE)
94 idata = memory_readmax64(cpu, data, len);
95
96 switch (relative_addr) {
97
98 case GT_PCI0IOLD_OFS:
99 if (writeflag == MEM_READ) {
100 odata = d->pci0_iold;
101 } else {
102 fatal("[ gt: write to GT_PCI0IOLD_OFS: 0x%x (TODO) ]\n",
103 (int)idata);
104 }
105 break;
106
107 case GT_PCI0IOHD_OFS:
108 if (writeflag == MEM_READ) {
109 odata = d->pci0_iohd;
110 } else {
111 fatal("[ gt: write to GT_PCI0IOHD_OFS: 0x%x (TODO) ]\n",
112 (int)idata);
113 }
114 break;
115
116 case GT_PCI0IOREMAP_OFS:
117 /* TODO: Same as GT_PCI0IOLD_OFS? */
118 if (writeflag == MEM_READ) {
119 odata = d->pci0_iold;
120 } else {
121 debug("[ gt: write to GT_PCI0IOREMAP_OFS: 0x%x "
122 "(TODO) ]\n", (int)idata);
123 }
124 break;
125
126 case GT_INTR_CAUSE:
127 if (writeflag == MEM_WRITE) {
128 debug("[ gt: write to GT_INTR_CAUSE: 0x%08x ]\n",
129 (int)idata);
130 return 1;
131 } else {
132 odata = GTIC_T0EXP;
133 cpu_interrupt_ack(cpu, d->timer0_irqnr);
134
135 debug("[ gt: read from GT_INTR_CAUSE (0x%08x) ]\n",
136 (int)odata);
137 }
138 break;
139
140 case GT_PCI0_INTR_ACK:
141 odata = cpu->machine->isa_pic_data.last_int;
142 cpu_interrupt_ack(cpu, d->pci_irqbase + odata);
143 break;
144
145 case GT_PCI0_CFG_ADDR:
146 if (cpu->byte_order != EMUL_LITTLE_ENDIAN) {
147 fatal("[ gt: TODO: big endian PCI access ]\n");
148 exit(1);
149 }
150 bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
151 bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
152 break;
153
154 case GT_PCI0_CFG_DATA:
155 if (cpu->byte_order != EMUL_LITTLE_ENDIAN) {
156 fatal("[ gt: TODO: big endian PCI access ]\n");
157 exit(1);
158 }
159 bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
160 &odata : &idata, len, writeflag);
161 break;
162
163 default:
164 if (writeflag == MEM_READ) {
165 debug("[ gt: read from addr 0x%x ]\n",
166 (int)relative_addr);
167 } else {
168 debug("[ gt: write to addr 0x%x:", (int)relative_addr);
169 for (i=0; i<len; i++)
170 debug(" %02x", data[i]);
171 debug(" ]\n");
172 }
173 }
174
175 if (writeflag == MEM_READ)
176 memory_writemax64(cpu, data, len, odata);
177
178 return 1;
179 }
180
181
182 /*
183 * dev_gt_init():
184 *
185 * Initialize a GT device. Return a pointer to the pci_data used, so that
186 * the caller may add PCI devices. First, however, we add the GT device
187 * itself.
188 */
189 struct pci_data *dev_gt_init(struct machine *machine, struct memory *mem,
190 uint64_t baseaddr, int irq_nr, int pciirq, int type)
191 {
192 struct gt_data *d;
193 uint64_t pci_portbase = 0, pci_membase = 0;
194 uint64_t isa_portbase = 0, isa_membase = 0;
195 int isa_irqbase = 0, pci_irqbase = 0;
196 uint64_t pci_io_offset = 0, pci_mem_offset = 0;
197 char *gt_name = "NO";
198
199 d = malloc(sizeof(struct gt_data));
200 if (d == NULL) {
201 fprintf(stderr, "out of memory\n");
202 exit(1);
203 }
204 memset(d, 0, sizeof(struct gt_data));
205 d->timer0_irqnr = irq_nr;
206
207 switch (type) {
208 case 11:
209 /* Cobalt: */
210 d->type = PCI_PRODUCT_GALILEO_GT64011;
211 gt_name = "gt64011";
212 pci_io_offset = 0;
213 pci_mem_offset = 0;
214 pci_portbase = 0x10000000ULL;
215 pci_membase = 0x10100000ULL;
216 pci_irqbase = 8;
217 isa_portbase = 0x10000000ULL;
218 isa_membase = 0x10100000ULL;
219 isa_irqbase = 8;
220 break;
221 case 120:
222 /* EVBMIPS (Malta): */
223 d->type = PCI_PRODUCT_GALILEO_GT64120;
224 gt_name = "gt64120";
225 pci_io_offset = 0;
226 pci_mem_offset = 0;
227 pci_portbase = 0x18000000ULL;
228 pci_membase = 0x10000000ULL;
229 pci_irqbase = 8;
230 isa_portbase = 0x18000000ULL;
231 isa_membase = 0x10000000ULL;
232 isa_irqbase = 8;
233 break;
234 case 260:
235 /* MVMEPPC (mvme5500): */
236 d->type = PCI_PRODUCT_GALILEO_GT64260;
237 gt_name = "gt64260";
238 pci_io_offset = 0;
239 pci_mem_offset = 0;
240 pci_portbase = 0x18000000ULL;
241 pci_membase = 0x10000000ULL;
242 pci_irqbase = 8;
243 isa_portbase = 0x18000000ULL;
244 isa_membase = 0x10000000ULL;
245 isa_irqbase = 8;
246 break;
247 default:fatal("dev_gt_init(): unimplemented GT type (%i).\n", type);
248 exit(1);
249 }
250
251 d->pci_irqbase = pci_irqbase;
252 d->pci0_iold = pci_portbase >> 21;
253 d->pci0_iohd = 0x0000000f; /* TODO? */
254
255 d->pci_data = bus_pci_init(machine,
256 pciirq, pci_io_offset, pci_mem_offset,
257 pci_portbase, pci_membase, pci_irqbase,
258 isa_portbase, isa_membase, isa_irqbase);
259
260 /*
261 * According to NetBSD/cobalt:
262 * pchb0 at pci0 dev 0 function 0: Galileo GT-64011
263 * System Controller, rev 1
264 */
265 bus_pci_add(machine, d->pci_data, mem, 0, 0, 0, gt_name);
266
267 memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH,
268 dev_gt_access, d, DM_DEFAULT, NULL);
269 machine_add_tickfunction(machine, dev_gt_tick, d, TICK_SHIFT, 0.0);
270
271 return d->pci_data;
272 }
273

  ViewVC Help
Powered by ViewVC 1.1.26