/[gxemul]/trunk/src/devices/dev_gt.c
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Contents of /trunk/src/devices/dev_gt.c

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Revision 12 - (show annotations)
Mon Oct 8 16:18:38 2007 UTC (12 years, 2 months ago) by dpavlin
File MIME type: text/plain
File size: 6822 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.905 2005/08/16 09:16:24 debug Exp $
20050628	Continuing the work on the ARM translation engine. end_of_page
		works. Experimenting with load/store translation caches
		(virtual -> physical -> host).
20050629	More ARM stuff (memory access translation cache, mostly). This
		might break a lot of stuff elsewhere, probably some MIPS-
		related translation things.
20050630	Many load/stores are now automatically generated and included
		into cpu_arm_instr.c; 1024 functions in total (!).
		Fixes based on feedback from Alec Voropay: only print 8 hex
		digits instead of 16 in some cases when emulating 32-bit
		machines; similar 8 vs 16 digit fix for breakpoint addresses;
		4Kc has 16 TLB entries, not 48; the MIPS config select1
		register is now printed with "reg ,0".
		Also changing many other occurances of 16 vs 8 digit output.
		Adding cache associativity fields to mips_cpu_types.h; updating
		some other cache fields; making the output of
		mips_cpu_dumpinfo() look nicer.
		Generalizing the bintrans stuff for device accesses to also
		work with the new translation system. (This might also break
		some MIPS things.)
		Adding multi-load/store instructions to the ARM disassembler
		and the translator, and some optimizations of various kinds.
20050701	Adding a simple dev_disk (it can read/write sectors from
		disk images).
20050712	Adding dev_ether (a simple ethernet send/receive device).
		Debugger command "ninstrs" for toggling show_nr_of_instructions
		during runtime.
		Removing the framebuffer logo.
20050713	Continuing on dev_ether.
		Adding a dummy cpu_alpha (again).
20050714	More work on cpu_alpha.
20050715	More work on cpu_alpha. Many instructions work, enough to run
		a simple framebuffer fill test (similar to the ARM test).
20050716	More Alpha stuff.
20050717	Minor updates (Alpha stuff).
20050718	Minor updates (Alpha stuff).
20050719	Generalizing some Alpha instructions.
20050720	More Alpha-related updates.
20050721	Continuing on cpu_alpha. Importing rpb.h from NetBSD/alpha.
20050722	Alpha-related updates: userland stuff (Hello World using
		write() compiled statically for FreeBSD/Alpha runs fine), and
		more instructions are now implemented.
20050723	Fixing ldq_u and stq_u.
		Adding more instructions (conditional moves, masks, extracts,
		shifts).
20050724	More FreeBSD/Alpha userland stuff, and adding some more
		instructions (inserts).
20050725	Continuing on the Alpha stuff. (Adding dummy ldt/stt.)
		Adding a -A command line option to turn off alignment checks
		in some cases (for translated code).
		Trying to remove the old bintrans code which updated the pc
		and nr_of_executed_instructions for every instruction.
20050726	Making another attempt att removing the pc/nr of instructions
		code. This time it worked, huge performance increase for
		artificial test code, but performance loss for real-world
		code :-( so I'm scrapping that code for now.
		Tiny performance increase on Alpha (by using ret instead of
		jmp, to play nice with the Alpha's branch prediction) for the
		old MIPS bintrans backend.
20050727	Various minor fixes and cleanups.
20050728	Switching from a 2-level virtual to host/physical translation
		system for ARM emulation, to a 1-level translation.
		Trying to switch from 2-level to 1-level for the MIPS bintrans
		system as well (Alpha only, so far), but there is at least one
		problem: caches and/or how they work with device mappings.
20050730	Doing the 2-level to 1-level conversion for the i386 backend.
		The cache/device bug is still there for R2K/3K :(
		Various other minor updates (Malta etc).
		The mc146818 clock now updates the UIP bit in a way which works
		better with Linux for at least sgimips and Malta emulation.
		Beginning the work on refactoring the dyntrans system.
20050731	Continuing the dyntrans refactoring.
		Fixing a small but serious host alignment bug in memory_rw.
		Adding support for big-endian load/stores to the i386 bintrans
		backend.
		Another minor i386 bintrans backend update: stores from the
		zero register are now one (or two) loads shorter.
		The slt and sltu instructions were incorrectly implemented for
		the i386 backend; only using them for 32-bit mode for now.
20050801	Continuing the dyntrans refactoring.
		Cleanup of the ns16550 serial controller (removing unnecessary
		code).
		Bugfix (memory corruption bug) in dev_gt, and a patch/hack from
		Alec Voropay for Linux/Malta.
20050802	More cleanup/refactoring of the dyntrans subsystem: adding
		phys_page pointers to the lookup tables, for quick jumps
		between translated pages.
		Better fix for the ns16550 device (but still no real FIFO
		functionality).
		Converting cpu_ppc to the new dyntrans system. This means that
		I will have to start from scratch with implementing each
		instruction, and figure out how to implement dual 64/32-bit
		modes etc.
		Removing the URISC CPU family, because it was useless.
20050803	When selecting a machine type, the main type can now be omitted
		if the subtype name is unique. (I.e. -E can be omitted.)
		Fixing a dyntrans/device update bug. (Writes to offset 0 of
		a device could sometimes go unnoticed.)
		Adding an experimental "instruction combination" hack for
		ARM for memset-like byte fill loops.
20050804	Minor progress on cpu_alpha and related things.
		Finally fixing the MIPS dmult/dmultu bugs.
		Fixing some minor TODOs.
20050805	Generalizing the 8259 PIC. It now also works with Cobalt
		and evbmips emulation, in addition to the x86 hack.
		Finally converting the ns16550 device to use devinit.
		Continuing the work on the dyntrans system. Thinking about
		how to add breakpoints.
20050806	More dyntrans updates. Breakpoints seem to work now.
20050807	Minor updates: cpu_alpha and related things; removing
		dev_malta (as it isn't used any more).
		Dyntrans: working on general "show trace tree" support.
		The trace tree stuff now works with both the old MIPS code and
		with newer dyntrans modes. :)
		Continuing on Alpha-related stuff (trying to get *BSD to boot
		a bit further, adding more instructions, etc).
20050808	Adding a dummy IA64 cpu family, and continuing the refactoring
		of the dyntrans system.
		Removing the regression test stuff, because it was more or
		less useless.
		Adding loadlinked/storeconditional type instructions to the
		Alpha emulation. (Needed for Linux/alpha. Not very well tested
		yet.)
20050809	The function call trace tree now prints a per-function nr of
		arguments. (Semi-meaningless, since that data isn't read yet
		from the ELFs; some hardcoded symbols such as memcpy() and
		strlen() work fine, though.)
		More dyntrans refactoring; taking out more of the things that
		are common to all cpu families.
20050810	Working on adding support for "dual mode" for PPC dyntrans
		(i.e. both 64-bit and 32-bit modes).
		(Re)adding some simple PPC instructions.
20050811	Adding a dummy M68K cpu family. The dyntrans system isn't ready
		for variable-length ISAs yet, so it's completely bogus so far.
		Re-adding more PPC instructions.
		Adding a hack to src/file.c which allows OpenBSD/mac68k a.out
		kernels to be loaded.
		Beginning to add PPC loads/stores. So far they only work in
		32-bit mode.
20050812	The configure file option "add_remote" now accepts symbolic
		host names, in addition to numeric IPv4 addresses.
		Re-adding more PPC instructions.
20050814	Continuing to port back more PPC instructions.
		Found and fixed the cache/device write-update bug for 32-bit
		MIPS bintrans. :-)
		Triggered a really weird and annoying bug in Compaq's C
		compiler; ccc sometimes outputs code which loads from an
		address _before_ checking whether the pointer was NULL or not.
		(I'm not sure how to handle this problem.)
20050815	Removing all of the old x86 instruction execution code; adding
		a new (dummy) dyntrans module for x86.
		Taking the first steps to extend the dyntrans system to support
		variable-length instructions.
		Slowly preparing for the next release.
20050816	Adding a dummy SPARC cpu module.
		Minor updates (documentation etc) for the release.

==============  RELEASE 0.3.5  ==============


1 /*
2 * Copyright (C) 2003-2005 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_gt.c,v 1.26 2005/08/05 07:50:37 debug Exp $
29 *
30 * Galileo Technology GT-64xxx PCI controller.
31 *
32 * GT-64011 Used in Cobalt machines.
33 * GT-64120 Used in evbmips machines (Malta).
34 *
35 * TODO: This more or less just a dummy device, so far. It happens to work
36 * with NetBSD/cobalt and /evbmips, and in some cases it might happen
37 * to work with Linux as well, but don't rely on it for anything else.
38 */
39
40 #include <stdio.h>
41 #include <stdlib.h>
42 #include <string.h>
43
44 #include "bus_pci.h"
45 #include "cpu.h"
46 #include "devices.h"
47 #include "machine.h"
48 #include "memory.h"
49 #include "misc.h"
50
51
52 #define TICK_SHIFT 14
53
54 /* #define debug fatal */
55
56 #define PCI_VENDOR_GALILEO 0x11ab /* Galileo Technology */
57 #define PCI_PRODUCT_GALILEO_GT64011 0x4146 /* GT-64011 System Controller */
58 #define PCI_PRODUCT_GALILEO_GT64120 0x4620 /* GT-64120 */
59
60 struct gt_data {
61 int irqnr;
62 int pciirq;
63 int type;
64
65 struct pci_data *pci_data;
66 };
67
68
69 /*
70 * dev_gt_tick():
71 */
72 void dev_gt_tick(struct cpu *cpu, void *extra)
73 {
74 struct gt_data *gt_data = extra;
75
76 cpu_interrupt(cpu, gt_data->irqnr);
77 }
78
79
80 /*
81 * dev_gt_access():
82 */
83 int dev_gt_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr,
84 unsigned char *data, size_t len, int writeflag, void *extra)
85 {
86 uint64_t idata = 0, odata = 0;
87 int i, asserted;
88 struct gt_data *d = extra;
89
90 idata = memory_readmax64(cpu, data, len);
91
92 switch (relative_addr) {
93
94 case 0x48:
95 switch (d->type) {
96 case PCI_PRODUCT_GALILEO_GT64120:
97 /*
98 * This is needed for Linux on Malta, according
99 * to Alec Voropay. (TODO: Remove this hack when
100 * things have stabilized.)
101 */
102 if (writeflag == MEM_READ) {
103 odata = 0x18000000 >> 21;
104 debug("[ gt: read from 0x48: 0x%08x ]\n",
105 (int)odata);
106 }
107 break;
108 default:
109 fatal("[ gt: access to 0x48? (type %i) ]\n", d->type);
110 }
111 break;
112
113 case 0xc18:
114 if (writeflag == MEM_WRITE) {
115 debug("[ gt: write to 0xc18: 0x%08x ]\n", (int)idata);
116 return 1;
117 } else {
118 odata = 0xffffffffULL;
119 /* ??? interrupt something... */
120
121 /*
122 * TODO: Remove this hack when things have stabilized.
123 */
124 odata = 0x00000100; /* netbsd/cobalt cobalt/machdep.c:cpu_intr() */
125
126 cpu_interrupt_ack(cpu, d->irqnr);
127
128 debug("[ gt: read from 0xc18 (0x%08x) ]\n", (int)odata);
129 }
130 break;
131
132 case 0xc34: /* GT_PCI0_INTR_ACK */
133 /*
134 * Ugly hack, which works for at least evbmips/Malta:
135 */
136 asserted =
137 (cpu->machine->md_int.isa_pic_data.pic1->irr &
138 ~cpu->machine->md_int.isa_pic_data.pic1->ier) |
139 ((cpu->machine->md_int.isa_pic_data.pic2->irr &
140 ~cpu->machine->md_int.isa_pic_data.pic2->ier) << 8);
141 odata = 7; /* "Spurious interrupt" defaults to 7. */
142 for (i=0; i<16; i++)
143 if ((asserted >> i) & 1) {
144 odata = i;
145 break;
146 }
147 break;
148
149 case 0xcf8: /* PCI ADDR */
150 case 0xcfc: /* PCI DATA */
151 if (writeflag == MEM_WRITE) {
152 bus_pci_access(cpu, mem, relative_addr, &idata,
153 writeflag, d->pci_data);
154 } else {
155 bus_pci_access(cpu, mem, relative_addr, &odata,
156 writeflag, d->pci_data);
157 }
158 break;
159 default:
160 if (writeflag==MEM_READ) {
161 debug("[ gt: read from addr 0x%x ]\n",
162 (int)relative_addr);
163 } else {
164 debug("[ gt: write to addr 0x%x:", (int)relative_addr);
165 for (i=0; i<len; i++)
166 debug(" %02x", data[i]);
167 debug(" ]\n");
168 }
169 }
170
171 if (writeflag == MEM_READ)
172 memory_writemax64(cpu, data, len, odata);
173
174 return 1;
175 }
176
177
178 /*
179 * pci_gt_rr_011():
180 */
181 static uint32_t pci_gt_rr_011(int reg)
182 {
183 switch (reg) {
184 case 0x00:
185 return PCI_VENDOR_GALILEO + (PCI_PRODUCT_GALILEO_GT64011 << 16);
186 case 0x08:
187 return 0x06000001; /* Revision 1 */
188 default:
189 return 0;
190 }
191 }
192
193
194 /*
195 * pci_gt_rr_120():
196 */
197 static uint32_t pci_gt_rr_120(int reg)
198 {
199 switch (reg) {
200 case 0x00:
201 return PCI_VENDOR_GALILEO + (PCI_PRODUCT_GALILEO_GT64120 << 16);
202 case 0x08:
203 return 0x06000002; /* Revision 2? */
204 default:
205 return 0;
206 }
207 }
208
209
210 /*
211 * pci_gt_init():
212 */
213 void pci_gt_init(struct machine *machine, struct memory *mem)
214 {
215 }
216
217
218 /*
219 * dev_gt_init():
220 *
221 * Initialize a GT device. Return a pointer to the pci_data used, so that
222 * the caller may add PCI devices. First, however, we add the GT device
223 * itself.
224 */
225 struct pci_data *dev_gt_init(struct machine *machine, struct memory *mem,
226 uint64_t baseaddr, int irq_nr, int pciirq, int type)
227 {
228 struct gt_data *d;
229
230 d = malloc(sizeof(struct gt_data));
231 if (d == NULL) {
232 fprintf(stderr, "out of memory\n");
233 exit(1);
234 }
235 memset(d, 0, sizeof(struct gt_data));
236 d->irqnr = irq_nr;
237 d->pciirq = pciirq;
238 d->pci_data = bus_pci_init(pciirq);
239
240 switch (type) {
241 case 11:
242 d->type = PCI_PRODUCT_GALILEO_GT64011;
243 break;
244 case 120:
245 d->type = PCI_PRODUCT_GALILEO_GT64120;
246 break;
247 default:fatal("dev_gt_init(): type must be 11 or 120.\n");
248 exit(1);
249 }
250
251 /*
252 * According to NetBSD/cobalt:
253 * pchb0 at pci0 dev 0 function 0: Galileo GT-64011
254 * System Controller, rev 1
255 */
256 bus_pci_add(machine, d->pci_data, mem, 0, 0, 0, pci_gt_init,
257 d->type == PCI_PRODUCT_GALILEO_GT64011?
258 pci_gt_rr_011 : pci_gt_rr_120);
259
260 memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH,
261 dev_gt_access, d, MEM_DEFAULT, NULL);
262 machine_add_tickfunction(machine, dev_gt_tick, d, TICK_SHIFT);
263
264 return d->pci_data;
265 }
266

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