/[gxemul]/trunk/src/devices/dev_gt.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Diff of /trunk/src/devices/dev_gt.c

Parent Directory Parent Directory | Revision Log Revision Log | View Patch Patch

revision 32 by dpavlin, Mon Oct 8 16:20:58 2007 UTC revision 34 by dpavlin, Mon Oct 8 16:21:17 2007 UTC
# Line 1  Line 1 
1  /*  /*
2   *  Copyright (C) 2003-2006  Anders Gavare.  All rights reserved.   *  Copyright (C) 2003-2007  Anders Gavare.  All rights reserved.
3   *   *
4   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
5   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 25  Line 25 
25   *  SUCH DAMAGE.   *  SUCH DAMAGE.
26   *     *  
27   *   *
28   *  $Id: dev_gt.c,v 1.44 2006/09/23 03:52:10 debug Exp $   *  $Id: dev_gt.c,v 1.49 2007/01/05 16:50:08 debug Exp $
29   *     *  
30   *  Galileo Technology GT-64xxx PCI controller.   *  Galileo Technology GT-64xxx PCI controller.
31   *   *
# Line 41  Line 41 
41  #include "bus_pci.h"  #include "bus_pci.h"
42  #include "cpu.h"  #include "cpu.h"
43  #include "devices.h"  #include "devices.h"
44    #include "interrupt.h"
45  #include "machine.h"  #include "machine.h"
46  #include "memory.h"  #include "memory.h"
47  #include "misc.h"  #include "misc.h"
# Line 59  Line 60 
60    
61    
62  struct gt_data {  struct gt_data {
         int             pci_irqbase;  
63          int             type;          int             type;
64    
65          struct timer    *timer;          struct timer    *timer;
66          int             timer0_irqnr;          struct interrupt timer0_irq;
67          int             interrupt_hz;          int             interrupt_hz;
68          int             pending_timer0_interrupts;          int             pending_timer0_interrupts;
69    
# Line 91  DEVICE_TICK(gt) Line 91  DEVICE_TICK(gt)
91          struct gt_data *d = (struct gt_data *) extra;          struct gt_data *d = (struct gt_data *) extra;
92    
93          if (d->pending_timer0_interrupts > 0)          if (d->pending_timer0_interrupts > 0)
94                  cpu_interrupt(cpu, d->timer0_irqnr);                  INTERRUPT_ASSERT(d->timer0_irq);
95  }  }
96    
97    
# Line 144  DEVICE_ACCESS(gt) Line 144  DEVICE_ACCESS(gt)
144                          return 1;                          return 1;
145                  } else {                  } else {
146                          odata = GTIC_T0EXP;                          odata = GTIC_T0EXP;
147                          cpu_interrupt_ack(cpu, d->timer0_irqnr);                          INTERRUPT_DEASSERT(d->timer0_irq);
148    
149                          if (d->pending_timer0_interrupts > 0)                          if (d->pending_timer0_interrupts > 0)
150                                  d->pending_timer0_interrupts --;                                  d->pending_timer0_interrupts --;
# Line 156  DEVICE_ACCESS(gt) Line 156  DEVICE_ACCESS(gt)
156    
157          case GT_PCI0_INTR_ACK:          case GT_PCI0_INTR_ACK:
158                  odata = cpu->machine->isa_pic_data.last_int;                  odata = cpu->machine->isa_pic_data.last_int;
159                  cpu_interrupt_ack(cpu, d->pci_irqbase + odata);  
160    fatal("TODO: GT_PCI0_INTR_ACK\n");
161    
162    //              cpu_interrupt_ack(cpu, d->pci_irqbase + odata);
163                  break;                  break;
164    
165          case GT_TIMER_CTRL:          case GT_TIMER_CTRL:
# Line 218  DEVICE_ACCESS(gt) Line 221  DEVICE_ACCESS(gt)
221   *  is added to the bus, then a pointer to the bus is returned.   *  is added to the bus, then a pointer to the bus is returned.
222   */   */
223  struct pci_data *dev_gt_init(struct machine *machine, struct memory *mem,  struct pci_data *dev_gt_init(struct machine *machine, struct memory *mem,
224          uint64_t baseaddr, int irq_nr, int pciirq, int type)          uint64_t baseaddr, char *timer_irq_path, char *isa_irq_path, int type)
225  {  {
226          struct gt_data *d;          struct gt_data *d;
227          uint64_t pci_portbase = 0, pci_membase = 0;          uint64_t pci_portbase = 0, pci_membase = 0;
228          uint64_t isa_portbase = 0, isa_membase = 0;          uint64_t isa_portbase = 0, isa_membase = 0;
         int isa_irqbase = 0, pci_irqbase = 0;  
229          uint64_t pci_io_offset = 0, pci_mem_offset = 0;          uint64_t pci_io_offset = 0, pci_mem_offset = 0;
230          char *gt_name = "NO";          char *gt_name = "NO";
231    
# Line 233  struct pci_data *dev_gt_init(struct mach Line 235  struct pci_data *dev_gt_init(struct mach
235                  exit(1);                  exit(1);
236          }          }
237          memset(d, 0, sizeof(struct gt_data));          memset(d, 0, sizeof(struct gt_data));
238          d->timer0_irqnr = irq_nr;  
239            INTERRUPT_CONNECT(timer_irq_path, d->timer0_irq);
240    
241          switch (type) {          switch (type) {
242          case 11:          case 11:
# Line 244  struct pci_data *dev_gt_init(struct mach Line 247  struct pci_data *dev_gt_init(struct mach
247                  pci_mem_offset = 0;                  pci_mem_offset = 0;
248                  pci_portbase = 0x10000000ULL;                  pci_portbase = 0x10000000ULL;
249                  pci_membase = 0x10100000ULL;                  pci_membase = 0x10100000ULL;
                 pci_irqbase = 8;  
250                  isa_portbase = 0x10000000ULL;                  isa_portbase = 0x10000000ULL;
251                  isa_membase = 0x10100000ULL;                  isa_membase = 0x10100000ULL;
                 isa_irqbase = 8;  
252                  break;                  break;
253          case 120:          case 120:
254                  /*  EVBMIPS (Malta):  */                  /*  EVBMIPS (Malta):  */
# Line 257  struct pci_data *dev_gt_init(struct mach Line 258  struct pci_data *dev_gt_init(struct mach
258                  pci_mem_offset = 0;                  pci_mem_offset = 0;
259                  pci_portbase = 0x18000000ULL;                  pci_portbase = 0x18000000ULL;
260                  pci_membase = 0x10000000ULL;                  pci_membase = 0x10000000ULL;
                 pci_irqbase = 8;  
261                  isa_portbase = 0x18000000ULL;                  isa_portbase = 0x18000000ULL;
262                  isa_membase = 0x10000000ULL;                  isa_membase = 0x10000000ULL;
                 isa_irqbase = 8;  
263                  break;                  break;
264          case 260:          case 260:
265                  /*  MVMEPPC (mvme5500):  */                  /*  MVMEPPC (mvme5500):  */
# Line 270  struct pci_data *dev_gt_init(struct mach Line 269  struct pci_data *dev_gt_init(struct mach
269                  pci_mem_offset = 0;                  pci_mem_offset = 0;
270                  pci_portbase = 0x18000000ULL;                  pci_portbase = 0x18000000ULL;
271                  pci_membase = 0x10000000ULL;                  pci_membase = 0x10000000ULL;
                 pci_irqbase = 8;  
272                  isa_portbase = 0x18000000ULL;                  isa_portbase = 0x18000000ULL;
273                  isa_membase = 0x10000000ULL;                  isa_membase = 0x10000000ULL;
                 isa_irqbase = 8;  
274                  break;                  break;
275          default:fatal("dev_gt_init(): unimplemented GT type (%i).\n", type);          default:fatal("dev_gt_init(): unimplemented GT type (%i).\n", type);
276                  exit(1);                  exit(1);
277          }          }
278    
279    
         d->pci_irqbase = pci_irqbase;  
   
280          /*          /*
281           *  TODO: FIX THESE! Hardcoded numbers = bad.           *  TODO: FIX THESE! Hardcoded numbers = bad.
282           */           */
# Line 296  struct pci_data *dev_gt_init(struct mach Line 291  struct pci_data *dev_gt_init(struct mach
291          d->decode[GT_PCI0M1REMAP_OFS / 8] = d->decode[GT_PCI0M1LD_OFS / 8];          d->decode[GT_PCI0M1REMAP_OFS / 8] = d->decode[GT_PCI0M1LD_OFS / 8];
292    
293          d->pci_data = bus_pci_init(machine,          d->pci_data = bus_pci_init(machine,
294              pciirq, pci_io_offset, pci_mem_offset,              "TODO irq stuff!", pci_io_offset, pci_mem_offset,
295              pci_portbase, pci_membase, pci_irqbase,              pci_portbase, pci_membase, "TODO: pci_irqbase",
296              isa_portbase, isa_membase, isa_irqbase);              isa_portbase, isa_membase, isa_irq_path);
297    
298          /*          /*
299           *  According to NetBSD/cobalt:           *  According to NetBSD/cobalt:
Legend:
Removed from v.32  
changed lines
  Added in v.34
  ViewVC Help
Powered by ViewVC 1.1.26