--- trunk/src/devices/dev_gt.c	2007/10/08 16:19:28	21
+++ trunk/src/devices/dev_gt.c	2007/10/08 16:19:37	22
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2003-2005  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2003-2006  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -25,16 +25,17 @@
  *  SUCH DAMAGE.
  *   
  *
- *  $Id: dev_gt.c,v 1.35 2005/11/21 09:17:26 debug Exp $
+ *  $Id: dev_gt.c,v 1.40 2006/01/14 11:29:36 debug Exp $
  *  
  *  Galileo Technology GT-64xxx PCI controller.
  *
  *	GT-64011	Used in Cobalt machines.
  *	GT-64120	Used in evbmips machines (Malta).
+ *	GT-64260	Used in mvmeppc machines.
  *
  *  TODO: This more or less just a dummy device, so far. It happens to work
- *        with NetBSD/cobalt and /evbmips, and in some cases it might happen
- *        to work with Linux as well, but don't rely on it for anything else.
+ *        with some NetBSD ports in some cases, and perhaps with Linux too,
+ *        but it is not really working for anything else.
  */
 
 #include <stdio.h>
@@ -55,6 +56,7 @@
 
 #define PCI_PRODUCT_GALILEO_GT64011  0x4146    /*  GT-64011  */
 #define	PCI_PRODUCT_GALILEO_GT64120  0x4620    /*  GT-64120  */
+#define	PCI_PRODUCT_GALILEO_GT64260  0x6430    /*  GT-64260  */
 
 struct gt_data {
 	int	irqnr;
@@ -79,11 +81,11 @@
 /*
  *  dev_gt_access():
  */
-int dev_gt_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr,
-	unsigned char *data, size_t len, int writeflag, void *extra)
+DEVICE_ACCESS(gt)
 {
 	uint64_t idata = 0, odata = 0;
-	int i;
+	int bus, dev, func, reg;
+	size_t i;
 	struct gt_data *d = extra;
 
 	if (writeflag == MEM_WRITE)
@@ -136,15 +138,23 @@
 		break;
 
 	case 0xcf8:	/*  PCI ADDR  */
+		if (cpu->byte_order != EMUL_LITTLE_ENDIAN) {
+			fatal("[ gt: TODO: big endian PCI access ]\n");
+			exit(1);
+		}
+		bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
+		bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
+		break;
+
 	case 0xcfc:	/*  PCI DATA  */
-		if (writeflag == MEM_WRITE) {
-			bus_pci_access(cpu, mem, relative_addr, &idata,
-			    len, writeflag, d->pci_data);
-		} else {
-			bus_pci_access(cpu, mem, relative_addr, &odata,
-			    len, writeflag, d->pci_data);
+		if (cpu->byte_order != EMUL_LITTLE_ENDIAN) {
+			fatal("[ gt: TODO: big endian PCI access ]\n");
+			exit(1);
 		}
+		bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
+		    &odata : &idata, len, writeflag);
 		break;
+
 	default:
 		if (writeflag == MEM_READ) {
 			debug("[ gt: read from addr 0x%x ]\n",
@@ -179,6 +189,7 @@
 	uint64_t isa_portbase = 0, isa_membase = 0;
 	int isa_irqbase = 0, pci_irqbase = 0;
 	uint64_t pci_io_offset = 0, pci_mem_offset = 0;
+	char *gt_name = "NO";
 
 	d = malloc(sizeof(struct gt_data));
 	if (d == NULL) {
@@ -193,6 +204,7 @@
 	case 11:
 		/*  Cobalt:  */
 		d->type = PCI_PRODUCT_GALILEO_GT64011;
+		gt_name = "gt64011";
 		pci_io_offset = 0;
 		pci_mem_offset = 0;
 		pci_portbase = 0x10000000ULL;
@@ -205,6 +217,20 @@
 	case 120:
 		/*  EVBMIPS (Malta):  */
 		d->type = PCI_PRODUCT_GALILEO_GT64120;
+		gt_name = "gt64120";
+		pci_io_offset = 0;
+		pci_mem_offset = 0;
+		pci_portbase = 0x18000000ULL;
+		pci_membase = 0x10000000ULL;
+		pci_irqbase = 8;
+		isa_portbase = 0x18000000ULL;
+		isa_membase = 0x10000000ULL;
+		isa_irqbase = 8;
+		break;
+	case 260:
+		/*  MVMEPPC (mvme5500):  */
+		d->type = PCI_PRODUCT_GALILEO_GT64260;
+		gt_name = "gt64260";
 		pci_io_offset = 0;
 		pci_mem_offset = 0;
 		pci_portbase = 0x18000000ULL;
@@ -214,11 +240,11 @@
 		isa_membase = 0x10000000ULL;
 		isa_irqbase = 8;
 		break;
-	default:fatal("dev_gt_init(): type must be 11 or 120.\n");
+	default:fatal("dev_gt_init(): unimplemented GT type (%i).\n", type);
 		exit(1);
 	}
 
-	d->pci_data = bus_pci_init(
+	d->pci_data = bus_pci_init(machine,
 	    pciirq, pci_io_offset, pci_mem_offset,
 	    pci_portbase, pci_membase, pci_irqbase,
 	    isa_portbase, isa_membase, isa_irqbase);
@@ -228,8 +254,7 @@
 	 *  pchb0 at pci0 dev 0 function 0: Galileo GT-64011
 	 *  System Controller, rev 1
 	 */
-	bus_pci_add(machine, d->pci_data, mem, 0, 0, 0,
-	    d->type == PCI_PRODUCT_GALILEO_GT64011? "gt64011" : "gt64120");
+	bus_pci_add(machine, d->pci_data, mem, 0, 0, 0, gt_name);
 
 	memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH,
 	    dev_gt_access, d, DM_DEFAULT, NULL);