25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: dev_gt.c,v 1.28 2005/10/26 14:37:04 debug Exp $ |
* $Id: dev_gt.c,v 1.35 2005/11/21 09:17:26 debug Exp $ |
29 |
* |
* |
30 |
* Galileo Technology GT-64xxx PCI controller. |
* Galileo Technology GT-64xxx PCI controller. |
31 |
* |
* |
53 |
|
|
54 |
/* #define debug fatal */ |
/* #define debug fatal */ |
55 |
|
|
56 |
#define PCI_VENDOR_GALILEO 0x11ab /* Galileo Technology */ |
#define PCI_PRODUCT_GALILEO_GT64011 0x4146 /* GT-64011 */ |
57 |
#define PCI_PRODUCT_GALILEO_GT64011 0x4146 /* GT-64011 System Controller */ |
#define PCI_PRODUCT_GALILEO_GT64120 0x4620 /* GT-64120 */ |
|
#define PCI_PRODUCT_GALILEO_GT64120 0x4620 /* GT-64120 */ |
|
58 |
|
|
59 |
struct gt_data { |
struct gt_data { |
60 |
int irqnr; |
int irqnr; |
83 |
unsigned char *data, size_t len, int writeflag, void *extra) |
unsigned char *data, size_t len, int writeflag, void *extra) |
84 |
{ |
{ |
85 |
uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
86 |
int i, asserted; |
int i; |
87 |
struct gt_data *d = extra; |
struct gt_data *d = extra; |
88 |
|
|
89 |
if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) |
116 |
return 1; |
return 1; |
117 |
} else { |
} else { |
118 |
odata = 0xffffffffULL; |
odata = 0xffffffffULL; |
119 |
/* ??? interrupt something... */ |
/* |
120 |
|
* ??? interrupt something... |
121 |
/* |
* |
122 |
* TODO: Remove this hack when things have stabilized. |
* TODO: Remove this hack when things have stabilized. |
123 |
*/ |
*/ |
124 |
odata = 0x00000100; /* netbsd/cobalt cobalt/machdep.c:cpu_intr() */ |
odata = 0x00000100; |
125 |
|
/* netbsd/cobalt cobalt/machdep.c:cpu_intr() */ |
126 |
|
|
127 |
cpu_interrupt_ack(cpu, d->irqnr); |
cpu_interrupt_ack(cpu, d->irqnr); |
128 |
|
|
129 |
debug("[ gt: read from 0xc18 (0x%08x) ]\n", (int)odata); |
debug("[ gt: read from 0xc18 (0x%08x) ]\n", (int)odata); |
130 |
} |
} |
131 |
break; |
break; |
132 |
|
|
133 |
case 0xc34: /* GT_PCI0_INTR_ACK */ |
case 0xc34: /* GT_PCI0_INTR_ACK */ |
134 |
/* |
odata = cpu->machine->isa_pic_data.last_int; |
135 |
* Ugly hack, which works for at least evbmips/Malta: |
cpu_interrupt_ack(cpu, 8 + odata); |
|
*/ |
|
|
asserted = |
|
|
(cpu->machine->isa_pic_data.pic1->irr & |
|
|
~cpu->machine->isa_pic_data.pic1->ier) | |
|
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((cpu->machine->isa_pic_data.pic2->irr & |
|
|
~cpu->machine->isa_pic_data.pic2->ier) << 8); |
|
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odata = 7; /* "Spurious interrupt" defaults to 7. */ |
|
|
for (i=0; i<16; i++) |
|
|
if ((asserted >> i) & 1) { |
|
|
odata = i; |
|
|
break; |
|
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} |
|
136 |
break; |
break; |
137 |
|
|
138 |
case 0xcf8: /* PCI ADDR */ |
case 0xcf8: /* PCI ADDR */ |
139 |
case 0xcfc: /* PCI DATA */ |
case 0xcfc: /* PCI DATA */ |
140 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
141 |
bus_pci_access(cpu, mem, relative_addr, &idata, |
bus_pci_access(cpu, mem, relative_addr, &idata, |
142 |
writeflag, d->pci_data); |
len, writeflag, d->pci_data); |
143 |
} else { |
} else { |
144 |
bus_pci_access(cpu, mem, relative_addr, &odata, |
bus_pci_access(cpu, mem, relative_addr, &odata, |
145 |
writeflag, d->pci_data); |
len, writeflag, d->pci_data); |
146 |
} |
} |
147 |
break; |
break; |
148 |
default: |
default: |
149 |
if (writeflag==MEM_READ) { |
if (writeflag == MEM_READ) { |
150 |
debug("[ gt: read from addr 0x%x ]\n", |
debug("[ gt: read from addr 0x%x ]\n", |
151 |
(int)relative_addr); |
(int)relative_addr); |
152 |
} else { |
} else { |
165 |
|
|
166 |
|
|
167 |
/* |
/* |
|
* pci_gt_rr_011(): |
|
|
*/ |
|
|
static uint32_t pci_gt_rr_011(int reg) |
|
|
{ |
|
|
switch (reg) { |
|
|
case 0x00: |
|
|
return PCI_VENDOR_GALILEO + (PCI_PRODUCT_GALILEO_GT64011 << 16); |
|
|
case 0x08: |
|
|
return 0x06000001; /* Revision 1 */ |
|
|
default: |
|
|
return 0; |
|
|
} |
|
|
} |
|
|
|
|
|
|
|
|
/* |
|
|
* pci_gt_rr_120(): |
|
|
*/ |
|
|
static uint32_t pci_gt_rr_120(int reg) |
|
|
{ |
|
|
switch (reg) { |
|
|
case 0x00: |
|
|
return PCI_VENDOR_GALILEO + (PCI_PRODUCT_GALILEO_GT64120 << 16); |
|
|
case 0x08: |
|
|
return 0x06000002; /* Revision 2? */ |
|
|
default: |
|
|
return 0; |
|
|
} |
|
|
} |
|
|
|
|
|
|
|
|
/* |
|
|
* pci_gt_init(): |
|
|
*/ |
|
|
void pci_gt_init(struct machine *machine, struct memory *mem) |
|
|
{ |
|
|
} |
|
|
|
|
|
|
|
|
/* |
|
168 |
* dev_gt_init(): |
* dev_gt_init(): |
169 |
* |
* |
170 |
* Initialize a GT device. Return a pointer to the pci_data used, so that |
* Initialize a GT device. Return a pointer to the pci_data used, so that |
175 |
uint64_t baseaddr, int irq_nr, int pciirq, int type) |
uint64_t baseaddr, int irq_nr, int pciirq, int type) |
176 |
{ |
{ |
177 |
struct gt_data *d; |
struct gt_data *d; |
178 |
|
uint64_t pci_portbase = 0, pci_membase = 0; |
179 |
|
uint64_t isa_portbase = 0, isa_membase = 0; |
180 |
|
int isa_irqbase = 0, pci_irqbase = 0; |
181 |
|
uint64_t pci_io_offset = 0, pci_mem_offset = 0; |
182 |
|
|
183 |
d = malloc(sizeof(struct gt_data)); |
d = malloc(sizeof(struct gt_data)); |
184 |
if (d == NULL) { |
if (d == NULL) { |
188 |
memset(d, 0, sizeof(struct gt_data)); |
memset(d, 0, sizeof(struct gt_data)); |
189 |
d->irqnr = irq_nr; |
d->irqnr = irq_nr; |
190 |
d->pciirq = pciirq; |
d->pciirq = pciirq; |
|
d->pci_data = bus_pci_init(pciirq); |
|
191 |
|
|
192 |
switch (type) { |
switch (type) { |
193 |
case 11: |
case 11: |
194 |
|
/* Cobalt: */ |
195 |
d->type = PCI_PRODUCT_GALILEO_GT64011; |
d->type = PCI_PRODUCT_GALILEO_GT64011; |
196 |
|
pci_io_offset = 0; |
197 |
|
pci_mem_offset = 0; |
198 |
|
pci_portbase = 0x10000000ULL; |
199 |
|
pci_membase = 0x10100000ULL; |
200 |
|
pci_irqbase = 0; |
201 |
|
isa_portbase = 0x10000000ULL; |
202 |
|
isa_membase = 0x10100000ULL; |
203 |
|
isa_irqbase = 8; |
204 |
break; |
break; |
205 |
case 120: |
case 120: |
206 |
|
/* EVBMIPS (Malta): */ |
207 |
d->type = PCI_PRODUCT_GALILEO_GT64120; |
d->type = PCI_PRODUCT_GALILEO_GT64120; |
208 |
|
pci_io_offset = 0; |
209 |
|
pci_mem_offset = 0; |
210 |
|
pci_portbase = 0x18000000ULL; |
211 |
|
pci_membase = 0x10000000ULL; |
212 |
|
pci_irqbase = 8; |
213 |
|
isa_portbase = 0x18000000ULL; |
214 |
|
isa_membase = 0x10000000ULL; |
215 |
|
isa_irqbase = 8; |
216 |
break; |
break; |
217 |
default:fatal("dev_gt_init(): type must be 11 or 120.\n"); |
default:fatal("dev_gt_init(): type must be 11 or 120.\n"); |
218 |
exit(1); |
exit(1); |
219 |
} |
} |
220 |
|
|
221 |
|
d->pci_data = bus_pci_init( |
222 |
|
pciirq, pci_io_offset, pci_mem_offset, |
223 |
|
pci_portbase, pci_membase, pci_irqbase, |
224 |
|
isa_portbase, isa_membase, isa_irqbase); |
225 |
|
|
226 |
/* |
/* |
227 |
* According to NetBSD/cobalt: |
* According to NetBSD/cobalt: |
228 |
* pchb0 at pci0 dev 0 function 0: Galileo GT-64011 |
* pchb0 at pci0 dev 0 function 0: Galileo GT-64011 |
229 |
* System Controller, rev 1 |
* System Controller, rev 1 |
230 |
*/ |
*/ |
231 |
bus_pci_add(machine, d->pci_data, mem, 0, 0, 0, pci_gt_init, |
bus_pci_add(machine, d->pci_data, mem, 0, 0, 0, |
232 |
d->type == PCI_PRODUCT_GALILEO_GT64011? |
d->type == PCI_PRODUCT_GALILEO_GT64011? "gt64011" : "gt64120"); |
|
pci_gt_rr_011 : pci_gt_rr_120); |
|
233 |
|
|
234 |
memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH, |
memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH, |
235 |
dev_gt_access, d, MEM_DEFAULT, NULL); |
dev_gt_access, d, DM_DEFAULT, NULL); |
236 |
machine_add_tickfunction(machine, dev_gt_tick, d, TICK_SHIFT); |
machine_add_tickfunction(machine, dev_gt_tick, d, TICK_SHIFT); |
237 |
|
|
238 |
return d->pci_data; |
return d->pci_data; |