25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: dev_gt.c,v 1.42 2006/07/21 16:55:41 debug Exp $ |
* $Id: dev_gt.c,v 1.43 2006/08/13 08:34:06 debug Exp $ |
29 |
* |
* |
30 |
* Galileo Technology GT-64xxx PCI controller. |
* Galileo Technology GT-64xxx PCI controller. |
31 |
* |
* |
32 |
* GT-64011 Used in Cobalt machines. |
* GT-64011 Used in Cobalt machines. |
33 |
* GT-64120 Used in evbmips machines (Malta). |
* GT-64120 Used in evbmips machines (Malta). |
34 |
* GT-64260 Used in mvmeppc machines. |
* GT-64260 Used in mvmeppc machines. |
|
* |
|
|
* TODO: This more or less just a dummy device, so far. It happens to work |
|
|
* with some NetBSD ports in some cases, and perhaps with Linux too, |
|
|
* but it is not really working for anything else. |
|
35 |
*/ |
*/ |
36 |
|
|
37 |
#include <stdio.h> |
#include <stdio.h> |
62 |
int pci_irqbase; |
int pci_irqbase; |
63 |
int type; |
int type; |
64 |
|
|
65 |
uint32_t pci0_iold; /* I/O Low Decode address */ |
/* Address decode registers: */ |
66 |
uint32_t pci0_iohd; /* I/O High Decode address */ |
uint32_t decode[GT_N_DECODE_REGS]; |
67 |
|
|
68 |
struct pci_data *pci_data; |
struct pci_data *pci_data; |
69 |
}; |
}; |
92 |
switch (relative_addr) { |
switch (relative_addr) { |
93 |
|
|
94 |
case GT_PCI0IOLD_OFS: |
case GT_PCI0IOLD_OFS: |
|
if (writeflag == MEM_READ) { |
|
|
odata = d->pci0_iold; |
|
|
} else { |
|
|
fatal("[ gt: write to GT_PCI0IOLD_OFS: 0x%x (TODO) ]\n", |
|
|
(int)idata); |
|
|
} |
|
|
break; |
|
|
|
|
95 |
case GT_PCI0IOHD_OFS: |
case GT_PCI0IOHD_OFS: |
96 |
|
case GT_PCI0M0LD_OFS: |
97 |
|
case GT_PCI0M0HD_OFS: |
98 |
|
case GT_PCI0M1LD_OFS: |
99 |
|
case GT_PCI0M1HD_OFS: |
100 |
|
case GT_PCI0IOREMAP_OFS: |
101 |
|
case GT_PCI0M0REMAP_OFS: |
102 |
|
case GT_PCI0M1REMAP_OFS: |
103 |
if (writeflag == MEM_READ) { |
if (writeflag == MEM_READ) { |
104 |
odata = d->pci0_iohd; |
odata = d->decode[relative_addr / 8]; |
105 |
|
debug("[ gt: read from offset 0x%x: 0x%x ]\n", |
106 |
|
(int)relative_addr, (int)odata); |
107 |
} else { |
} else { |
108 |
fatal("[ gt: write to GT_PCI0IOHD_OFS: 0x%x (TODO) ]\n", |
d->decode[relative_addr / 8] = idata; |
109 |
(int)idata); |
fatal("[ gt: write to offset 0x%x: 0x%x (TODO) ]\n", |
110 |
|
(int)relative_addr, (int)idata); |
111 |
} |
} |
112 |
break; |
break; |
113 |
|
|
114 |
case GT_PCI0IOREMAP_OFS: |
case GT_PCI0_CMD_OFS: |
115 |
/* TODO: Same as GT_PCI0IOLD_OFS? */ |
if (writeflag == MEM_WRITE) { |
116 |
if (writeflag == MEM_READ) { |
debug("[ gt: write to GT_PCI0_CMD: 0x%08x (TODO) ]\n", |
117 |
odata = d->pci0_iold; |
(int)idata); |
118 |
} else { |
} else { |
119 |
debug("[ gt: write to GT_PCI0IOREMAP_OFS: 0x%x " |
debug("[ gt: read from GT_PCI0_CMD (0x%08x) (TODO) ]\n", |
120 |
"(TODO) ]\n", (int)idata); |
(int)odata); |
121 |
} |
} |
122 |
break; |
break; |
123 |
|
|
180 |
/* |
/* |
181 |
* dev_gt_init(): |
* dev_gt_init(): |
182 |
* |
* |
183 |
* Initialize a GT device. Return a pointer to the pci_data used, so that |
* Initialize a Gallileo PCI controller device. First, the controller itself |
184 |
* the caller may add PCI devices. First, however, we add the GT device |
* is added to the bus, then a pointer to the bus is returned. |
|
* itself. |
|
185 |
*/ |
*/ |
186 |
struct pci_data *dev_gt_init(struct machine *machine, struct memory *mem, |
struct pci_data *dev_gt_init(struct machine *machine, struct memory *mem, |
187 |
uint64_t baseaddr, int irq_nr, int pciirq, int type) |
uint64_t baseaddr, int irq_nr, int pciirq, int type) |
245 |
exit(1); |
exit(1); |
246 |
} |
} |
247 |
|
|
248 |
|
|
249 |
d->pci_irqbase = pci_irqbase; |
d->pci_irqbase = pci_irqbase; |
250 |
d->pci0_iold = pci_portbase >> 21; |
|
251 |
d->pci0_iohd = 0x0000000f; /* TODO? */ |
/* |
252 |
|
* TODO: FIX THESE! Hardcoded numbers = bad. |
253 |
|
*/ |
254 |
|
d->decode[GT_PCI0IOLD_OFS / 8] = pci_portbase >> 21; |
255 |
|
d->decode[GT_PCI0IOHD_OFS / 8] = 0x40; |
256 |
|
d->decode[GT_PCI0M0LD_OFS / 8] = 0x80; |
257 |
|
d->decode[GT_PCI0M0HD_OFS / 8] = 0x3f; |
258 |
|
d->decode[GT_PCI0M1LD_OFS / 8] = 0xc1; |
259 |
|
d->decode[GT_PCI0M1HD_OFS / 8] = 0x5e; |
260 |
|
d->decode[GT_PCI0IOREMAP_OFS / 8] = d->decode[GT_PCI0IOLD_OFS / 8]; |
261 |
|
d->decode[GT_PCI0M0REMAP_OFS / 8] = d->decode[GT_PCI0M0LD_OFS / 8]; |
262 |
|
d->decode[GT_PCI0M1REMAP_OFS / 8] = d->decode[GT_PCI0M1LD_OFS / 8]; |
263 |
|
|
264 |
d->pci_data = bus_pci_init(machine, |
d->pci_data = bus_pci_init(machine, |
265 |
pciirq, pci_io_offset, pci_mem_offset, |
pciirq, pci_io_offset, pci_mem_offset, |