25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: dev_gt.c,v 1.40 2006/01/14 11:29:36 debug Exp $ |
* $Id: dev_gt.c,v 1.42 2006/07/21 16:55:41 debug Exp $ |
29 |
* |
* |
30 |
* Galileo Technology GT-64xxx PCI controller. |
* Galileo Technology GT-64xxx PCI controller. |
31 |
* |
* |
49 |
#include "memory.h" |
#include "memory.h" |
50 |
#include "misc.h" |
#include "misc.h" |
51 |
|
|
52 |
|
#include "gtreg.h" |
53 |
|
|
54 |
|
|
55 |
#define TICK_SHIFT 14 |
#define TICK_SHIFT 14 |
56 |
|
|
60 |
#define PCI_PRODUCT_GALILEO_GT64120 0x4620 /* GT-64120 */ |
#define PCI_PRODUCT_GALILEO_GT64120 0x4620 /* GT-64120 */ |
61 |
#define PCI_PRODUCT_GALILEO_GT64260 0x6430 /* GT-64260 */ |
#define PCI_PRODUCT_GALILEO_GT64260 0x6430 /* GT-64260 */ |
62 |
|
|
63 |
|
|
64 |
struct gt_data { |
struct gt_data { |
65 |
int irqnr; |
int timer0_irqnr; |
66 |
int pciirq; |
int pci_irqbase; |
67 |
int type; |
int type; |
68 |
|
|
69 |
|
uint32_t pci0_iold; /* I/O Low Decode address */ |
70 |
|
uint32_t pci0_iohd; /* I/O High Decode address */ |
71 |
|
|
72 |
struct pci_data *pci_data; |
struct pci_data *pci_data; |
73 |
}; |
}; |
74 |
|
|
75 |
|
|
76 |
/* |
DEVICE_TICK(gt) |
|
* dev_gt_tick(): |
|
|
*/ |
|
|
void dev_gt_tick(struct cpu *cpu, void *extra) |
|
77 |
{ |
{ |
78 |
struct gt_data *gt_data = extra; |
struct gt_data *gt_data = extra; |
79 |
|
|
80 |
cpu_interrupt(cpu, gt_data->irqnr); |
/* TODO: Implement real timer interrupts. */ |
81 |
|
|
82 |
|
cpu_interrupt(cpu, gt_data->timer0_irqnr); |
83 |
} |
} |
84 |
|
|
85 |
|
|
|
/* |
|
|
* dev_gt_access(): |
|
|
*/ |
|
86 |
DEVICE_ACCESS(gt) |
DEVICE_ACCESS(gt) |
87 |
{ |
{ |
88 |
uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
95 |
|
|
96 |
switch (relative_addr) { |
switch (relative_addr) { |
97 |
|
|
98 |
case 0x48: |
case GT_PCI0IOLD_OFS: |
99 |
switch (d->type) { |
if (writeflag == MEM_READ) { |
100 |
case PCI_PRODUCT_GALILEO_GT64120: |
odata = d->pci0_iold; |
101 |
/* |
} else { |
102 |
* This is needed for Linux on Malta, according |
fatal("[ gt: write to GT_PCI0IOLD_OFS: 0x%x (TODO) ]\n", |
103 |
* to Alec Voropay. (TODO: Remove this hack when |
(int)idata); |
|
* things have stabilized.) |
|
|
*/ |
|
|
if (writeflag == MEM_READ) { |
|
|
odata = 0x18000000 >> 21; |
|
|
debug("[ gt: read from 0x48: 0x%08x ]\n", |
|
|
(int)odata); |
|
|
} |
|
|
break; |
|
|
default: |
|
|
fatal("[ gt: access to 0x48? (type %i) ]\n", d->type); |
|
104 |
} |
} |
105 |
break; |
break; |
106 |
|
|
107 |
case 0xc18: |
case GT_PCI0IOHD_OFS: |
108 |
|
if (writeflag == MEM_READ) { |
109 |
|
odata = d->pci0_iohd; |
110 |
|
} else { |
111 |
|
fatal("[ gt: write to GT_PCI0IOHD_OFS: 0x%x (TODO) ]\n", |
112 |
|
(int)idata); |
113 |
|
} |
114 |
|
break; |
115 |
|
|
116 |
|
case GT_PCI0IOREMAP_OFS: |
117 |
|
/* TODO: Same as GT_PCI0IOLD_OFS? */ |
118 |
|
if (writeflag == MEM_READ) { |
119 |
|
odata = d->pci0_iold; |
120 |
|
} else { |
121 |
|
debug("[ gt: write to GT_PCI0IOREMAP_OFS: 0x%x " |
122 |
|
"(TODO) ]\n", (int)idata); |
123 |
|
} |
124 |
|
break; |
125 |
|
|
126 |
|
case GT_INTR_CAUSE: |
127 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
128 |
debug("[ gt: write to 0xc18: 0x%08x ]\n", (int)idata); |
debug("[ gt: write to GT_INTR_CAUSE: 0x%08x ]\n", |
129 |
|
(int)idata); |
130 |
return 1; |
return 1; |
131 |
} else { |
} else { |
132 |
odata = 0xffffffffULL; |
odata = GTIC_T0EXP; |
133 |
/* |
cpu_interrupt_ack(cpu, d->timer0_irqnr); |
|
* ??? interrupt something... |
|
|
* |
|
|
* TODO: Remove this hack when things have stabilized. |
|
|
*/ |
|
|
odata = 0x00000100; |
|
|
/* netbsd/cobalt cobalt/machdep.c:cpu_intr() */ |
|
|
|
|
|
cpu_interrupt_ack(cpu, d->irqnr); |
|
134 |
|
|
135 |
debug("[ gt: read from 0xc18 (0x%08x) ]\n", (int)odata); |
debug("[ gt: read from GT_INTR_CAUSE (0x%08x) ]\n", |
136 |
|
(int)odata); |
137 |
} |
} |
138 |
break; |
break; |
139 |
|
|
140 |
case 0xc34: /* GT_PCI0_INTR_ACK */ |
case GT_PCI0_INTR_ACK: |
141 |
odata = cpu->machine->isa_pic_data.last_int; |
odata = cpu->machine->isa_pic_data.last_int; |
142 |
cpu_interrupt_ack(cpu, 8 + odata); |
cpu_interrupt_ack(cpu, d->pci_irqbase + odata); |
143 |
break; |
break; |
144 |
|
|
145 |
case 0xcf8: /* PCI ADDR */ |
case GT_PCI0_CFG_ADDR: |
146 |
if (cpu->byte_order != EMUL_LITTLE_ENDIAN) { |
if (cpu->byte_order != EMUL_LITTLE_ENDIAN) { |
147 |
fatal("[ gt: TODO: big endian PCI access ]\n"); |
fatal("[ gt: TODO: big endian PCI access ]\n"); |
148 |
exit(1); |
exit(1); |
151 |
bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg); |
bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg); |
152 |
break; |
break; |
153 |
|
|
154 |
case 0xcfc: /* PCI DATA */ |
case GT_PCI0_CFG_DATA: |
155 |
if (cpu->byte_order != EMUL_LITTLE_ENDIAN) { |
if (cpu->byte_order != EMUL_LITTLE_ENDIAN) { |
156 |
fatal("[ gt: TODO: big endian PCI access ]\n"); |
fatal("[ gt: TODO: big endian PCI access ]\n"); |
157 |
exit(1); |
exit(1); |
202 |
exit(1); |
exit(1); |
203 |
} |
} |
204 |
memset(d, 0, sizeof(struct gt_data)); |
memset(d, 0, sizeof(struct gt_data)); |
205 |
d->irqnr = irq_nr; |
d->timer0_irqnr = irq_nr; |
|
d->pciirq = pciirq; |
|
206 |
|
|
207 |
switch (type) { |
switch (type) { |
208 |
case 11: |
case 11: |
213 |
pci_mem_offset = 0; |
pci_mem_offset = 0; |
214 |
pci_portbase = 0x10000000ULL; |
pci_portbase = 0x10000000ULL; |
215 |
pci_membase = 0x10100000ULL; |
pci_membase = 0x10100000ULL; |
216 |
pci_irqbase = 0; |
pci_irqbase = 8; |
217 |
isa_portbase = 0x10000000ULL; |
isa_portbase = 0x10000000ULL; |
218 |
isa_membase = 0x10100000ULL; |
isa_membase = 0x10100000ULL; |
219 |
isa_irqbase = 8; |
isa_irqbase = 8; |
248 |
exit(1); |
exit(1); |
249 |
} |
} |
250 |
|
|
251 |
|
d->pci_irqbase = pci_irqbase; |
252 |
|
d->pci0_iold = pci_portbase >> 21; |
253 |
|
d->pci0_iohd = 0x0000000f; /* TODO? */ |
254 |
|
|
255 |
d->pci_data = bus_pci_init(machine, |
d->pci_data = bus_pci_init(machine, |
256 |
pciirq, pci_io_offset, pci_mem_offset, |
pciirq, pci_io_offset, pci_mem_offset, |
257 |
pci_portbase, pci_membase, pci_irqbase, |
pci_portbase, pci_membase, pci_irqbase, |
266 |
|
|
267 |
memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH, |
memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH, |
268 |
dev_gt_access, d, DM_DEFAULT, NULL); |
dev_gt_access, d, DM_DEFAULT, NULL); |
269 |
machine_add_tickfunction(machine, dev_gt_tick, d, TICK_SHIFT); |
machine_add_tickfunction(machine, dev_gt_tick, d, TICK_SHIFT, 0.0); |
270 |
|
|
271 |
return d->pci_data; |
return d->pci_data; |
272 |
} |
} |