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/* |
/* |
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* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: dev_gt.c,v 1.35 2005/11/21 09:17:26 debug Exp $ |
* $Id: dev_gt.c,v 1.40 2006/01/14 11:29:36 debug Exp $ |
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* |
* |
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* Galileo Technology GT-64xxx PCI controller. |
* Galileo Technology GT-64xxx PCI controller. |
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* |
* |
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* GT-64011 Used in Cobalt machines. |
* GT-64011 Used in Cobalt machines. |
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* GT-64120 Used in evbmips machines (Malta). |
* GT-64120 Used in evbmips machines (Malta). |
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|
* GT-64260 Used in mvmeppc machines. |
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* |
* |
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* TODO: This more or less just a dummy device, so far. It happens to work |
* TODO: This more or less just a dummy device, so far. It happens to work |
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* with NetBSD/cobalt and /evbmips, and in some cases it might happen |
* with some NetBSD ports in some cases, and perhaps with Linux too, |
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* to work with Linux as well, but don't rely on it for anything else. |
* but it is not really working for anything else. |
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*/ |
*/ |
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#include <stdio.h> |
#include <stdio.h> |
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#define PCI_PRODUCT_GALILEO_GT64011 0x4146 /* GT-64011 */ |
#define PCI_PRODUCT_GALILEO_GT64011 0x4146 /* GT-64011 */ |
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#define PCI_PRODUCT_GALILEO_GT64120 0x4620 /* GT-64120 */ |
#define PCI_PRODUCT_GALILEO_GT64120 0x4620 /* GT-64120 */ |
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#define PCI_PRODUCT_GALILEO_GT64260 0x6430 /* GT-64260 */ |
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struct gt_data { |
struct gt_data { |
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int irqnr; |
int irqnr; |
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/* |
/* |
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* dev_gt_access(): |
* dev_gt_access(): |
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*/ |
*/ |
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int dev_gt_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, |
DEVICE_ACCESS(gt) |
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unsigned char *data, size_t len, int writeflag, void *extra) |
|
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{ |
{ |
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uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
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int i; |
int bus, dev, func, reg; |
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size_t i; |
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struct gt_data *d = extra; |
struct gt_data *d = extra; |
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if (writeflag == MEM_WRITE) |
if (writeflag == MEM_WRITE) |
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break; |
break; |
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case 0xcf8: /* PCI ADDR */ |
case 0xcf8: /* PCI ADDR */ |
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if (cpu->byte_order != EMUL_LITTLE_ENDIAN) { |
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fatal("[ gt: TODO: big endian PCI access ]\n"); |
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exit(1); |
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} |
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bus_pci_decompose_1(idata, &bus, &dev, &func, ®); |
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bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg); |
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break; |
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case 0xcfc: /* PCI DATA */ |
case 0xcfc: /* PCI DATA */ |
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if (writeflag == MEM_WRITE) { |
if (cpu->byte_order != EMUL_LITTLE_ENDIAN) { |
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bus_pci_access(cpu, mem, relative_addr, &idata, |
fatal("[ gt: TODO: big endian PCI access ]\n"); |
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len, writeflag, d->pci_data); |
exit(1); |
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} else { |
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bus_pci_access(cpu, mem, relative_addr, &odata, |
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len, writeflag, d->pci_data); |
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} |
} |
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bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ? |
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&odata : &idata, len, writeflag); |
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break; |
break; |
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default: |
default: |
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if (writeflag == MEM_READ) { |
if (writeflag == MEM_READ) { |
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debug("[ gt: read from addr 0x%x ]\n", |
debug("[ gt: read from addr 0x%x ]\n", |
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uint64_t isa_portbase = 0, isa_membase = 0; |
uint64_t isa_portbase = 0, isa_membase = 0; |
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int isa_irqbase = 0, pci_irqbase = 0; |
int isa_irqbase = 0, pci_irqbase = 0; |
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uint64_t pci_io_offset = 0, pci_mem_offset = 0; |
uint64_t pci_io_offset = 0, pci_mem_offset = 0; |
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char *gt_name = "NO"; |
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d = malloc(sizeof(struct gt_data)); |
d = malloc(sizeof(struct gt_data)); |
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if (d == NULL) { |
if (d == NULL) { |
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case 11: |
case 11: |
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/* Cobalt: */ |
/* Cobalt: */ |
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d->type = PCI_PRODUCT_GALILEO_GT64011; |
d->type = PCI_PRODUCT_GALILEO_GT64011; |
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gt_name = "gt64011"; |
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pci_io_offset = 0; |
pci_io_offset = 0; |
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pci_mem_offset = 0; |
pci_mem_offset = 0; |
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pci_portbase = 0x10000000ULL; |
pci_portbase = 0x10000000ULL; |
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case 120: |
case 120: |
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/* EVBMIPS (Malta): */ |
/* EVBMIPS (Malta): */ |
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d->type = PCI_PRODUCT_GALILEO_GT64120; |
d->type = PCI_PRODUCT_GALILEO_GT64120; |
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gt_name = "gt64120"; |
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pci_io_offset = 0; |
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pci_mem_offset = 0; |
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pci_portbase = 0x18000000ULL; |
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pci_membase = 0x10000000ULL; |
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pci_irqbase = 8; |
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isa_portbase = 0x18000000ULL; |
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isa_membase = 0x10000000ULL; |
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isa_irqbase = 8; |
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break; |
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case 260: |
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/* MVMEPPC (mvme5500): */ |
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d->type = PCI_PRODUCT_GALILEO_GT64260; |
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gt_name = "gt64260"; |
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pci_io_offset = 0; |
pci_io_offset = 0; |
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pci_mem_offset = 0; |
pci_mem_offset = 0; |
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pci_portbase = 0x18000000ULL; |
pci_portbase = 0x18000000ULL; |
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isa_membase = 0x10000000ULL; |
isa_membase = 0x10000000ULL; |
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isa_irqbase = 8; |
isa_irqbase = 8; |
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break; |
break; |
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default:fatal("dev_gt_init(): type must be 11 or 120.\n"); |
default:fatal("dev_gt_init(): unimplemented GT type (%i).\n", type); |
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exit(1); |
exit(1); |
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} |
} |
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|
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d->pci_data = bus_pci_init( |
d->pci_data = bus_pci_init(machine, |
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pciirq, pci_io_offset, pci_mem_offset, |
pciirq, pci_io_offset, pci_mem_offset, |
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pci_portbase, pci_membase, pci_irqbase, |
pci_portbase, pci_membase, pci_irqbase, |
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isa_portbase, isa_membase, isa_irqbase); |
isa_portbase, isa_membase, isa_irqbase); |
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* pchb0 at pci0 dev 0 function 0: Galileo GT-64011 |
* pchb0 at pci0 dev 0 function 0: Galileo GT-64011 |
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* System Controller, rev 1 |
* System Controller, rev 1 |
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*/ |
*/ |
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bus_pci_add(machine, d->pci_data, mem, 0, 0, 0, |
bus_pci_add(machine, d->pci_data, mem, 0, 0, 0, gt_name); |
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d->type == PCI_PRODUCT_GALILEO_GT64011? "gt64011" : "gt64120"); |
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memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH, |
memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH, |
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dev_gt_access, d, DM_DEFAULT, NULL); |
dev_gt_access, d, DM_DEFAULT, NULL); |