25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: dev_gt.c,v 1.21 2005/03/18 23:20:52 debug Exp $ |
* $Id: dev_gt.c,v 1.26 2005/08/05 07:50:37 debug Exp $ |
29 |
* |
* |
30 |
* The "gt" device used in Cobalt machines. |
* Galileo Technology GT-64xxx PCI controller. |
31 |
* |
* |
32 |
* TODO: This more or less just a dummy device, so far. |
* GT-64011 Used in Cobalt machines. |
33 |
|
* GT-64120 Used in evbmips machines (Malta). |
34 |
|
* |
35 |
|
* TODO: This more or less just a dummy device, so far. It happens to work |
36 |
|
* with NetBSD/cobalt and /evbmips, and in some cases it might happen |
37 |
|
* to work with Linux as well, but don't rely on it for anything else. |
38 |
*/ |
*/ |
39 |
|
|
40 |
#include <stdio.h> |
#include <stdio.h> |
49 |
#include "misc.h" |
#include "misc.h" |
50 |
|
|
51 |
|
|
52 |
#define TICK_STEPS_SHIFT 16 |
#define TICK_SHIFT 14 |
53 |
|
|
54 |
|
/* #define debug fatal */ |
55 |
|
|
56 |
#define PCI_VENDOR_GALILEO 0x11ab /* Galileo Technology */ |
#define PCI_VENDOR_GALILEO 0x11ab /* Galileo Technology */ |
57 |
#define PCI_PRODUCT_GALILEO_GT64011 0x4146 /* GT-64011 System Controller */ |
#define PCI_PRODUCT_GALILEO_GT64011 0x4146 /* GT-64011 System Controller */ |
58 |
|
#define PCI_PRODUCT_GALILEO_GT64120 0x4620 /* GT-64120 */ |
59 |
|
|
60 |
struct gt_data { |
struct gt_data { |
|
int reg[8]; |
|
61 |
int irqnr; |
int irqnr; |
62 |
int pciirq; |
int pciirq; |
63 |
|
int type; |
64 |
|
|
65 |
struct pci_data *pci_data; |
struct pci_data *pci_data; |
66 |
}; |
}; |
84 |
unsigned char *data, size_t len, int writeflag, void *extra) |
unsigned char *data, size_t len, int writeflag, void *extra) |
85 |
{ |
{ |
86 |
uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
87 |
int i; |
int i, asserted; |
88 |
struct gt_data *d = extra; |
struct gt_data *d = extra; |
89 |
|
|
90 |
idata = memory_readmax64(cpu, data, len); |
idata = memory_readmax64(cpu, data, len); |
91 |
|
|
92 |
switch (relative_addr) { |
switch (relative_addr) { |
93 |
|
|
94 |
|
case 0x48: |
95 |
|
switch (d->type) { |
96 |
|
case PCI_PRODUCT_GALILEO_GT64120: |
97 |
|
/* |
98 |
|
* This is needed for Linux on Malta, according |
99 |
|
* to Alec Voropay. (TODO: Remove this hack when |
100 |
|
* things have stabilized.) |
101 |
|
*/ |
102 |
|
if (writeflag == MEM_READ) { |
103 |
|
odata = 0x18000000 >> 21; |
104 |
|
debug("[ gt: read from 0x48: 0x%08x ]\n", |
105 |
|
(int)odata); |
106 |
|
} |
107 |
|
break; |
108 |
|
default: |
109 |
|
fatal("[ gt: access to 0x48? (type %i) ]\n", d->type); |
110 |
|
} |
111 |
|
break; |
112 |
|
|
113 |
case 0xc18: |
case 0xc18: |
114 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
115 |
debug("[ gt write to 0xc18: data = 0x%08lx ]\n", |
debug("[ gt: write to 0xc18: 0x%08x ]\n", (int)idata); |
|
(long)idata); |
|
116 |
return 1; |
return 1; |
117 |
} else { |
} else { |
118 |
odata = 0xffffffffULL; |
odata = 0xffffffffULL; |
119 |
/* ??? interrupt something... */ |
/* ??? interrupt something... */ |
120 |
|
|
121 |
|
/* |
122 |
|
* TODO: Remove this hack when things have stabilized. |
123 |
|
*/ |
124 |
odata = 0x00000100; /* netbsd/cobalt cobalt/machdep.c:cpu_intr() */ |
odata = 0x00000100; /* netbsd/cobalt cobalt/machdep.c:cpu_intr() */ |
125 |
|
|
126 |
cpu_interrupt_ack(cpu, d->irqnr); |
cpu_interrupt_ack(cpu, d->irqnr); |
127 |
|
|
128 |
debug("[ gt read from 0xc18 (data = 0x%08lx) ]\n", |
debug("[ gt: read from 0xc18 (0x%08x) ]\n", (int)odata); |
|
(long)odata); |
|
129 |
} |
} |
130 |
break; |
break; |
131 |
|
|
132 |
|
case 0xc34: /* GT_PCI0_INTR_ACK */ |
133 |
|
/* |
134 |
|
* Ugly hack, which works for at least evbmips/Malta: |
135 |
|
*/ |
136 |
|
asserted = |
137 |
|
(cpu->machine->md_int.isa_pic_data.pic1->irr & |
138 |
|
~cpu->machine->md_int.isa_pic_data.pic1->ier) | |
139 |
|
((cpu->machine->md_int.isa_pic_data.pic2->irr & |
140 |
|
~cpu->machine->md_int.isa_pic_data.pic2->ier) << 8); |
141 |
|
odata = 7; /* "Spurious interrupt" defaults to 7. */ |
142 |
|
for (i=0; i<16; i++) |
143 |
|
if ((asserted >> i) & 1) { |
144 |
|
odata = i; |
145 |
|
break; |
146 |
|
} |
147 |
|
break; |
148 |
|
|
149 |
case 0xcf8: /* PCI ADDR */ |
case 0xcf8: /* PCI ADDR */ |
150 |
case 0xcfc: /* PCI DATA */ |
case 0xcfc: /* PCI DATA */ |
151 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
158 |
break; |
break; |
159 |
default: |
default: |
160 |
if (writeflag==MEM_READ) { |
if (writeflag==MEM_READ) { |
161 |
debug("[ gt read from addr 0x%x ]\n", |
debug("[ gt: read from addr 0x%x ]\n", |
162 |
(int)relative_addr); |
(int)relative_addr); |
|
odata = d->reg[relative_addr]; |
|
163 |
} else { |
} else { |
164 |
debug("[ gt write to addr 0x%x:", (int)relative_addr); |
debug("[ gt: write to addr 0x%x:", (int)relative_addr); |
165 |
for (i=0; i<len; i++) |
for (i=0; i<len; i++) |
166 |
debug(" %02x", data[i]); |
debug(" %02x", data[i]); |
167 |
debug(" ]\n"); |
debug(" ]\n"); |
|
d->reg[relative_addr] = idata; |
|
168 |
} |
} |
169 |
} |
} |
170 |
|
|
176 |
|
|
177 |
|
|
178 |
/* |
/* |
179 |
* pci_gt_rr(): |
* pci_gt_rr_011(): |
180 |
*/ |
*/ |
181 |
uint32_t pci_gt_rr(int reg) |
static uint32_t pci_gt_rr_011(int reg) |
182 |
{ |
{ |
183 |
switch (reg) { |
switch (reg) { |
184 |
case 0x00: |
case 0x00: |
185 |
return PCI_VENDOR_GALILEO + (PCI_PRODUCT_GALILEO_GT64011 << 16); |
return PCI_VENDOR_GALILEO + (PCI_PRODUCT_GALILEO_GT64011 << 16); |
186 |
case 0x08: |
case 0x08: |
187 |
return 0x01; /* Revision 1 */ |
return 0x06000001; /* Revision 1 */ |
188 |
|
default: |
189 |
|
return 0; |
190 |
|
} |
191 |
|
} |
192 |
|
|
193 |
|
|
194 |
|
/* |
195 |
|
* pci_gt_rr_120(): |
196 |
|
*/ |
197 |
|
static uint32_t pci_gt_rr_120(int reg) |
198 |
|
{ |
199 |
|
switch (reg) { |
200 |
|
case 0x00: |
201 |
|
return PCI_VENDOR_GALILEO + (PCI_PRODUCT_GALILEO_GT64120 << 16); |
202 |
|
case 0x08: |
203 |
|
return 0x06000002; /* Revision 2? */ |
204 |
default: |
default: |
205 |
return 0; |
return 0; |
206 |
} |
} |
223 |
* itself. |
* itself. |
224 |
*/ |
*/ |
225 |
struct pci_data *dev_gt_init(struct machine *machine, struct memory *mem, |
struct pci_data *dev_gt_init(struct machine *machine, struct memory *mem, |
226 |
uint64_t baseaddr, int irq_nr, int pciirq) |
uint64_t baseaddr, int irq_nr, int pciirq, int type) |
227 |
{ |
{ |
228 |
struct gt_data *d; |
struct gt_data *d; |
229 |
|
|
237 |
d->pciirq = pciirq; |
d->pciirq = pciirq; |
238 |
d->pci_data = bus_pci_init(pciirq); |
d->pci_data = bus_pci_init(pciirq); |
239 |
|
|
240 |
|
switch (type) { |
241 |
|
case 11: |
242 |
|
d->type = PCI_PRODUCT_GALILEO_GT64011; |
243 |
|
break; |
244 |
|
case 120: |
245 |
|
d->type = PCI_PRODUCT_GALILEO_GT64120; |
246 |
|
break; |
247 |
|
default:fatal("dev_gt_init(): type must be 11 or 120.\n"); |
248 |
|
exit(1); |
249 |
|
} |
250 |
|
|
251 |
/* |
/* |
252 |
* According to NetBSD/cobalt: |
* According to NetBSD/cobalt: |
253 |
* pchb0 at pci0 dev 0 function 0: Galileo GT-64011 |
* pchb0 at pci0 dev 0 function 0: Galileo GT-64011 |
254 |
* System Controller, rev 1 |
* System Controller, rev 1 |
255 |
*/ |
*/ |
256 |
bus_pci_add(machine, d->pci_data, mem, 0, 0, 0, pci_gt_init, pci_gt_rr); |
bus_pci_add(machine, d->pci_data, mem, 0, 0, 0, pci_gt_init, |
257 |
|
d->type == PCI_PRODUCT_GALILEO_GT64011? |
258 |
|
pci_gt_rr_011 : pci_gt_rr_120); |
259 |
|
|
260 |
memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH, |
memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH, |
261 |
dev_gt_access, d, MEM_DEFAULT, NULL); |
dev_gt_access, d, MEM_DEFAULT, NULL); |
262 |
machine_add_tickfunction(machine, dev_gt_tick, d, TICK_STEPS_SHIFT); |
machine_add_tickfunction(machine, dev_gt_tick, d, TICK_SHIFT); |
263 |
|
|
264 |
return d->pci_data; |
return d->pci_data; |
265 |
} |
} |