/[gxemul]/trunk/src/devices/dev_gt.c
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revision 21 by dpavlin, Mon Oct 8 16:19:23 2007 UTC revision 22 by dpavlin, Mon Oct 8 16:19:37 2007 UTC
# Line 1  Line 1 
1  /*  /*
2   *  Copyright (C) 2003-2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2003-2006  Anders Gavare.  All rights reserved.
3   *   *
4   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
5   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 25  Line 25 
25   *  SUCH DAMAGE.   *  SUCH DAMAGE.
26   *     *  
27   *   *
28   *  $Id: dev_gt.c,v 1.35 2005/11/21 09:17:26 debug Exp $   *  $Id: dev_gt.c,v 1.40 2006/01/14 11:29:36 debug Exp $
29   *     *  
30   *  Galileo Technology GT-64xxx PCI controller.   *  Galileo Technology GT-64xxx PCI controller.
31   *   *
32   *      GT-64011        Used in Cobalt machines.   *      GT-64011        Used in Cobalt machines.
33   *      GT-64120        Used in evbmips machines (Malta).   *      GT-64120        Used in evbmips machines (Malta).
34     *      GT-64260        Used in mvmeppc machines.
35   *   *
36   *  TODO: This more or less just a dummy device, so far. It happens to work   *  TODO: This more or less just a dummy device, so far. It happens to work
37   *        with NetBSD/cobalt and /evbmips, and in some cases it might happen   *        with some NetBSD ports in some cases, and perhaps with Linux too,
38   *        to work with Linux as well, but don't rely on it for anything else.   *        but it is not really working for anything else.
39   */   */
40    
41  #include <stdio.h>  #include <stdio.h>
# Line 55  Line 56 
56    
57  #define PCI_PRODUCT_GALILEO_GT64011  0x4146    /*  GT-64011  */  #define PCI_PRODUCT_GALILEO_GT64011  0x4146    /*  GT-64011  */
58  #define PCI_PRODUCT_GALILEO_GT64120  0x4620    /*  GT-64120  */  #define PCI_PRODUCT_GALILEO_GT64120  0x4620    /*  GT-64120  */
59    #define PCI_PRODUCT_GALILEO_GT64260  0x6430    /*  GT-64260  */
60    
61  struct gt_data {  struct gt_data {
62          int     irqnr;          int     irqnr;
# Line 79  void dev_gt_tick(struct cpu *cpu, void * Line 81  void dev_gt_tick(struct cpu *cpu, void *
81  /*  /*
82   *  dev_gt_access():   *  dev_gt_access():
83   */   */
84  int dev_gt_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr,  DEVICE_ACCESS(gt)
         unsigned char *data, size_t len, int writeflag, void *extra)  
85  {  {
86          uint64_t idata = 0, odata = 0;          uint64_t idata = 0, odata = 0;
87          int i;          int bus, dev, func, reg;
88            size_t i;
89          struct gt_data *d = extra;          struct gt_data *d = extra;
90    
91          if (writeflag == MEM_WRITE)          if (writeflag == MEM_WRITE)
# Line 136  int dev_gt_access(struct cpu *cpu, struc Line 138  int dev_gt_access(struct cpu *cpu, struc
138                  break;                  break;
139    
140          case 0xcf8:     /*  PCI ADDR  */          case 0xcf8:     /*  PCI ADDR  */
141                    if (cpu->byte_order != EMUL_LITTLE_ENDIAN) {
142                            fatal("[ gt: TODO: big endian PCI access ]\n");
143                            exit(1);
144                    }
145                    bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
146                    bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
147                    break;
148    
149          case 0xcfc:     /*  PCI DATA  */          case 0xcfc:     /*  PCI DATA  */
150                  if (writeflag == MEM_WRITE) {                  if (cpu->byte_order != EMUL_LITTLE_ENDIAN) {
151                          bus_pci_access(cpu, mem, relative_addr, &idata,                          fatal("[ gt: TODO: big endian PCI access ]\n");
152                              len, writeflag, d->pci_data);                          exit(1);
                 } else {  
                         bus_pci_access(cpu, mem, relative_addr, &odata,  
                             len, writeflag, d->pci_data);  
153                  }                  }
154                    bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
155                        &odata : &idata, len, writeflag);
156                  break;                  break;
157    
158          default:          default:
159                  if (writeflag == MEM_READ) {                  if (writeflag == MEM_READ) {
160                          debug("[ gt: read from addr 0x%x ]\n",                          debug("[ gt: read from addr 0x%x ]\n",
# Line 179  struct pci_data *dev_gt_init(struct mach Line 189  struct pci_data *dev_gt_init(struct mach
189          uint64_t isa_portbase = 0, isa_membase = 0;          uint64_t isa_portbase = 0, isa_membase = 0;
190          int isa_irqbase = 0, pci_irqbase = 0;          int isa_irqbase = 0, pci_irqbase = 0;
191          uint64_t pci_io_offset = 0, pci_mem_offset = 0;          uint64_t pci_io_offset = 0, pci_mem_offset = 0;
192            char *gt_name = "NO";
193    
194          d = malloc(sizeof(struct gt_data));          d = malloc(sizeof(struct gt_data));
195          if (d == NULL) {          if (d == NULL) {
# Line 193  struct pci_data *dev_gt_init(struct mach Line 204  struct pci_data *dev_gt_init(struct mach
204          case 11:          case 11:
205                  /*  Cobalt:  */                  /*  Cobalt:  */
206                  d->type = PCI_PRODUCT_GALILEO_GT64011;                  d->type = PCI_PRODUCT_GALILEO_GT64011;
207                    gt_name = "gt64011";
208                  pci_io_offset = 0;                  pci_io_offset = 0;
209                  pci_mem_offset = 0;                  pci_mem_offset = 0;
210                  pci_portbase = 0x10000000ULL;                  pci_portbase = 0x10000000ULL;
# Line 205  struct pci_data *dev_gt_init(struct mach Line 217  struct pci_data *dev_gt_init(struct mach
217          case 120:          case 120:
218                  /*  EVBMIPS (Malta):  */                  /*  EVBMIPS (Malta):  */
219                  d->type = PCI_PRODUCT_GALILEO_GT64120;                  d->type = PCI_PRODUCT_GALILEO_GT64120;
220                    gt_name = "gt64120";
221                    pci_io_offset = 0;
222                    pci_mem_offset = 0;
223                    pci_portbase = 0x18000000ULL;
224                    pci_membase = 0x10000000ULL;
225                    pci_irqbase = 8;
226                    isa_portbase = 0x18000000ULL;
227                    isa_membase = 0x10000000ULL;
228                    isa_irqbase = 8;
229                    break;
230            case 260:
231                    /*  MVMEPPC (mvme5500):  */
232                    d->type = PCI_PRODUCT_GALILEO_GT64260;
233                    gt_name = "gt64260";
234                  pci_io_offset = 0;                  pci_io_offset = 0;
235                  pci_mem_offset = 0;                  pci_mem_offset = 0;
236                  pci_portbase = 0x18000000ULL;                  pci_portbase = 0x18000000ULL;
# Line 214  struct pci_data *dev_gt_init(struct mach Line 240  struct pci_data *dev_gt_init(struct mach
240                  isa_membase = 0x10000000ULL;                  isa_membase = 0x10000000ULL;
241                  isa_irqbase = 8;                  isa_irqbase = 8;
242                  break;                  break;
243          default:fatal("dev_gt_init(): type must be 11 or 120.\n");          default:fatal("dev_gt_init(): unimplemented GT type (%i).\n", type);
244                  exit(1);                  exit(1);
245          }          }
246    
247          d->pci_data = bus_pci_init(          d->pci_data = bus_pci_init(machine,
248              pciirq, pci_io_offset, pci_mem_offset,              pciirq, pci_io_offset, pci_mem_offset,
249              pci_portbase, pci_membase, pci_irqbase,              pci_portbase, pci_membase, pci_irqbase,
250              isa_portbase, isa_membase, isa_irqbase);              isa_portbase, isa_membase, isa_irqbase);
# Line 228  struct pci_data *dev_gt_init(struct mach Line 254  struct pci_data *dev_gt_init(struct mach
254           *  pchb0 at pci0 dev 0 function 0: Galileo GT-64011           *  pchb0 at pci0 dev 0 function 0: Galileo GT-64011
255           *  System Controller, rev 1           *  System Controller, rev 1
256           */           */
257          bus_pci_add(machine, d->pci_data, mem, 0, 0, 0,          bus_pci_add(machine, d->pci_data, mem, 0, 0, 0, gt_name);
             d->type == PCI_PRODUCT_GALILEO_GT64011? "gt64011" : "gt64120");  
258    
259          memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH,          memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH,
260              dev_gt_access, d, DM_DEFAULT, NULL);              dev_gt_access, d, DM_DEFAULT, NULL);

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