25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: dev_gt.c,v 1.22 2005/06/20 08:19:58 debug Exp $ |
* $Id: dev_gt.c,v 1.28 2005/10/26 14:37:04 debug Exp $ |
29 |
* |
* |
30 |
* Galileo Technology GT-64xxx PCI controller. |
* Galileo Technology GT-64xxx PCI controller. |
31 |
* |
* |
32 |
* GT-64011 Used in Cobalt machines. |
* GT-64011 Used in Cobalt machines. |
33 |
* GT-64120 Used in evbmips machines (Malta). |
* GT-64120 Used in evbmips machines (Malta). |
34 |
* |
* |
35 |
* TODO: This more or less just a dummy device, so far. |
* TODO: This more or less just a dummy device, so far. It happens to work |
36 |
|
* with NetBSD/cobalt and /evbmips, and in some cases it might happen |
37 |
|
* to work with Linux as well, but don't rely on it for anything else. |
38 |
*/ |
*/ |
39 |
|
|
40 |
#include <stdio.h> |
#include <stdio.h> |
49 |
#include "misc.h" |
#include "misc.h" |
50 |
|
|
51 |
|
|
52 |
#define TICK_STEPS_SHIFT 16 |
#define TICK_SHIFT 14 |
53 |
|
|
54 |
|
/* #define debug fatal */ |
55 |
|
|
56 |
#define PCI_VENDOR_GALILEO 0x11ab /* Galileo Technology */ |
#define PCI_VENDOR_GALILEO 0x11ab /* Galileo Technology */ |
57 |
#define PCI_PRODUCT_GALILEO_GT64011 0x4146 /* GT-64011 System Controller */ |
#define PCI_PRODUCT_GALILEO_GT64011 0x4146 /* GT-64011 System Controller */ |
58 |
#define PCI_PRODUCT_GALILEO_GT64120 0x4620 /* GT-64120 */ |
#define PCI_PRODUCT_GALILEO_GT64120 0x4620 /* GT-64120 */ |
59 |
|
|
60 |
struct gt_data { |
struct gt_data { |
|
int reg[8]; |
|
61 |
int irqnr; |
int irqnr; |
62 |
int pciirq; |
int pciirq; |
63 |
int type; |
int type; |
84 |
unsigned char *data, size_t len, int writeflag, void *extra) |
unsigned char *data, size_t len, int writeflag, void *extra) |
85 |
{ |
{ |
86 |
uint64_t idata = 0, odata = 0; |
uint64_t idata = 0, odata = 0; |
87 |
int i; |
int i, asserted; |
88 |
struct gt_data *d = extra; |
struct gt_data *d = extra; |
89 |
|
|
90 |
idata = memory_readmax64(cpu, data, len); |
if (writeflag == MEM_WRITE) |
91 |
|
idata = memory_readmax64(cpu, data, len); |
92 |
|
|
93 |
switch (relative_addr) { |
switch (relative_addr) { |
94 |
|
|
95 |
|
case 0x48: |
96 |
|
switch (d->type) { |
97 |
|
case PCI_PRODUCT_GALILEO_GT64120: |
98 |
|
/* |
99 |
|
* This is needed for Linux on Malta, according |
100 |
|
* to Alec Voropay. (TODO: Remove this hack when |
101 |
|
* things have stabilized.) |
102 |
|
*/ |
103 |
|
if (writeflag == MEM_READ) { |
104 |
|
odata = 0x18000000 >> 21; |
105 |
|
debug("[ gt: read from 0x48: 0x%08x ]\n", |
106 |
|
(int)odata); |
107 |
|
} |
108 |
|
break; |
109 |
|
default: |
110 |
|
fatal("[ gt: access to 0x48? (type %i) ]\n", d->type); |
111 |
|
} |
112 |
|
break; |
113 |
|
|
114 |
case 0xc18: |
case 0xc18: |
115 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
116 |
debug("[ gt write to 0xc18: data = 0x%08lx ]\n", |
debug("[ gt: write to 0xc18: 0x%08x ]\n", (int)idata); |
|
(long)idata); |
|
117 |
return 1; |
return 1; |
118 |
} else { |
} else { |
119 |
odata = 0xffffffffULL; |
odata = 0xffffffffULL; |
120 |
/* ??? interrupt something... */ |
/* ??? interrupt something... */ |
121 |
|
|
122 |
|
/* |
123 |
|
* TODO: Remove this hack when things have stabilized. |
124 |
|
*/ |
125 |
odata = 0x00000100; /* netbsd/cobalt cobalt/machdep.c:cpu_intr() */ |
odata = 0x00000100; /* netbsd/cobalt cobalt/machdep.c:cpu_intr() */ |
126 |
|
|
127 |
cpu_interrupt_ack(cpu, d->irqnr); |
cpu_interrupt_ack(cpu, d->irqnr); |
128 |
|
|
129 |
debug("[ gt read from 0xc18 (data = 0x%08lx) ]\n", |
debug("[ gt: read from 0xc18 (0x%08x) ]\n", (int)odata); |
|
(long)odata); |
|
130 |
} |
} |
131 |
break; |
break; |
132 |
|
|
133 |
|
case 0xc34: /* GT_PCI0_INTR_ACK */ |
134 |
|
/* |
135 |
|
* Ugly hack, which works for at least evbmips/Malta: |
136 |
|
*/ |
137 |
|
asserted = |
138 |
|
(cpu->machine->isa_pic_data.pic1->irr & |
139 |
|
~cpu->machine->isa_pic_data.pic1->ier) | |
140 |
|
((cpu->machine->isa_pic_data.pic2->irr & |
141 |
|
~cpu->machine->isa_pic_data.pic2->ier) << 8); |
142 |
|
odata = 7; /* "Spurious interrupt" defaults to 7. */ |
143 |
|
for (i=0; i<16; i++) |
144 |
|
if ((asserted >> i) & 1) { |
145 |
|
odata = i; |
146 |
|
break; |
147 |
|
} |
148 |
|
break; |
149 |
|
|
150 |
case 0xcf8: /* PCI ADDR */ |
case 0xcf8: /* PCI ADDR */ |
151 |
case 0xcfc: /* PCI DATA */ |
case 0xcfc: /* PCI DATA */ |
152 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
159 |
break; |
break; |
160 |
default: |
default: |
161 |
if (writeflag==MEM_READ) { |
if (writeflag==MEM_READ) { |
162 |
debug("[ gt read from addr 0x%x ]\n", |
debug("[ gt: read from addr 0x%x ]\n", |
163 |
(int)relative_addr); |
(int)relative_addr); |
|
odata = d->reg[relative_addr]; |
|
164 |
} else { |
} else { |
165 |
debug("[ gt write to addr 0x%x:", (int)relative_addr); |
debug("[ gt: write to addr 0x%x:", (int)relative_addr); |
166 |
for (i=0; i<len; i++) |
for (i=0; i<len; i++) |
167 |
debug(" %02x", data[i]); |
debug(" %02x", data[i]); |
168 |
debug(" ]\n"); |
debug(" ]\n"); |
|
d->reg[relative_addr] = idata; |
|
169 |
} |
} |
170 |
} |
} |
171 |
|
|
260 |
|
|
261 |
memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH, |
memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH, |
262 |
dev_gt_access, d, MEM_DEFAULT, NULL); |
dev_gt_access, d, MEM_DEFAULT, NULL); |
263 |
machine_add_tickfunction(machine, dev_gt_tick, d, TICK_STEPS_SHIFT); |
machine_add_tickfunction(machine, dev_gt_tick, d, TICK_SHIFT); |
264 |
|
|
265 |
return d->pci_data; |
return d->pci_data; |
266 |
} |
} |