/[gxemul]/trunk/src/devices/dev_gt.c
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Annotation of /trunk/src/devices/dev_gt.c

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Revision 42 - (hide annotations)
Mon Oct 8 16:22:32 2007 UTC (16 years, 7 months ago) by dpavlin
File MIME type: text/plain
File size: 8261 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1613 2007/06/15 20:11:26 debug Exp $
20070501	Continuing a little on m88k disassembly (control registers,
		more instructions).
		Adding a dummy mvme88k machine mode.
20070502	Re-adding MIPS load/store alignment exceptions.
20070503	Implementing more of the M88K disassembly code.
20070504	Adding disassembly of some more M88K load/store instructions.
		Implementing some relatively simple M88K instructions (br.n,
		xor[.u] imm, and[.u] imm).
20070505	Implementing M88K three-register and, or, xor, and jmp[.n],
		bsr[.n] including function call trace stuff.
		Applying a patch from Bruce M. Simpson which implements the
		SYSCON_BOARD_CPU_CLOCK_FREQ_ID object of the syscon call in
		the yamon PROM emulation.
20070506	Implementing M88K bb0[.n] and bb1[.n], and skeletons for
		ldcr and stcr (although no control regs are implemented yet).
20070509	Found and fixed the bug which caused Linux for QEMU_MIPS to
		stop working in 0.4.5.1: It was a faulty change to the MIPS
		'sc' and 'scd' instructions I made while going through gcc -W
		warnings on 20070428.
20070510	Updating the Linux/QEMU_MIPS section in guestoses.html to
		use mips-test-0.2.tar.gz instead of 0.1.
		A big thank you to Miod Vallat for sending me M88K manuals.
		Implementing more M88K instructions (addu, subu, div[u], mulu,
		ext[u], clr, set, cmp).
20070511	Fixing bugs in the M88K "and" and "and.u" instructions (found
		by comparing against the manual).
		Implementing more M88K instructions (mask[.u], mak, bcnd (auto-
		generated)) and some more control register details.
		Cleanup: Removing the experimental AVR emulation mode and
		corresponding devices; AVR emulation wasn't really meaningful.
		Implementing autogeneration of most M88K loads/stores. The
		rectangle drawing demo (with -O0) for M88K runs :-)
		Beginning on M88K exception handling.
		More M88K instructions: tb0, tb1, rte, sub, jsr[.n].
		Adding some skeleton MVME PROM ("BUG") emulation.
20070512	Fixing a bug in the M88K cmp instruction.
		Adding the M88K lda (scaled register) instruction.
		Fixing bugs in 64-bit (32-bit pairs) M88K loads/stores.
		Removing the unused tick_hz stuff from the machine struct.
		Implementing the M88K xmem instruction. OpenBSD/mvme88k gets
		far enough to display the Copyright banner :-)
		Implementing subu.co (guess), addu.co, addu.ci, ff0, and ff1.
		Adding a dev_mvme187, for MVME187-specific devices/registers.
		OpenBSD/mvme88k prints more boot messages. :)
20070515	Continuing on MVME187 emulation (adding more devices, beginning
		on the CMMUs, etc).
		Adding the M88K and.c, xor.c, and or.c instructions, and making
		sure that mul, div, etc cause exceptions if executed when SFD1
		is disabled.
20070517	Continuing on M88K and MVME187 emulation in general; moving
		the CMMU registers to the CPU struct, separating dev_pcc2 from
		dev_mvme187, and beginning on memory_m88k.c (BATC and PATC).
		Fixing a bug in 64-bit (32-bit pairs) M88K fast stores.
		Implementing the clock part of dev_mk48txx.
		Implementing the M88K fstcr and xcr instructions.
		Implementing m88k_cpu_tlbdump().
		Beginning on the implementation of a separate address space
		for M88K .usr loads/stores.
20070520	Removing the non-working (skeleton) Sandpoint, SonyNEWS, SHARK
		Dnard, and Zaurus machine modes.
		Experimenting with dyntrans to_be_translated read-ahead. It
		seems to give a very small performance increase for MIPS
		emulation, but a large performance degradation for SuperH. Hm.
20070522	Disabling correct SuperH ITLB emulation; it does not seem to be
		necessary in order to let SH4 guest OSes run, and it slows down
		userspace code.
		Implementing "samepage" branches for SuperH emulation, and some
		other minor speed hacks.
20070525	Continuing on M88K memory-related stuff: exceptions, memory
		transaction register contents, etc.
		Implementing the M88K subu.ci instruction.
		Removing the non-working (skeleton) Iyonix machine mode.
		OpenBSD/mvme88k reaches userland :-), starts executing
		/sbin/init's instructions, and issues a few syscalls, before
		crashing.
20070526	Fixing bugs in dev_mk48txx, so that OpenBSD/mvme88k detects
		the correct time-of-day.
		Implementing a generic IRQ controller for the test machines
		(dev_irqc), similar to a proposed patch from Petr Stepan.
		Experimenting some more with translation read-ahead.
		Adding an "expect" script for automated OpenBSD/landisk
		install regression/performance tests.
20070527	Adding a dummy mmEye (SH3) machine mode skeleton.
		FINALLY found the strange M88K bug I have been hunting: I had
		not emulated the SNIP value for exceptions occurring in
		branch delay slots correctly.
		Implementing correct exceptions for 64-bit M88K loads/stores.
		Address to symbol lookups are now disabled when M88K is
		running in usermode (because usermode addresses don't have
		anything to do with supervisor addresses).
20070531	Removing the mmEye machine mode skeleton.
20070604	Some minor code cleanup.
20070605	Moving src/useremul.c into a subdir (src/useremul/), and
		cleaning up some more legacy constructs.
		Adding -Wstrict-aliasing and -fstrict-aliasing detection to
		the configure script.
20070606	Adding a check for broken GCC on Solaris to the configure
		script. (GCC 3.4.3 on Solaris cannot handle static variables
		which are initialized to 0 or NULL. :-/)
		Removing the old (non-working) ARC emulation modes: NEC RD94,
		R94, R96, and R98, and the last traces of Olivetti M700 and
		Deskstation Tyne.
		Removing the non-working skeleton WDSC device (dev_wdsc).
20070607	Thinking about how to use the host's cc + ld at runtime to
		generate native code. (See experiments/native_cc_ld_test.i
		for an example.)
20070608	Adding a program counter sampling timer, which could be useful
		for native code generation experiments.
		The KN02_CSR_NRMMOD bit in the DECstation 5000/200 (KN02) CSR
		should always be set, to allow a 5000/200 PROM to boot.
20070609	Moving out breakpoint details from the machine struct into
		a helper struct, and removing the limit on max nr of
		breakpoints.
20070610	Moving out tick functions into a helper struct as well (which
		also gets rid of the max limit).
20070612	FINALLY figured out why Debian/DECstation stopped working when
		translation read-ahead was enabled: in src/memory_rw.c, the
		call to invalidate_code_translation was made also if the
		memory access was an instruction load (if the page was mapped
		as writable); it shouldn't be called in that case.
20070613	Implementing some more MIPS32/64 revision 2 instructions: di,
		ei, ext, dext, dextm, dextu, and ins.
20070614	Implementing an instruction combination for the NetBSD/arm
		idle loop (making the host not use any cpu if NetBSD/arm
		inside the emulator is not using any cpu).
		Increasing the nr of ARM VPH entries from 128 to 384.
20070615	Removing the ENABLE_arch stuff from the configure script, so
		that all included architectures are included in both release
		and development builds.
		Moving memory related helper functions from misc.c to memory.c.
		Adding preliminary instructions for netbooting NetBSD/pmppc to
		guestoses.html; it doesn't work yet, there are weird timeouts.
		Beginning a total rewrite of the userland emulation modes
		(removing all emulation modes, beginning from scratch with
		NetBSD/MIPS and FreeBSD/Alpha only).
20070616	After fixing a bug in the DEC21143 NIC (the TDSTAT_OWN bit was
		only cleared for the last segment when transmitting, not all
		segments), NetBSD/pmppc boots with root-on-nfs without the
		timeouts. Updating guestoses.html.
		Removing the skeleton PSP (Playstation Portable) mode.
		Moving X11-related stuff in the machine struct into a helper
		struct.
		Cleanup of out-of-memory checks, to use a new CHECK_ALLOCATION
		macro (which prints a meaningful error message).
		Adding a COMMENT to each machine and device (for automagic
		.index comment generation).
		Doing regression testing for the next release.

==============  RELEASE 0.4.6  ==============
1 dpavlin 4 /*
2 dpavlin 34 * Copyright (C) 2003-2007 Anders Gavare. All rights reserved.
3 dpavlin 4 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 42 * $Id: dev_gt.c,v 1.52 2007/06/15 19:11:15 debug Exp $
29 dpavlin 4 *
30 dpavlin 42 * COMMENT: Galileo Technology GT-64xxx PCI controller
31 dpavlin 4 *
32 dpavlin 10 * GT-64011 Used in Cobalt machines.
33     * GT-64120 Used in evbmips machines (Malta).
34 dpavlin 22 * GT-64260 Used in mvmeppc machines.
35 dpavlin 4 */
36    
37     #include <stdio.h>
38     #include <stdlib.h>
39     #include <string.h>
40    
41     #include "bus_pci.h"
42     #include "cpu.h"
43     #include "devices.h"
44 dpavlin 34 #include "interrupt.h"
45 dpavlin 4 #include "machine.h"
46     #include "memory.h"
47     #include "misc.h"
48 dpavlin 32 #include "timer.h"
49 dpavlin 4
50 dpavlin 28 #include "gtreg.h"
51 dpavlin 4
52 dpavlin 28
53 dpavlin 12 #define TICK_SHIFT 14
54 dpavlin 4
55 dpavlin 12 /* #define debug fatal */
56    
57 dpavlin 20 #define PCI_PRODUCT_GALILEO_GT64011 0x4146 /* GT-64011 */
58     #define PCI_PRODUCT_GALILEO_GT64120 0x4620 /* GT-64120 */
59 dpavlin 22 #define PCI_PRODUCT_GALILEO_GT64260 0x6430 /* GT-64260 */
60 dpavlin 4
61 dpavlin 28
62 dpavlin 4 struct gt_data {
63 dpavlin 28 int type;
64 dpavlin 4
65 dpavlin 32 struct timer *timer;
66 dpavlin 34 struct interrupt timer0_irq;
67 dpavlin 32 int interrupt_hz;
68     int pending_timer0_interrupts;
69    
70 dpavlin 30 /* Address decode registers: */
71     uint32_t decode[GT_N_DECODE_REGS];
72 dpavlin 28
73     struct pci_data *pci_data;
74 dpavlin 4 };
75    
76    
77 dpavlin 32 /*
78     * timer_tick():
79     *
80     * Called d->interrupt_hz times per (real-world) second.
81     */
82     static void timer_tick(struct timer *timer, void *extra)
83     {
84 dpavlin 42 struct gt_data *d = extra;
85 dpavlin 32 d->pending_timer0_interrupts ++;
86     }
87    
88    
89 dpavlin 28 DEVICE_TICK(gt)
90 dpavlin 4 {
91 dpavlin 42 struct gt_data *d = extra;
92 dpavlin 32 if (d->pending_timer0_interrupts > 0)
93 dpavlin 34 INTERRUPT_ASSERT(d->timer0_irq);
94 dpavlin 4 }
95    
96    
97 dpavlin 22 DEVICE_ACCESS(gt)
98 dpavlin 4 {
99 dpavlin 42 struct gt_data *d = extra;
100 dpavlin 4 uint64_t idata = 0, odata = 0;
101 dpavlin 22 int bus, dev, func, reg;
102     size_t i;
103 dpavlin 4
104 dpavlin 18 if (writeflag == MEM_WRITE)
105     idata = memory_readmax64(cpu, data, len);
106 dpavlin 4
107     switch (relative_addr) {
108 dpavlin 12
109 dpavlin 28 case GT_PCI0IOLD_OFS:
110 dpavlin 30 case GT_PCI0IOHD_OFS:
111     case GT_PCI0M0LD_OFS:
112     case GT_PCI0M0HD_OFS:
113     case GT_PCI0M1LD_OFS:
114     case GT_PCI0M1HD_OFS:
115     case GT_PCI0IOREMAP_OFS:
116     case GT_PCI0M0REMAP_OFS:
117     case GT_PCI0M1REMAP_OFS:
118 dpavlin 28 if (writeflag == MEM_READ) {
119 dpavlin 30 odata = d->decode[relative_addr / 8];
120     debug("[ gt: read from offset 0x%x: 0x%x ]\n",
121     (int)relative_addr, (int)odata);
122 dpavlin 28 } else {
123 dpavlin 30 d->decode[relative_addr / 8] = idata;
124     fatal("[ gt: write to offset 0x%x: 0x%x (TODO) ]\n",
125     (int)relative_addr, (int)idata);
126 dpavlin 12 }
127     break;
128    
129 dpavlin 30 case GT_PCI0_CMD_OFS:
130     if (writeflag == MEM_WRITE) {
131     debug("[ gt: write to GT_PCI0_CMD: 0x%08x (TODO) ]\n",
132 dpavlin 28 (int)idata);
133     } else {
134 dpavlin 30 debug("[ gt: read from GT_PCI0_CMD (0x%08x) (TODO) ]\n",
135     (int)odata);
136 dpavlin 28 }
137     break;
138    
139     case GT_INTR_CAUSE:
140 dpavlin 4 if (writeflag == MEM_WRITE) {
141 dpavlin 28 debug("[ gt: write to GT_INTR_CAUSE: 0x%08x ]\n",
142     (int)idata);
143 dpavlin 4 return 1;
144     } else {
145 dpavlin 28 odata = GTIC_T0EXP;
146 dpavlin 34 INTERRUPT_DEASSERT(d->timer0_irq);
147 dpavlin 4
148 dpavlin 32 if (d->pending_timer0_interrupts > 0)
149     d->pending_timer0_interrupts --;
150    
151 dpavlin 28 debug("[ gt: read from GT_INTR_CAUSE (0x%08x) ]\n",
152     (int)odata);
153 dpavlin 4 }
154     break;
155 dpavlin 12
156 dpavlin 28 case GT_PCI0_INTR_ACK:
157 dpavlin 20 odata = cpu->machine->isa_pic_data.last_int;
158 dpavlin 34
159     fatal("TODO: GT_PCI0_INTR_ACK\n");
160    
161     // cpu_interrupt_ack(cpu, d->pci_irqbase + odata);
162 dpavlin 12 break;
163    
164 dpavlin 32 case GT_TIMER_CTRL:
165     if (writeflag == MEM_WRITE) {
166     if (idata & ENTC0) {
167     /* TODO: Don't hardcode this. */
168     d->interrupt_hz = 100;
169     if (d->timer == NULL)
170     d->timer = timer_add(d->interrupt_hz,
171     timer_tick, d);
172     else
173     timer_update_frequency(d->timer,
174     d->interrupt_hz);
175     }
176     }
177     break;
178    
179 dpavlin 28 case GT_PCI0_CFG_ADDR:
180 dpavlin 22 if (cpu->byte_order != EMUL_LITTLE_ENDIAN) {
181     fatal("[ gt: TODO: big endian PCI access ]\n");
182     exit(1);
183     }
184     bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
185     bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
186     break;
187    
188 dpavlin 28 case GT_PCI0_CFG_DATA:
189 dpavlin 22 if (cpu->byte_order != EMUL_LITTLE_ENDIAN) {
190     fatal("[ gt: TODO: big endian PCI access ]\n");
191     exit(1);
192 dpavlin 4 }
193 dpavlin 22 bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
194     &odata : &idata, len, writeflag);
195 dpavlin 4 break;
196 dpavlin 22
197 dpavlin 4 default:
198 dpavlin 20 if (writeflag == MEM_READ) {
199 dpavlin 12 debug("[ gt: read from addr 0x%x ]\n",
200 dpavlin 4 (int)relative_addr);
201     } else {
202 dpavlin 12 debug("[ gt: write to addr 0x%x:", (int)relative_addr);
203 dpavlin 4 for (i=0; i<len; i++)
204     debug(" %02x", data[i]);
205     debug(" ]\n");
206     }
207     }
208    
209     if (writeflag == MEM_READ)
210     memory_writemax64(cpu, data, len, odata);
211    
212     return 1;
213     }
214    
215    
216     /*
217     * dev_gt_init():
218     *
219 dpavlin 30 * Initialize a Gallileo PCI controller device. First, the controller itself
220     * is added to the bus, then a pointer to the bus is returned.
221 dpavlin 4 */
222     struct pci_data *dev_gt_init(struct machine *machine, struct memory *mem,
223 dpavlin 34 uint64_t baseaddr, char *timer_irq_path, char *isa_irq_path, int type)
224 dpavlin 4 {
225     struct gt_data *d;
226 dpavlin 20 uint64_t pci_portbase = 0, pci_membase = 0;
227     uint64_t isa_portbase = 0, isa_membase = 0;
228     uint64_t pci_io_offset = 0, pci_mem_offset = 0;
229 dpavlin 22 char *gt_name = "NO";
230 dpavlin 4
231 dpavlin 42 CHECK_ALLOCATION(d = malloc(sizeof(struct gt_data)));
232 dpavlin 4 memset(d, 0, sizeof(struct gt_data));
233    
234 dpavlin 34 INTERRUPT_CONNECT(timer_irq_path, d->timer0_irq);
235    
236 dpavlin 10 switch (type) {
237     case 11:
238 dpavlin 20 /* Cobalt: */
239 dpavlin 10 d->type = PCI_PRODUCT_GALILEO_GT64011;
240 dpavlin 22 gt_name = "gt64011";
241 dpavlin 20 pci_io_offset = 0;
242     pci_mem_offset = 0;
243     pci_portbase = 0x10000000ULL;
244     pci_membase = 0x10100000ULL;
245     isa_portbase = 0x10000000ULL;
246     isa_membase = 0x10100000ULL;
247 dpavlin 10 break;
248     case 120:
249 dpavlin 20 /* EVBMIPS (Malta): */
250 dpavlin 10 d->type = PCI_PRODUCT_GALILEO_GT64120;
251 dpavlin 22 gt_name = "gt64120";
252 dpavlin 20 pci_io_offset = 0;
253     pci_mem_offset = 0;
254     pci_portbase = 0x18000000ULL;
255     pci_membase = 0x10000000ULL;
256     isa_portbase = 0x18000000ULL;
257     isa_membase = 0x10000000ULL;
258 dpavlin 10 break;
259 dpavlin 22 case 260:
260     /* MVMEPPC (mvme5500): */
261     d->type = PCI_PRODUCT_GALILEO_GT64260;
262     gt_name = "gt64260";
263     pci_io_offset = 0;
264     pci_mem_offset = 0;
265     pci_portbase = 0x18000000ULL;
266     pci_membase = 0x10000000ULL;
267     isa_portbase = 0x18000000ULL;
268     isa_membase = 0x10000000ULL;
269     break;
270     default:fatal("dev_gt_init(): unimplemented GT type (%i).\n", type);
271 dpavlin 10 exit(1);
272     }
273    
274 dpavlin 30
275     /*
276     * TODO: FIX THESE! Hardcoded numbers = bad.
277     */
278     d->decode[GT_PCI0IOLD_OFS / 8] = pci_portbase >> 21;
279     d->decode[GT_PCI0IOHD_OFS / 8] = 0x40;
280     d->decode[GT_PCI0M0LD_OFS / 8] = 0x80;
281     d->decode[GT_PCI0M0HD_OFS / 8] = 0x3f;
282     d->decode[GT_PCI0M1LD_OFS / 8] = 0xc1;
283     d->decode[GT_PCI0M1HD_OFS / 8] = 0x5e;
284     d->decode[GT_PCI0IOREMAP_OFS / 8] = d->decode[GT_PCI0IOLD_OFS / 8];
285     d->decode[GT_PCI0M0REMAP_OFS / 8] = d->decode[GT_PCI0M0LD_OFS / 8];
286     d->decode[GT_PCI0M1REMAP_OFS / 8] = d->decode[GT_PCI0M1LD_OFS / 8];
287    
288 dpavlin 22 d->pci_data = bus_pci_init(machine,
289 dpavlin 40 "TODO_gt_irq", pci_io_offset, pci_mem_offset,
290     pci_portbase, pci_membase, "TODO_pci_irqbase",
291 dpavlin 34 isa_portbase, isa_membase, isa_irq_path);
292 dpavlin 20
293 dpavlin 4 /*
294     * According to NetBSD/cobalt:
295     * pchb0 at pci0 dev 0 function 0: Galileo GT-64011
296     * System Controller, rev 1
297     */
298 dpavlin 22 bus_pci_add(machine, d->pci_data, mem, 0, 0, 0, gt_name);
299 dpavlin 4
300     memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH,
301 dpavlin 20 dev_gt_access, d, DM_DEFAULT, NULL);
302 dpavlin 42 machine_add_tickfunction(machine, dev_gt_tick, d, TICK_SHIFT);
303 dpavlin 4
304     return d->pci_data;
305     }
306    
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