src/devices/dev_gt.c

/*
 *  Copyright (C) 2003-2007  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *   
 *
 *  $Id: dev_gt.c,v 1.50 2007/04/29 13:44:14 debug Exp $
 *  
 *  Galileo Technology GT-64xxx PCI controller.
 *
 *      GT-64011        Used in Cobalt machines.
 *      GT-64120        Used in evbmips machines (Malta).
 *      GT-64260        Used in mvmeppc machines.
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "bus_pci.h"
#include "cpu.h"
#include "devices.h"
#include "interrupt.h"
#include "machine.h"
#include "memory.h"
#include "misc.h"
#include "timer.h"

#include "gtreg.h"


#define TICK_SHIFT              14

/*  #define debug fatal  */

#define PCI_PRODUCT_GALILEO_GT64011  0x4146    /*  GT-64011  */
#define PCI_PRODUCT_GALILEO_GT64120  0x4620    /*  GT-64120  */
#define PCI_PRODUCT_GALILEO_GT64260  0x6430    /*  GT-64260  */


struct gt_data {
        int             type;

        struct timer    *timer;
        struct interrupt timer0_irq;
        int             interrupt_hz;
        int             pending_timer0_interrupts;

        /*  Address decode registers:  */
        uint32_t        decode[GT_N_DECODE_REGS];

        struct pci_data *pci_data;
};


/*
 *  timer_tick():
 *
 *  Called d->interrupt_hz times per (real-world) second.
 */
static void timer_tick(struct timer *timer, void *extra)
{
        struct gt_data *d = (struct gt_data *) extra;
        d->pending_timer0_interrupts ++;
}


DEVICE_TICK(gt)
{
        struct gt_data *d = (struct gt_data *) extra;

        if (d->pending_timer0_interrupts > 0)
                INTERRUPT_ASSERT(d->timer0_irq);
}


DEVICE_ACCESS(gt)
{
        uint64_t idata = 0, odata = 0;
        int bus, dev, func, reg;
        size_t i;
        struct gt_data *d = extra;

        if (writeflag == MEM_WRITE)
                idata = memory_readmax64(cpu, data, len);

        switch (relative_addr) {

        case GT_PCI0IOLD_OFS:
        case GT_PCI0IOHD_OFS:
        case GT_PCI0M0LD_OFS:
        case GT_PCI0M0HD_OFS:
        case GT_PCI0M1LD_OFS:
        case GT_PCI0M1HD_OFS:
        case GT_PCI0IOREMAP_OFS:
        case GT_PCI0M0REMAP_OFS:
        case GT_PCI0M1REMAP_OFS:
                if (writeflag == MEM_READ) {
                        odata = d->decode[relative_addr / 8];
                        debug("[ gt: read from offset 0x%x: 0x%x ]\n",
                            (int)relative_addr, (int)odata);
                } else {
                        d->decode[relative_addr / 8] = idata;
                        fatal("[ gt: write to offset 0x%x: 0x%x (TODO) ]\n",
                            (int)relative_addr, (int)idata);
                }
                break;

        case GT_PCI0_CMD_OFS:
                if (writeflag == MEM_WRITE) {
                        debug("[ gt: write to GT_PCI0_CMD: 0x%08x (TODO) ]\n",
                            (int)idata);
                } else {
                        debug("[ gt: read from GT_PCI0_CMD (0x%08x) (TODO) ]\n",
                            (int)odata);
                }
                break;

        case GT_INTR_CAUSE:
                if (writeflag == MEM_WRITE) {
                        debug("[ gt: write to GT_INTR_CAUSE: 0x%08x ]\n",
                            (int)idata);
                        return 1;
                } else {
                        odata = GTIC_T0EXP;
                        INTERRUPT_DEASSERT(d->timer0_irq);

                        if (d->pending_timer0_interrupts > 0)
                                d->pending_timer0_interrupts --;

                        debug("[ gt: read from GT_INTR_CAUSE (0x%08x) ]\n",
                            (int)odata);
                }
                break;

        case GT_PCI0_INTR_ACK:
                odata = cpu->machine->isa_pic_data.last_int;

fatal("TODO: GT_PCI0_INTR_ACK\n");

//              cpu_interrupt_ack(cpu, d->pci_irqbase + odata);
                break;

        case GT_TIMER_CTRL:
                if (writeflag == MEM_WRITE) {
                        if (idata & ENTC0) {
                                /*  TODO: Don't hardcode this.  */
                                d->interrupt_hz = 100;
                                if (d->timer == NULL)
                                        d->timer = timer_add(d->interrupt_hz,
                                            timer_tick, d);
                                else
                                        timer_update_frequency(d->timer,
                                            d->interrupt_hz);
                        }
                }
                break;

        case GT_PCI0_CFG_ADDR:
                if (cpu->byte_order != EMUL_LITTLE_ENDIAN) {
                        fatal("[ gt: TODO: big endian PCI access ]\n");
                        exit(1);
                }
                bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
                bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
                break;

        case GT_PCI0_CFG_DATA:
                if (cpu->byte_order != EMUL_LITTLE_ENDIAN) {
                        fatal("[ gt: TODO: big endian PCI access ]\n");
                        exit(1);
                }
                bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
                    &odata : &idata, len, writeflag);
                break;

        default:
                if (writeflag == MEM_READ) {
                        debug("[ gt: read from addr 0x%x ]\n",
                            (int)relative_addr);
                } else {
                        debug("[ gt: write to addr 0x%x:", (int)relative_addr);
                        for (i=0; i<len; i++)
                                debug(" %02x", data[i]);
                        debug(" ]\n");
                }
        }

        if (writeflag == MEM_READ)
                memory_writemax64(cpu, data, len, odata);

        return 1;
}


/*
 *  dev_gt_init():
 *
 *  Initialize a Gallileo PCI controller device. First, the controller itself
 *  is added to the bus, then a pointer to the bus is returned.
 */
struct pci_data *dev_gt_init(struct machine *machine, struct memory *mem,
        uint64_t baseaddr, char *timer_irq_path, char *isa_irq_path, int type)
{
        struct gt_data *d;
        uint64_t pci_portbase = 0, pci_membase = 0;
        uint64_t isa_portbase = 0, isa_membase = 0;
        uint64_t pci_io_offset = 0, pci_mem_offset = 0;
        char *gt_name = "NO";

        d = malloc(sizeof(struct gt_data));
        if (d == NULL) {
                fprintf(stderr, "out of memory\n");
                exit(1);
        }
        memset(d, 0, sizeof(struct gt_data));

        INTERRUPT_CONNECT(timer_irq_path, d->timer0_irq);

        switch (type) {
        case 11:
                /*  Cobalt:  */
                d->type = PCI_PRODUCT_GALILEO_GT64011;
                gt_name = "gt64011";
                pci_io_offset = 0;
                pci_mem_offset = 0;
                pci_portbase = 0x10000000ULL;
                pci_membase = 0x10100000ULL;
                isa_portbase = 0x10000000ULL;
                isa_membase = 0x10100000ULL;
                break;
        case 120:
                /*  EVBMIPS (Malta):  */
                d->type = PCI_PRODUCT_GALILEO_GT64120;
                gt_name = "gt64120";
                pci_io_offset = 0;
                pci_mem_offset = 0;
                pci_portbase = 0x18000000ULL;
                pci_membase = 0x10000000ULL;
                isa_portbase = 0x18000000ULL;
                isa_membase = 0x10000000ULL;
                break;
        case 260:
                /*  MVMEPPC (mvme5500):  */
                d->type = PCI_PRODUCT_GALILEO_GT64260;
                gt_name = "gt64260";
                pci_io_offset = 0;
                pci_mem_offset = 0;
                pci_portbase = 0x18000000ULL;
                pci_membase = 0x10000000ULL;
                isa_portbase = 0x18000000ULL;
                isa_membase = 0x10000000ULL;
                break;
        default:fatal("dev_gt_init(): unimplemented GT type (%i).\n", type);
                exit(1);
        }


        /*
         *  TODO: FIX THESE! Hardcoded numbers = bad.
         */
        d->decode[GT_PCI0IOLD_OFS / 8] = pci_portbase >> 21;
        d->decode[GT_PCI0IOHD_OFS / 8] = 0x40;
        d->decode[GT_PCI0M0LD_OFS / 8] = 0x80;
        d->decode[GT_PCI0M0HD_OFS / 8] = 0x3f;
        d->decode[GT_PCI0M1LD_OFS / 8] = 0xc1;
        d->decode[GT_PCI0M1HD_OFS / 8] = 0x5e;
        d->decode[GT_PCI0IOREMAP_OFS / 8] = d->decode[GT_PCI0IOLD_OFS / 8];
        d->decode[GT_PCI0M0REMAP_OFS / 8] = d->decode[GT_PCI0M0LD_OFS / 8];
        d->decode[GT_PCI0M1REMAP_OFS / 8] = d->decode[GT_PCI0M1LD_OFS / 8];

        d->pci_data = bus_pci_init(machine,
            "TODO_gt_irq", pci_io_offset, pci_mem_offset,
            pci_portbase, pci_membase, "TODO_pci_irqbase",
            isa_portbase, isa_membase, isa_irq_path);

        /*
         *  According to NetBSD/cobalt:
         *  pchb0 at pci0 dev 0 function 0: Galileo GT-64011
         *  System Controller, rev 1
         */
        bus_pci_add(machine, d->pci_data, mem, 0, 0, 0, gt_name);

        memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH,
            dev_gt_access, d, DM_DEFAULT, NULL);
        machine_add_tickfunction(machine, dev_gt_tick, d, TICK_SHIFT, 0.0);

        return d->pci_data;
}

1	dpavlin	4	/*
2	dpavlin	34	* Copyright (C) 2003-2007 Anders Gavare. All rights reserved.
3	dpavlin	4	*
4			* Redistribution and use in source and binary forms, with or without
5			* modification, are permitted provided that the following conditions are met:
6			*
7			* 1. Redistributions of source code must retain the above copyright
8			* notice, this list of conditions and the following disclaimer.
9			* 2. Redistributions in binary form must reproduce the above copyright
10			* notice, this list of conditions and the following disclaimer in the
11			* documentation and/or other materials provided with the distribution.
12			* 3. The name of the author may not be used to endorse or promote products
13			* derived from this software without specific prior written permission.
14			*
15			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25			* SUCH DAMAGE.
26			*
27			*
28	dpavlin	40	* $Id: dev_gt.c,v 1.50 2007/04/29 13:44:14 debug Exp $
29	dpavlin	4	*
30	dpavlin	10	* Galileo Technology GT-64xxx PCI controller.
31	dpavlin	4	*
32	dpavlin	10	* GT-64011 Used in Cobalt machines.
33			* GT-64120 Used in evbmips machines (Malta).
34	dpavlin	22	* GT-64260 Used in mvmeppc machines.
35	dpavlin	4	*/
36
37			#include <stdio.h>
38			#include <stdlib.h>
39			#include <string.h>
40
41			#include "bus_pci.h"
42			#include "cpu.h"
43			#include "devices.h"
44	dpavlin	34	#include "interrupt.h"
45	dpavlin	4	#include "machine.h"
46			#include "memory.h"
47			#include "misc.h"
48	dpavlin	32	#include "timer.h"
49	dpavlin	4
50	dpavlin	28	#include "gtreg.h"
51	dpavlin	4
52	dpavlin	28
53	dpavlin	12	#define TICK_SHIFT 14
54	dpavlin	4
55	dpavlin	12	/* #define debug fatal */
56
57	dpavlin	20	#define PCI_PRODUCT_GALILEO_GT64011 0x4146 /* GT-64011 */
58			#define PCI_PRODUCT_GALILEO_GT64120 0x4620 /* GT-64120 */
59	dpavlin	22	#define PCI_PRODUCT_GALILEO_GT64260 0x6430 /* GT-64260 */
60	dpavlin	4
61	dpavlin	28
62	dpavlin	4	struct gt_data {
63	dpavlin	28	int type;
64	dpavlin	4
65	dpavlin	32	struct timer *timer;
66	dpavlin	34	struct interrupt timer0_irq;
67	dpavlin	32	int interrupt_hz;
68			int pending_timer0_interrupts;
69
70	dpavlin	30	/* Address decode registers: */
71			uint32_t decode[GT_N_DECODE_REGS];
72	dpavlin	28
73			struct pci_data *pci_data;
74	dpavlin	4	};
75
76
77	dpavlin	32	/*
78			* timer_tick():
79			*
80			* Called d->interrupt_hz times per (real-world) second.
81			*/
82			static void timer_tick(struct timer timer, void extra)
83			{
84			struct gt_data d = (struct gt_data ) extra;
85			d->pending_timer0_interrupts ++;
86			}
87
88
89	dpavlin	28	DEVICE_TICK(gt)
90	dpavlin	4	{
91	dpavlin	32	struct gt_data d = (struct gt_data ) extra;
92	dpavlin	4
93	dpavlin	32	if (d->pending_timer0_interrupts > 0)
94	dpavlin	34	INTERRUPT_ASSERT(d->timer0_irq);
95	dpavlin	4	}
96
97
98	dpavlin	22	DEVICE_ACCESS(gt)
99	dpavlin	4	{
100			uint64_t idata = 0, odata = 0;
101	dpavlin	22	int bus, dev, func, reg;
102			size_t i;
103	dpavlin	4	struct gt_data *d = extra;
104
105	dpavlin	18	if (writeflag == MEM_WRITE)
106			idata = memory_readmax64(cpu, data, len);
107	dpavlin	4
108			switch (relative_addr) {
109	dpavlin	12
110	dpavlin	28	case GT_PCI0IOLD_OFS:
111	dpavlin	30	case GT_PCI0IOHD_OFS:
112			case GT_PCI0M0LD_OFS:
113			case GT_PCI0M0HD_OFS:
114			case GT_PCI0M1LD_OFS:
115			case GT_PCI0M1HD_OFS:
116			case GT_PCI0IOREMAP_OFS:
117			case GT_PCI0M0REMAP_OFS:
118			case GT_PCI0M1REMAP_OFS:
119	dpavlin	28	if (writeflag == MEM_READ) {
120	dpavlin	30	odata = d->decode[relative_addr / 8];
121			debug("[ gt: read from offset 0x%x: 0x%x ]\n",
122			(int)relative_addr, (int)odata);
123	dpavlin	28	} else {
124	dpavlin	30	d->decode[relative_addr / 8] = idata;
125			fatal("[ gt: write to offset 0x%x: 0x%x (TODO) ]\n",
126			(int)relative_addr, (int)idata);
127	dpavlin	12	}
128			break;
129
130	dpavlin	30	case GT_PCI0_CMD_OFS:
131			if (writeflag == MEM_WRITE) {
132			debug("[ gt: write to GT_PCI0_CMD: 0x%08x (TODO) ]\n",
133	dpavlin	28	(int)idata);
134			} else {
135	dpavlin	30	debug("[ gt: read from GT_PCI0_CMD (0x%08x) (TODO) ]\n",
136			(int)odata);
137	dpavlin	28	}
138			break;
139
140			case GT_INTR_CAUSE:
141	dpavlin	4	if (writeflag == MEM_WRITE) {
142	dpavlin	28	debug("[ gt: write to GT_INTR_CAUSE: 0x%08x ]\n",
143			(int)idata);
144	dpavlin	4	return 1;
145			} else {
146	dpavlin	28	odata = GTIC_T0EXP;
147	dpavlin	34	INTERRUPT_DEASSERT(d->timer0_irq);
148	dpavlin	4
149	dpavlin	32	if (d->pending_timer0_interrupts > 0)
150			d->pending_timer0_interrupts --;
151
152	dpavlin	28	debug("[ gt: read from GT_INTR_CAUSE (0x%08x) ]\n",
153			(int)odata);
154	dpavlin	4	}
155			break;
156	dpavlin	12
157	dpavlin	28	case GT_PCI0_INTR_ACK:
158	dpavlin	20	odata = cpu->machine->isa_pic_data.last_int;
159	dpavlin	34
160			fatal("TODO: GT_PCI0_INTR_ACK\n");
161
162			// cpu_interrupt_ack(cpu, d->pci_irqbase + odata);
163	dpavlin	12	break;
164
165	dpavlin	32	case GT_TIMER_CTRL:
166			if (writeflag == MEM_WRITE) {
167			if (idata & ENTC0) {
168			/* TODO: Don't hardcode this. */
169			d->interrupt_hz = 100;
170			if (d->timer == NULL)
171			d->timer = timer_add(d->interrupt_hz,
172			timer_tick, d);
173			else
174			timer_update_frequency(d->timer,
175			d->interrupt_hz);
176			}
177			}
178			break;
179
180	dpavlin	28	case GT_PCI0_CFG_ADDR:
181	dpavlin	22	if (cpu->byte_order != EMUL_LITTLE_ENDIAN) {
182			fatal("[ gt: TODO: big endian PCI access ]\n");
183			exit(1);
184			}
185			bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
186			bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
187			break;
188
189	dpavlin	28	case GT_PCI0_CFG_DATA:
190	dpavlin	22	if (cpu->byte_order != EMUL_LITTLE_ENDIAN) {
191			fatal("[ gt: TODO: big endian PCI access ]\n");
192			exit(1);
193	dpavlin	4	}
194	dpavlin	22	bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
195			&odata : &idata, len, writeflag);
196	dpavlin	4	break;
197	dpavlin	22
198	dpavlin	4	default:
199	dpavlin	20	if (writeflag == MEM_READ) {
200	dpavlin	12	debug("[ gt: read from addr 0x%x ]\n",
201	dpavlin	4	(int)relative_addr);
202			} else {
203	dpavlin	12	debug("[ gt: write to addr 0x%x:", (int)relative_addr);
204	dpavlin	4	for (i=0; i<len; i++)
205			debug(" %02x", data[i]);
206			debug(" ]\n");
207			}
208			}
209
210			if (writeflag == MEM_READ)
211			memory_writemax64(cpu, data, len, odata);
212
213			return 1;
214			}
215
216
217			/*
218			* dev_gt_init():
219			*
220	dpavlin	30	* Initialize a Gallileo PCI controller device. First, the controller itself
221			* is added to the bus, then a pointer to the bus is returned.
222	dpavlin	4	*/
223			struct pci_data dev_gt_init(struct machine machine, struct memory *mem,
224	dpavlin	34	uint64_t baseaddr, char timer_irq_path, char isa_irq_path, int type)
225	dpavlin	4	{
226			struct gt_data *d;
227	dpavlin	20	uint64_t pci_portbase = 0, pci_membase = 0;
228			uint64_t isa_portbase = 0, isa_membase = 0;
229			uint64_t pci_io_offset = 0, pci_mem_offset = 0;
230	dpavlin	22	char *gt_name = "NO";
231	dpavlin	4
232			d = malloc(sizeof(struct gt_data));
233			if (d == NULL) {
234			fprintf(stderr, "out of memory\n");
235			exit(1);
236			}
237			memset(d, 0, sizeof(struct gt_data));
238
239	dpavlin	34	INTERRUPT_CONNECT(timer_irq_path, d->timer0_irq);
240
241	dpavlin	10	switch (type) {
242			case 11:
243	dpavlin	20	/* Cobalt: */
244	dpavlin	10	d->type = PCI_PRODUCT_GALILEO_GT64011;
245	dpavlin	22	gt_name = "gt64011";
246	dpavlin	20	pci_io_offset = 0;
247			pci_mem_offset = 0;
248			pci_portbase = 0x10000000ULL;
249			pci_membase = 0x10100000ULL;
250			isa_portbase = 0x10000000ULL;
251			isa_membase = 0x10100000ULL;
252	dpavlin	10	break;
253			case 120:
254	dpavlin	20	/* EVBMIPS (Malta): */
255	dpavlin	10	d->type = PCI_PRODUCT_GALILEO_GT64120;
256	dpavlin	22	gt_name = "gt64120";
257	dpavlin	20	pci_io_offset = 0;
258			pci_mem_offset = 0;
259			pci_portbase = 0x18000000ULL;
260			pci_membase = 0x10000000ULL;
261			isa_portbase = 0x18000000ULL;
262			isa_membase = 0x10000000ULL;
263	dpavlin	10	break;
264	dpavlin	22	case 260:
265			/* MVMEPPC (mvme5500): */
266			d->type = PCI_PRODUCT_GALILEO_GT64260;
267			gt_name = "gt64260";
268			pci_io_offset = 0;
269			pci_mem_offset = 0;
270			pci_portbase = 0x18000000ULL;
271			pci_membase = 0x10000000ULL;
272			isa_portbase = 0x18000000ULL;
273			isa_membase = 0x10000000ULL;
274			break;
275			default:fatal("dev_gt_init(): unimplemented GT type (%i).\n", type);
276	dpavlin	10	exit(1);
277			}
278
279	dpavlin	30
280			/*
281			* TODO: FIX THESE! Hardcoded numbers = bad.
282			*/
283			d->decode[GT_PCI0IOLD_OFS / 8] = pci_portbase >> 21;
284			d->decode[GT_PCI0IOHD_OFS / 8] = 0x40;
285			d->decode[GT_PCI0M0LD_OFS / 8] = 0x80;
286			d->decode[GT_PCI0M0HD_OFS / 8] = 0x3f;
287			d->decode[GT_PCI0M1LD_OFS / 8] = 0xc1;
288			d->decode[GT_PCI0M1HD_OFS / 8] = 0x5e;
289			d->decode[GT_PCI0IOREMAP_OFS / 8] = d->decode[GT_PCI0IOLD_OFS / 8];
290			d->decode[GT_PCI0M0REMAP_OFS / 8] = d->decode[GT_PCI0M0LD_OFS / 8];
291			d->decode[GT_PCI0M1REMAP_OFS / 8] = d->decode[GT_PCI0M1LD_OFS / 8];
292
293	dpavlin	22	d->pci_data = bus_pci_init(machine,
294	dpavlin	40	"TODO_gt_irq", pci_io_offset, pci_mem_offset,
295			pci_portbase, pci_membase, "TODO_pci_irqbase",
296	dpavlin	34	isa_portbase, isa_membase, isa_irq_path);
297	dpavlin	20
298	dpavlin	4	/*
299			* According to NetBSD/cobalt:
300			* pchb0 at pci0 dev 0 function 0: Galileo GT-64011
301			* System Controller, rev 1
302			*/
303	dpavlin	22	bus_pci_add(machine, d->pci_data, mem, 0, 0, 0, gt_name);
304	dpavlin	4
305			memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH,
306	dpavlin	20	dev_gt_access, d, DM_DEFAULT, NULL);
307	dpavlin	24	machine_add_tickfunction(machine, dev_gt_tick, d, TICK_SHIFT, 0.0);
308	dpavlin	4
309			return d->pci_data;
310			}
311