/[gxemul]/trunk/src/devices/dev_gt.c
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Revision 34 - (hide annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 8354 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============
1 dpavlin 4 /*
2 dpavlin 34 * Copyright (C) 2003-2007 Anders Gavare. All rights reserved.
3 dpavlin 4 *
4     * Redistribution and use in source and binary forms, with or without
5     * modification, are permitted provided that the following conditions are met:
6     *
7     * 1. Redistributions of source code must retain the above copyright
8     * notice, this list of conditions and the following disclaimer.
9     * 2. Redistributions in binary form must reproduce the above copyright
10     * notice, this list of conditions and the following disclaimer in the
11     * documentation and/or other materials provided with the distribution.
12     * 3. The name of the author may not be used to endorse or promote products
13     * derived from this software without specific prior written permission.
14     *
15     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25     * SUCH DAMAGE.
26     *
27     *
28 dpavlin 34 * $Id: dev_gt.c,v 1.49 2007/01/05 16:50:08 debug Exp $
29 dpavlin 4 *
30 dpavlin 10 * Galileo Technology GT-64xxx PCI controller.
31 dpavlin 4 *
32 dpavlin 10 * GT-64011 Used in Cobalt machines.
33     * GT-64120 Used in evbmips machines (Malta).
34 dpavlin 22 * GT-64260 Used in mvmeppc machines.
35 dpavlin 4 */
36    
37     #include <stdio.h>
38     #include <stdlib.h>
39     #include <string.h>
40    
41     #include "bus_pci.h"
42     #include "cpu.h"
43     #include "devices.h"
44 dpavlin 34 #include "interrupt.h"
45 dpavlin 4 #include "machine.h"
46     #include "memory.h"
47     #include "misc.h"
48 dpavlin 32 #include "timer.h"
49 dpavlin 4
50 dpavlin 28 #include "gtreg.h"
51 dpavlin 4
52 dpavlin 28
53 dpavlin 12 #define TICK_SHIFT 14
54 dpavlin 4
55 dpavlin 12 /* #define debug fatal */
56    
57 dpavlin 20 #define PCI_PRODUCT_GALILEO_GT64011 0x4146 /* GT-64011 */
58     #define PCI_PRODUCT_GALILEO_GT64120 0x4620 /* GT-64120 */
59 dpavlin 22 #define PCI_PRODUCT_GALILEO_GT64260 0x6430 /* GT-64260 */
60 dpavlin 4
61 dpavlin 28
62 dpavlin 4 struct gt_data {
63 dpavlin 28 int type;
64 dpavlin 4
65 dpavlin 32 struct timer *timer;
66 dpavlin 34 struct interrupt timer0_irq;
67 dpavlin 32 int interrupt_hz;
68     int pending_timer0_interrupts;
69    
70 dpavlin 30 /* Address decode registers: */
71     uint32_t decode[GT_N_DECODE_REGS];
72 dpavlin 28
73     struct pci_data *pci_data;
74 dpavlin 4 };
75    
76    
77 dpavlin 32 /*
78     * timer_tick():
79     *
80     * Called d->interrupt_hz times per (real-world) second.
81     */
82     static void timer_tick(struct timer *timer, void *extra)
83     {
84     struct gt_data *d = (struct gt_data *) extra;
85     d->pending_timer0_interrupts ++;
86     }
87    
88    
89 dpavlin 28 DEVICE_TICK(gt)
90 dpavlin 4 {
91 dpavlin 32 struct gt_data *d = (struct gt_data *) extra;
92 dpavlin 4
93 dpavlin 32 if (d->pending_timer0_interrupts > 0)
94 dpavlin 34 INTERRUPT_ASSERT(d->timer0_irq);
95 dpavlin 4 }
96    
97    
98 dpavlin 22 DEVICE_ACCESS(gt)
99 dpavlin 4 {
100     uint64_t idata = 0, odata = 0;
101 dpavlin 22 int bus, dev, func, reg;
102     size_t i;
103 dpavlin 4 struct gt_data *d = extra;
104    
105 dpavlin 18 if (writeflag == MEM_WRITE)
106     idata = memory_readmax64(cpu, data, len);
107 dpavlin 4
108     switch (relative_addr) {
109 dpavlin 12
110 dpavlin 28 case GT_PCI0IOLD_OFS:
111 dpavlin 30 case GT_PCI0IOHD_OFS:
112     case GT_PCI0M0LD_OFS:
113     case GT_PCI0M0HD_OFS:
114     case GT_PCI0M1LD_OFS:
115     case GT_PCI0M1HD_OFS:
116     case GT_PCI0IOREMAP_OFS:
117     case GT_PCI0M0REMAP_OFS:
118     case GT_PCI0M1REMAP_OFS:
119 dpavlin 28 if (writeflag == MEM_READ) {
120 dpavlin 30 odata = d->decode[relative_addr / 8];
121     debug("[ gt: read from offset 0x%x: 0x%x ]\n",
122     (int)relative_addr, (int)odata);
123 dpavlin 28 } else {
124 dpavlin 30 d->decode[relative_addr / 8] = idata;
125     fatal("[ gt: write to offset 0x%x: 0x%x (TODO) ]\n",
126     (int)relative_addr, (int)idata);
127 dpavlin 12 }
128     break;
129    
130 dpavlin 30 case GT_PCI0_CMD_OFS:
131     if (writeflag == MEM_WRITE) {
132     debug("[ gt: write to GT_PCI0_CMD: 0x%08x (TODO) ]\n",
133 dpavlin 28 (int)idata);
134     } else {
135 dpavlin 30 debug("[ gt: read from GT_PCI0_CMD (0x%08x) (TODO) ]\n",
136     (int)odata);
137 dpavlin 28 }
138     break;
139    
140     case GT_INTR_CAUSE:
141 dpavlin 4 if (writeflag == MEM_WRITE) {
142 dpavlin 28 debug("[ gt: write to GT_INTR_CAUSE: 0x%08x ]\n",
143     (int)idata);
144 dpavlin 4 return 1;
145     } else {
146 dpavlin 28 odata = GTIC_T0EXP;
147 dpavlin 34 INTERRUPT_DEASSERT(d->timer0_irq);
148 dpavlin 4
149 dpavlin 32 if (d->pending_timer0_interrupts > 0)
150     d->pending_timer0_interrupts --;
151    
152 dpavlin 28 debug("[ gt: read from GT_INTR_CAUSE (0x%08x) ]\n",
153     (int)odata);
154 dpavlin 4 }
155     break;
156 dpavlin 12
157 dpavlin 28 case GT_PCI0_INTR_ACK:
158 dpavlin 20 odata = cpu->machine->isa_pic_data.last_int;
159 dpavlin 34
160     fatal("TODO: GT_PCI0_INTR_ACK\n");
161    
162     // cpu_interrupt_ack(cpu, d->pci_irqbase + odata);
163 dpavlin 12 break;
164    
165 dpavlin 32 case GT_TIMER_CTRL:
166     if (writeflag == MEM_WRITE) {
167     if (idata & ENTC0) {
168     /* TODO: Don't hardcode this. */
169     d->interrupt_hz = 100;
170     if (d->timer == NULL)
171     d->timer = timer_add(d->interrupt_hz,
172     timer_tick, d);
173     else
174     timer_update_frequency(d->timer,
175     d->interrupt_hz);
176     }
177     }
178     break;
179    
180 dpavlin 28 case GT_PCI0_CFG_ADDR:
181 dpavlin 22 if (cpu->byte_order != EMUL_LITTLE_ENDIAN) {
182     fatal("[ gt: TODO: big endian PCI access ]\n");
183     exit(1);
184     }
185     bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
186     bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
187     break;
188    
189 dpavlin 28 case GT_PCI0_CFG_DATA:
190 dpavlin 22 if (cpu->byte_order != EMUL_LITTLE_ENDIAN) {
191     fatal("[ gt: TODO: big endian PCI access ]\n");
192     exit(1);
193 dpavlin 4 }
194 dpavlin 22 bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
195     &odata : &idata, len, writeflag);
196 dpavlin 4 break;
197 dpavlin 22
198 dpavlin 4 default:
199 dpavlin 20 if (writeflag == MEM_READ) {
200 dpavlin 12 debug("[ gt: read from addr 0x%x ]\n",
201 dpavlin 4 (int)relative_addr);
202     } else {
203 dpavlin 12 debug("[ gt: write to addr 0x%x:", (int)relative_addr);
204 dpavlin 4 for (i=0; i<len; i++)
205     debug(" %02x", data[i]);
206     debug(" ]\n");
207     }
208     }
209    
210     if (writeflag == MEM_READ)
211     memory_writemax64(cpu, data, len, odata);
212    
213     return 1;
214     }
215    
216    
217     /*
218     * dev_gt_init():
219     *
220 dpavlin 30 * Initialize a Gallileo PCI controller device. First, the controller itself
221     * is added to the bus, then a pointer to the bus is returned.
222 dpavlin 4 */
223     struct pci_data *dev_gt_init(struct machine *machine, struct memory *mem,
224 dpavlin 34 uint64_t baseaddr, char *timer_irq_path, char *isa_irq_path, int type)
225 dpavlin 4 {
226     struct gt_data *d;
227 dpavlin 20 uint64_t pci_portbase = 0, pci_membase = 0;
228     uint64_t isa_portbase = 0, isa_membase = 0;
229     uint64_t pci_io_offset = 0, pci_mem_offset = 0;
230 dpavlin 22 char *gt_name = "NO";
231 dpavlin 4
232     d = malloc(sizeof(struct gt_data));
233     if (d == NULL) {
234     fprintf(stderr, "out of memory\n");
235     exit(1);
236     }
237     memset(d, 0, sizeof(struct gt_data));
238    
239 dpavlin 34 INTERRUPT_CONNECT(timer_irq_path, d->timer0_irq);
240    
241 dpavlin 10 switch (type) {
242     case 11:
243 dpavlin 20 /* Cobalt: */
244 dpavlin 10 d->type = PCI_PRODUCT_GALILEO_GT64011;
245 dpavlin 22 gt_name = "gt64011";
246 dpavlin 20 pci_io_offset = 0;
247     pci_mem_offset = 0;
248     pci_portbase = 0x10000000ULL;
249     pci_membase = 0x10100000ULL;
250     isa_portbase = 0x10000000ULL;
251     isa_membase = 0x10100000ULL;
252 dpavlin 10 break;
253     case 120:
254 dpavlin 20 /* EVBMIPS (Malta): */
255 dpavlin 10 d->type = PCI_PRODUCT_GALILEO_GT64120;
256 dpavlin 22 gt_name = "gt64120";
257 dpavlin 20 pci_io_offset = 0;
258     pci_mem_offset = 0;
259     pci_portbase = 0x18000000ULL;
260     pci_membase = 0x10000000ULL;
261     isa_portbase = 0x18000000ULL;
262     isa_membase = 0x10000000ULL;
263 dpavlin 10 break;
264 dpavlin 22 case 260:
265     /* MVMEPPC (mvme5500): */
266     d->type = PCI_PRODUCT_GALILEO_GT64260;
267     gt_name = "gt64260";
268     pci_io_offset = 0;
269     pci_mem_offset = 0;
270     pci_portbase = 0x18000000ULL;
271     pci_membase = 0x10000000ULL;
272     isa_portbase = 0x18000000ULL;
273     isa_membase = 0x10000000ULL;
274     break;
275     default:fatal("dev_gt_init(): unimplemented GT type (%i).\n", type);
276 dpavlin 10 exit(1);
277     }
278    
279 dpavlin 30
280     /*
281     * TODO: FIX THESE! Hardcoded numbers = bad.
282     */
283     d->decode[GT_PCI0IOLD_OFS / 8] = pci_portbase >> 21;
284     d->decode[GT_PCI0IOHD_OFS / 8] = 0x40;
285     d->decode[GT_PCI0M0LD_OFS / 8] = 0x80;
286     d->decode[GT_PCI0M0HD_OFS / 8] = 0x3f;
287     d->decode[GT_PCI0M1LD_OFS / 8] = 0xc1;
288     d->decode[GT_PCI0M1HD_OFS / 8] = 0x5e;
289     d->decode[GT_PCI0IOREMAP_OFS / 8] = d->decode[GT_PCI0IOLD_OFS / 8];
290     d->decode[GT_PCI0M0REMAP_OFS / 8] = d->decode[GT_PCI0M0LD_OFS / 8];
291     d->decode[GT_PCI0M1REMAP_OFS / 8] = d->decode[GT_PCI0M1LD_OFS / 8];
292    
293 dpavlin 22 d->pci_data = bus_pci_init(machine,
294 dpavlin 34 "TODO irq stuff!", pci_io_offset, pci_mem_offset,
295     pci_portbase, pci_membase, "TODO: pci_irqbase",
296     isa_portbase, isa_membase, isa_irq_path);
297 dpavlin 20
298 dpavlin 4 /*
299     * According to NetBSD/cobalt:
300     * pchb0 at pci0 dev 0 function 0: Galileo GT-64011
301     * System Controller, rev 1
302     */
303 dpavlin 22 bus_pci_add(machine, d->pci_data, mem, 0, 0, 0, gt_name);
304 dpavlin 4
305     memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH,
306 dpavlin 20 dev_gt_access, d, DM_DEFAULT, NULL);
307 dpavlin 24 machine_add_tickfunction(machine, dev_gt_tick, d, TICK_SHIFT, 0.0);
308 dpavlin 4
309     return d->pci_data;
310     }
311    
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