src/devices/dev_gt.c

/*
 *  Copyright (C) 2003-2005  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *   
 *
 *  $Id: dev_gt.c,v 1.22 2005/06/20 08:19:58 debug Exp $
 *  
 *  Galileo Technology GT-64xxx PCI controller.
 *
 *      GT-64011        Used in Cobalt machines.
 *      GT-64120        Used in evbmips machines (Malta).
 *
 *  TODO:  This more or less just a dummy device, so far.
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "bus_pci.h"
#include "cpu.h"
#include "devices.h"
#include "machine.h"
#include "memory.h"
#include "misc.h"


#define TICK_STEPS_SHIFT        16

#define PCI_VENDOR_GALILEO           0x11ab    /* Galileo Technology */
#define PCI_PRODUCT_GALILEO_GT64011  0x4146    /* GT-64011 System Controller */
#define PCI_PRODUCT_GALILEO_GT64120  0x4620    /* GT-64120 */

struct gt_data {
        int     reg[8];
        int     irqnr;
        int     pciirq;
        int     type;

        struct pci_data *pci_data;
};


/*
 *  dev_gt_tick():
 */
void dev_gt_tick(struct cpu *cpu, void *extra)
{
        struct gt_data *gt_data = extra;

        cpu_interrupt(cpu, gt_data->irqnr);
}


/*
 *  dev_gt_access():
 */
int dev_gt_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr,
        unsigned char *data, size_t len, int writeflag, void *extra)
{
        uint64_t idata = 0, odata = 0;
        int i;
        struct gt_data *d = extra;

        idata = memory_readmax64(cpu, data, len);

        switch (relative_addr) {
        case 0xc18:
                if (writeflag == MEM_WRITE) {
                        debug("[ gt write to  0xc18: data = 0x%08lx ]\n",
                            (long)idata);
                        return 1;
                } else {
                        odata = 0xffffffffULL;
                        /*  ???  interrupt something...  */

odata = 0x00000100;     /*  netbsd/cobalt cobalt/machdep.c:cpu_intr()  */

cpu_interrupt_ack(cpu, d->irqnr);

                        debug("[ gt read from 0xc18 (data = 0x%08lx) ]\n",
                            (long)odata);
                }
                break;
        case 0xcf8:     /*  PCI ADDR  */
        case 0xcfc:     /*  PCI DATA  */
                if (writeflag == MEM_WRITE) {
                        bus_pci_access(cpu, mem, relative_addr, &idata,
                            writeflag, d->pci_data);
                } else {
                        bus_pci_access(cpu, mem, relative_addr, &odata,
                            writeflag, d->pci_data);
                }
                break;
        default:
                if (writeflag==MEM_READ) {
                        debug("[ gt read from addr 0x%x ]\n",
                            (int)relative_addr);
                        odata = d->reg[relative_addr];
                } else {
                        debug("[ gt write to addr 0x%x:", (int)relative_addr);
                        for (i=0; i<len; i++)
                                debug(" %02x", data[i]);
                        debug(" ]\n");
                        d->reg[relative_addr] = idata;
                }
        }

        if (writeflag == MEM_READ)
                memory_writemax64(cpu, data, len, odata);

        return 1;
}


/*
 *  pci_gt_rr_011():
 */
static uint32_t pci_gt_rr_011(int reg)
{
        switch (reg) {
        case 0x00:
                return PCI_VENDOR_GALILEO + (PCI_PRODUCT_GALILEO_GT64011 << 16);
        case 0x08:
                return 0x06000001;      /*  Revision 1  */
        default:
                return 0;
        }
}


/*
 *  pci_gt_rr_120():
 */
static uint32_t pci_gt_rr_120(int reg)
{
        switch (reg) {
        case 0x00:
                return PCI_VENDOR_GALILEO + (PCI_PRODUCT_GALILEO_GT64120 << 16);
        case 0x08:
                return 0x06000002;      /*  Revision 2?  */
        default:
                return 0;
        }
}


/*
 *  pci_gt_init():
 */
void pci_gt_init(struct machine *machine, struct memory *mem)
{
}


/*
 *  dev_gt_init():
 *
 *  Initialize a GT device.  Return a pointer to the pci_data used, so that
 *  the caller may add PCI devices.  First, however, we add the GT device
 *  itself.
 */
struct pci_data *dev_gt_init(struct machine *machine, struct memory *mem,
        uint64_t baseaddr, int irq_nr, int pciirq, int type)
{
        struct gt_data *d;

        d = malloc(sizeof(struct gt_data));
        if (d == NULL) {
                fprintf(stderr, "out of memory\n");
                exit(1);
        }
        memset(d, 0, sizeof(struct gt_data));
        d->irqnr    = irq_nr;
        d->pciirq   = pciirq;
        d->pci_data = bus_pci_init(pciirq);

        switch (type) {
        case 11:
                d->type = PCI_PRODUCT_GALILEO_GT64011;
                break;
        case 120:
                d->type = PCI_PRODUCT_GALILEO_GT64120;
                break;
        default:fatal("dev_gt_init(): type must be 11 or 120.\n");
                exit(1);
        }

        /*
         *  According to NetBSD/cobalt:
         *  pchb0 at pci0 dev 0 function 0: Galileo GT-64011
         *  System Controller, rev 1
         */
        bus_pci_add(machine, d->pci_data, mem, 0, 0, 0, pci_gt_init,
            d->type == PCI_PRODUCT_GALILEO_GT64011?
            pci_gt_rr_011 : pci_gt_rr_120);

        memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH,
            dev_gt_access, d, MEM_DEFAULT, NULL);
        machine_add_tickfunction(machine, dev_gt_tick, d, TICK_STEPS_SHIFT);

        return d->pci_data;
}

1	dpavlin	4	/*
2			* Copyright (C) 2003-2005 Anders Gavare. All rights reserved.
3			*
4			* Redistribution and use in source and binary forms, with or without
5			* modification, are permitted provided that the following conditions are met:
6			*
7			* 1. Redistributions of source code must retain the above copyright
8			* notice, this list of conditions and the following disclaimer.
9			* 2. Redistributions in binary form must reproduce the above copyright
10			* notice, this list of conditions and the following disclaimer in the
11			* documentation and/or other materials provided with the distribution.
12			* 3. The name of the author may not be used to endorse or promote products
13			* derived from this software without specific prior written permission.
14			*
15			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25			* SUCH DAMAGE.
26			*
27			*
28	dpavlin	10	* $Id: dev_gt.c,v 1.22 2005/06/20 08:19:58 debug Exp $
29	dpavlin	4	*
30	dpavlin	10	* Galileo Technology GT-64xxx PCI controller.
31	dpavlin	4	*
32	dpavlin	10	* GT-64011 Used in Cobalt machines.
33			* GT-64120 Used in evbmips machines (Malta).
34			*
35	dpavlin	4	* TODO: This more or less just a dummy device, so far.
36			*/
37
38			#include <stdio.h>
39			#include <stdlib.h>
40			#include <string.h>
41
42			#include "bus_pci.h"
43			#include "cpu.h"
44			#include "devices.h"
45			#include "machine.h"
46			#include "memory.h"
47			#include "misc.h"
48
49
50			#define TICK_STEPS_SHIFT 16
51
52			#define PCI_VENDOR_GALILEO 0x11ab /* Galileo Technology */
53			#define PCI_PRODUCT_GALILEO_GT64011 0x4146 /* GT-64011 System Controller */
54	dpavlin	10	#define PCI_PRODUCT_GALILEO_GT64120 0x4620 /* GT-64120 */
55	dpavlin	4
56			struct gt_data {
57			int reg[8];
58			int irqnr;
59			int pciirq;
60	dpavlin	10	int type;
61	dpavlin	4
62			struct pci_data *pci_data;
63			};
64
65
66			/*
67			* dev_gt_tick():
68			*/
69			void dev_gt_tick(struct cpu cpu, void extra)
70			{
71			struct gt_data *gt_data = extra;
72
73			cpu_interrupt(cpu, gt_data->irqnr);
74			}
75
76
77			/*
78			* dev_gt_access():
79			*/
80			int dev_gt_access(struct cpu cpu, struct memory mem, uint64_t relative_addr,
81			unsigned char data, size_t len, int writeflag, void extra)
82			{
83			uint64_t idata = 0, odata = 0;
84			int i;
85			struct gt_data *d = extra;
86
87			idata = memory_readmax64(cpu, data, len);
88
89			switch (relative_addr) {
90			case 0xc18:
91			if (writeflag == MEM_WRITE) {
92			debug("[ gt write to 0xc18: data = 0x%08lx ]\n",
93			(long)idata);
94			return 1;
95			} else {
96			odata = 0xffffffffULL;
97			/* ??? interrupt something... */
98
99			odata = 0x00000100; /* netbsd/cobalt cobalt/machdep.c:cpu_intr() */
100
101			cpu_interrupt_ack(cpu, d->irqnr);
102
103			debug("[ gt read from 0xc18 (data = 0x%08lx) ]\n",
104			(long)odata);
105			}
106			break;
107			case 0xcf8: /* PCI ADDR */
108			case 0xcfc: /* PCI DATA */
109			if (writeflag == MEM_WRITE) {
110			bus_pci_access(cpu, mem, relative_addr, &idata,
111			writeflag, d->pci_data);
112			} else {
113			bus_pci_access(cpu, mem, relative_addr, &odata,
114			writeflag, d->pci_data);
115			}
116			break;
117			default:
118			if (writeflag==MEM_READ) {
119			debug("[ gt read from addr 0x%x ]\n",
120			(int)relative_addr);
121			odata = d->reg[relative_addr];
122			} else {
123			debug("[ gt write to addr 0x%x:", (int)relative_addr);
124			for (i=0; i<len; i++)
125			debug(" %02x", data[i]);
126			debug(" ]\n");
127			d->reg[relative_addr] = idata;
128			}
129			}
130
131			if (writeflag == MEM_READ)
132			memory_writemax64(cpu, data, len, odata);
133
134			return 1;
135			}
136
137
138			/*
139	dpavlin	10	* pci_gt_rr_011():
140	dpavlin	4	*/
141	dpavlin	10	static uint32_t pci_gt_rr_011(int reg)
142	dpavlin	4	{
143			switch (reg) {
144			case 0x00:
145			return PCI_VENDOR_GALILEO + (PCI_PRODUCT_GALILEO_GT64011 << 16);
146			case 0x08:
147	dpavlin	10	return 0x06000001; /* Revision 1 */
148	dpavlin	4	default:
149			return 0;
150			}
151			}
152
153
154			/*
155	dpavlin	10	* pci_gt_rr_120():
156			*/
157			static uint32_t pci_gt_rr_120(int reg)
158			{
159			switch (reg) {
160			case 0x00:
161			return PCI_VENDOR_GALILEO + (PCI_PRODUCT_GALILEO_GT64120 << 16);
162			case 0x08:
163			return 0x06000002; /* Revision 2? */
164			default:
165			return 0;
166			}
167			}
168
169
170			/*
171	dpavlin	4	* pci_gt_init():
172			*/
173			void pci_gt_init(struct machine machine, struct memory mem)
174			{
175			}
176
177
178			/*
179			* dev_gt_init():
180			*
181			* Initialize a GT device. Return a pointer to the pci_data used, so that
182			* the caller may add PCI devices. First, however, we add the GT device
183			* itself.
184			*/
185			struct pci_data dev_gt_init(struct machine machine, struct memory *mem,
186	dpavlin	10	uint64_t baseaddr, int irq_nr, int pciirq, int type)
187	dpavlin	4	{
188			struct gt_data *d;
189
190			d = malloc(sizeof(struct gt_data));
191			if (d == NULL) {
192			fprintf(stderr, "out of memory\n");
193			exit(1);
194			}
195			memset(d, 0, sizeof(struct gt_data));
196			d->irqnr = irq_nr;
197			d->pciirq = pciirq;
198			d->pci_data = bus_pci_init(pciirq);
199
200	dpavlin	10	switch (type) {
201			case 11:
202			d->type = PCI_PRODUCT_GALILEO_GT64011;
203			break;
204			case 120:
205			d->type = PCI_PRODUCT_GALILEO_GT64120;
206			break;
207			default:fatal("dev_gt_init(): type must be 11 or 120.\n");
208			exit(1);
209			}
210
211	dpavlin	4	/*
212			* According to NetBSD/cobalt:
213			* pchb0 at pci0 dev 0 function 0: Galileo GT-64011
214			* System Controller, rev 1
215			*/
216	dpavlin	10	bus_pci_add(machine, d->pci_data, mem, 0, 0, 0, pci_gt_init,
217			d->type == PCI_PRODUCT_GALILEO_GT64011?
218			pci_gt_rr_011 : pci_gt_rr_120);
219	dpavlin	4
220			memory_device_register(mem, "gt", baseaddr, DEV_GT_LENGTH,
221			dev_gt_access, d, MEM_DEFAULT, NULL);
222			machine_add_tickfunction(machine, dev_gt_tick, d, TICK_STEPS_SHIFT);
223
224			return d->pci_data;
225			}
226