1 |
/* |
2 |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
3 |
* |
4 |
* Redistribution and use in source and binary forms, with or without |
5 |
* modification, are permitted provided that the following conditions are met: |
6 |
* |
7 |
* 1. Redistributions of source code must retain the above copyright |
8 |
* notice, this list of conditions and the following disclaimer. |
9 |
* 2. Redistributions in binary form must reproduce the above copyright |
10 |
* notice, this list of conditions and the following disclaimer in the |
11 |
* documentation and/or other materials provided with the distribution. |
12 |
* 3. The name of the author may not be used to endorse or promote products |
13 |
* derived from this software without specific prior written permission. |
14 |
* |
15 |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
16 |
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
17 |
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
18 |
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
19 |
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
20 |
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
21 |
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
22 |
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
23 |
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
24 |
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
25 |
* SUCH DAMAGE. |
26 |
* |
27 |
* |
28 |
* $Id: dev_footbridge.c,v 1.48 2006/09/30 10:09:19 debug Exp $ |
29 |
* |
30 |
* Footbridge. Used in Netwinder and Cats. |
31 |
* |
32 |
* TODO: |
33 |
* o) Add actual support for the fcom serial port. |
34 |
* o) FIQs. |
35 |
* o) Pretty much everything else as well :) (This entire thing |
36 |
* is a quick hack to work primarily with NetBSD and OpenBSD |
37 |
* as a guest OS.) |
38 |
*/ |
39 |
|
40 |
#include <stdio.h> |
41 |
#include <stdlib.h> |
42 |
#include <string.h> |
43 |
|
44 |
#include "bus_pci.h" |
45 |
#include "console.h" |
46 |
#include "cpu.h" |
47 |
#include "device.h" |
48 |
#include "devices.h" |
49 |
#include "machine.h" |
50 |
#include "memory.h" |
51 |
#include "misc.h" |
52 |
#include "timer.h" |
53 |
|
54 |
|
55 |
#include "dc21285reg.h" |
56 |
|
57 |
#define DEV_FOOTBRIDGE_TICK_SHIFT 14 |
58 |
#define DEV_FOOTBRIDGE_LENGTH 0x400 |
59 |
|
60 |
|
61 |
static void timer_tick0(struct timer *t, void *extra) |
62 |
{ ((struct footbridge_data *)extra)->pending_timer_interrupts[0] ++; } |
63 |
static void timer_tick1(struct timer *t, void *extra) |
64 |
{ ((struct footbridge_data *)extra)->pending_timer_interrupts[1] ++; } |
65 |
static void timer_tick2(struct timer *t, void *extra) |
66 |
{ ((struct footbridge_data *)extra)->pending_timer_interrupts[2] ++; } |
67 |
static void timer_tick3(struct timer *t, void *extra) |
68 |
{ ((struct footbridge_data *)extra)->pending_timer_interrupts[3] ++; } |
69 |
|
70 |
|
71 |
static void reload_timer_value(struct cpu *cpu, struct footbridge_data *d, |
72 |
int timer_nr) |
73 |
{ |
74 |
double freq = (double)cpu->machine->emulated_hz; |
75 |
int cycles = d->timer_load[timer_nr]; |
76 |
|
77 |
if (d->timer_control[timer_nr] & TIMER_FCLK_16) |
78 |
cycles <<= 4; |
79 |
else if (d->timer_control[timer_nr] & TIMER_FCLK_256) |
80 |
cycles <<= 8; |
81 |
freq /= (double)cycles; |
82 |
|
83 |
d->timer_value[timer_nr] = d->timer_load[timer_nr]; |
84 |
d->timer_tick_countdown[timer_nr] = 1; |
85 |
|
86 |
/* printf("%i: %i -> %f Hz\n", timer_nr, |
87 |
d->timer_load[timer_nr], freq); */ |
88 |
|
89 |
if (d->timer[timer_nr] == NULL) { |
90 |
switch (timer_nr) { |
91 |
case 0: d->timer[0] = timer_add(freq, timer_tick0, d); break; |
92 |
case 1: d->timer[1] = timer_add(freq, timer_tick1, d); break; |
93 |
case 2: d->timer[2] = timer_add(freq, timer_tick2, d); break; |
94 |
case 3: d->timer[3] = timer_add(freq, timer_tick3, d); break; |
95 |
} |
96 |
} else { |
97 |
timer_update_frequency(d->timer[timer_nr], freq); |
98 |
} |
99 |
} |
100 |
|
101 |
|
102 |
/* |
103 |
* dev_footbridge_tick(): |
104 |
* |
105 |
* The 4 footbridge timers should decrease and cause interrupts. Periodic |
106 |
* interrupts restart as soon as they are acknowledged, non-periodic |
107 |
* interrupts need to be "reloaded" to restart. |
108 |
* |
109 |
* TODO: Hm. I thought I had solved this, but it didn't quite work. |
110 |
* This needs to be re-checked against documentation, sometime. |
111 |
*/ |
112 |
void dev_footbridge_tick(struct cpu *cpu, void *extra) |
113 |
{ |
114 |
int i; |
115 |
struct footbridge_data *d = (struct footbridge_data *) extra; |
116 |
|
117 |
for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) { |
118 |
if (d->timer_control[i] & TIMER_ENABLE) { |
119 |
if (d->pending_timer_interrupts[i] > 0) { |
120 |
d->timer_value[i] = random() % d->timer_load[i]; |
121 |
cpu_interrupt(cpu, IRQ_TIMER_1 + i); |
122 |
} |
123 |
} |
124 |
} |
125 |
} |
126 |
|
127 |
|
128 |
/* |
129 |
* dev_footbridge_isa_access(): |
130 |
* |
131 |
* Reading the byte at 0x79000000 is a quicker way to figure out which ISA |
132 |
* interrupt has occurred (and acknowledging it at the same time), than |
133 |
* dealing with the legacy 0x20/0xa0 ISA ports. |
134 |
*/ |
135 |
DEVICE_ACCESS(footbridge_isa) |
136 |
{ |
137 |
/* struct footbridge_data *d = extra; */ |
138 |
uint64_t idata = 0, odata = 0; |
139 |
int x; |
140 |
|
141 |
if (writeflag == MEM_WRITE) { |
142 |
idata = memory_readmax64(cpu, data, len); |
143 |
fatal("[ footbridge_isa: WARNING/TODO: write! ]\n"); |
144 |
} |
145 |
|
146 |
x = cpu->machine->isa_pic_data.last_int; |
147 |
if (x == 0) |
148 |
cpu_interrupt_ack(cpu, 32 + x); |
149 |
|
150 |
if (x < 8) |
151 |
odata = cpu->machine->isa_pic_data.pic1->irq_base + x; |
152 |
else |
153 |
odata = cpu->machine->isa_pic_data.pic2->irq_base + x - 8; |
154 |
|
155 |
if (writeflag == MEM_READ) |
156 |
memory_writemax64(cpu, data, len, odata); |
157 |
|
158 |
return 1; |
159 |
} |
160 |
|
161 |
|
162 |
/* |
163 |
* Reset pin at ISA port 0x338, at least in the NetWinder: |
164 |
* |
165 |
* TODO: NOT WORKING YET! |
166 |
*/ |
167 |
DEVICE_ACCESS(footbridge_reset) |
168 |
{ |
169 |
uint64_t idata = 0; |
170 |
|
171 |
if (writeflag == MEM_WRITE) { |
172 |
idata = memory_readmax64(cpu, data, len); |
173 |
if (idata & 0x40) { |
174 |
debug("[ footbridge_reset: GP16: Halting. ]\n"); |
175 |
cpu->running = 0; |
176 |
exit(1); |
177 |
} |
178 |
} |
179 |
|
180 |
return 1; |
181 |
} |
182 |
|
183 |
|
184 |
/* |
185 |
* dev_footbridge_pci_access(): |
186 |
* |
187 |
* The Footbridge PCI configuration space is implemented as a direct memory |
188 |
* space (i.e. not one port for addr and one port for data). This function |
189 |
* translates that into bus_pci calls. |
190 |
*/ |
191 |
DEVICE_ACCESS(footbridge_pci) |
192 |
{ |
193 |
struct footbridge_data *d = extra; |
194 |
uint64_t idata = 0, odata = 0; |
195 |
int bus, dev, func, reg; |
196 |
|
197 |
if (writeflag == MEM_WRITE) |
198 |
idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN); |
199 |
|
200 |
/* Decompose the (direct) address into its components: */ |
201 |
bus_pci_decompose_1(relative_addr, &bus, &dev, &func, ®); |
202 |
bus_pci_setaddr(cpu, d->pcibus, bus, dev, func, reg); |
203 |
|
204 |
if (bus == 255) { |
205 |
fatal("[ footbridge DEBUG ERROR: bus 255 unlikely," |
206 |
" pc (might not be updated) = 0x%08x ]\n", (int)cpu->pc); |
207 |
exit(1); |
208 |
} |
209 |
|
210 |
debug("[ footbridge pci: %s bus %i, device %i, function %i, register " |
211 |
"%i ]\n", writeflag == MEM_READ? "read from" : "write to", bus, |
212 |
dev, func, reg); |
213 |
|
214 |
bus_pci_data_access(cpu, d->pcibus, writeflag == MEM_READ? |
215 |
&odata : &idata, len, writeflag); |
216 |
|
217 |
if (writeflag == MEM_READ) |
218 |
memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata); |
219 |
|
220 |
return 1; |
221 |
} |
222 |
|
223 |
|
224 |
/* |
225 |
* dev_footbridge_access(): |
226 |
* |
227 |
* The DC21285 registers. |
228 |
*/ |
229 |
DEVICE_ACCESS(footbridge) |
230 |
{ |
231 |
struct footbridge_data *d = extra; |
232 |
uint64_t idata = 0, odata = 0; |
233 |
int timer_nr = 0; |
234 |
|
235 |
if (writeflag == MEM_WRITE) |
236 |
idata = memory_readmax64(cpu, data, len); |
237 |
|
238 |
if (relative_addr >= TIMER_1_LOAD && relative_addr <= TIMER_4_CLEAR) { |
239 |
timer_nr = (relative_addr >> 5) & (N_FOOTBRIDGE_TIMERS - 1); |
240 |
relative_addr &= ~0x060; |
241 |
} |
242 |
|
243 |
switch (relative_addr) { |
244 |
|
245 |
case VENDOR_ID: |
246 |
odata = 0x1011; /* DC21285_VENDOR_ID */ |
247 |
break; |
248 |
|
249 |
case DEVICE_ID: |
250 |
odata = 0x1065; /* DC21285_DEVICE_ID */ |
251 |
break; |
252 |
|
253 |
case 0x04: |
254 |
case 0x0c: |
255 |
case 0x10: |
256 |
case 0x14: |
257 |
case 0x18: |
258 |
/* TODO. Written to by Linux. */ |
259 |
break; |
260 |
|
261 |
case REVISION: |
262 |
odata = 3; /* footbridge revision number */ |
263 |
break; |
264 |
|
265 |
case PCI_ADDRESS_EXTENSION: |
266 |
/* TODO: Written to by Linux. */ |
267 |
if (writeflag == MEM_WRITE && idata != 0) |
268 |
fatal("[ footbridge: TODO: write to PCI_ADDRESS_" |
269 |
"EXTENSION: 0x%llx ]\n", (long long)idata); |
270 |
break; |
271 |
|
272 |
case SA_CONTROL: |
273 |
/* Read by Linux: */ |
274 |
odata = PCI_CENTRAL_FUNCTION; |
275 |
break; |
276 |
|
277 |
case UART_DATA: |
278 |
if (writeflag == MEM_WRITE) |
279 |
console_putchar(d->console_handle, idata); |
280 |
break; |
281 |
|
282 |
case UART_RX_STAT: |
283 |
/* TODO */ |
284 |
odata = 0; |
285 |
break; |
286 |
|
287 |
case UART_FLAGS: |
288 |
odata = UART_TX_EMPTY; |
289 |
break; |
290 |
|
291 |
case IRQ_STATUS: |
292 |
if (writeflag == MEM_READ) |
293 |
odata = d->irq_status & d->irq_enable; |
294 |
else { |
295 |
fatal("[ WARNING: footbridge write to irq status? ]\n"); |
296 |
exit(1); |
297 |
} |
298 |
break; |
299 |
|
300 |
case IRQ_RAW_STATUS: |
301 |
if (writeflag == MEM_READ) |
302 |
odata = d->irq_status; |
303 |
else { |
304 |
fatal("[ footbridge write to irq_raw_status ]\n"); |
305 |
exit(1); |
306 |
} |
307 |
break; |
308 |
|
309 |
case IRQ_ENABLE_SET: |
310 |
if (writeflag == MEM_WRITE) { |
311 |
d->irq_enable |= idata; |
312 |
cpu_interrupt(cpu, 64); |
313 |
} else { |
314 |
odata = d->irq_enable; |
315 |
fatal("[ WARNING: footbridge read from " |
316 |
"ENABLE SET? ]\n"); |
317 |
exit(1); |
318 |
} |
319 |
break; |
320 |
|
321 |
case IRQ_ENABLE_CLEAR: |
322 |
if (writeflag == MEM_WRITE) { |
323 |
d->irq_enable &= ~idata; |
324 |
cpu_interrupt(cpu, 64); |
325 |
} else { |
326 |
odata = d->irq_enable; |
327 |
fatal("[ WARNING: footbridge read from " |
328 |
"ENABLE CLEAR? ]\n"); |
329 |
exit(1); |
330 |
} |
331 |
break; |
332 |
|
333 |
case FIQ_STATUS: |
334 |
if (writeflag == MEM_READ) |
335 |
odata = d->fiq_status & d->fiq_enable; |
336 |
else { |
337 |
fatal("[ WARNING: footbridge write to fiq status? ]\n"); |
338 |
exit(1); |
339 |
} |
340 |
break; |
341 |
|
342 |
case FIQ_RAW_STATUS: |
343 |
if (writeflag == MEM_READ) |
344 |
odata = d->fiq_status; |
345 |
else { |
346 |
fatal("[ footbridge write to fiq_raw_status ]\n"); |
347 |
exit(1); |
348 |
} |
349 |
break; |
350 |
|
351 |
case FIQ_ENABLE_SET: |
352 |
if (writeflag == MEM_WRITE) |
353 |
d->fiq_enable |= idata; |
354 |
break; |
355 |
|
356 |
case FIQ_ENABLE_CLEAR: |
357 |
if (writeflag == MEM_WRITE) |
358 |
d->fiq_enable &= ~idata; |
359 |
break; |
360 |
|
361 |
case TIMER_1_LOAD: |
362 |
if (writeflag == MEM_READ) |
363 |
odata = d->timer_load[timer_nr]; |
364 |
else { |
365 |
d->timer_load[timer_nr] = idata & TIMER_MAX_VAL; |
366 |
reload_timer_value(cpu, d, timer_nr); |
367 |
/* debug("[ footbridge: timer %i (1-based), " |
368 |
"value %i ]\n", timer_nr + 1, |
369 |
(int)d->timer_value[timer_nr]); */ |
370 |
cpu_interrupt_ack(cpu, IRQ_TIMER_1 + timer_nr); |
371 |
} |
372 |
break; |
373 |
|
374 |
case TIMER_1_VALUE: |
375 |
if (writeflag == MEM_READ) |
376 |
odata = d->timer_value[timer_nr]; |
377 |
else |
378 |
d->timer_value[timer_nr] = idata & TIMER_MAX_VAL; |
379 |
break; |
380 |
|
381 |
case TIMER_1_CONTROL: |
382 |
if (writeflag == MEM_READ) |
383 |
odata = d->timer_control[timer_nr]; |
384 |
else { |
385 |
d->timer_control[timer_nr] = idata; |
386 |
if (idata & TIMER_FCLK_16 && |
387 |
idata & TIMER_FCLK_256) { |
388 |
fatal("TODO: footbridge timer: " |
389 |
"both 16 and 256?\n"); |
390 |
exit(1); |
391 |
} |
392 |
if (idata & TIMER_ENABLE) { |
393 |
reload_timer_value(cpu, d, timer_nr); |
394 |
} else { |
395 |
d->pending_timer_interrupts[timer_nr] = 0; |
396 |
} |
397 |
cpu_interrupt_ack(cpu, IRQ_TIMER_1 + timer_nr); |
398 |
} |
399 |
break; |
400 |
|
401 |
case TIMER_1_CLEAR: |
402 |
if (d->timer_control[timer_nr] & TIMER_MODE_PERIODIC) { |
403 |
reload_timer_value(cpu, d, timer_nr); |
404 |
} |
405 |
|
406 |
if (d->pending_timer_interrupts[timer_nr] > 0) { |
407 |
d->pending_timer_interrupts[timer_nr] --; |
408 |
} |
409 |
|
410 |
cpu_interrupt_ack(cpu, IRQ_TIMER_1 + timer_nr); |
411 |
break; |
412 |
|
413 |
default:if (writeflag == MEM_READ) { |
414 |
fatal("[ footbridge: read from 0x%x ]\n", |
415 |
(int)relative_addr); |
416 |
} else { |
417 |
fatal("[ footbridge: write to 0x%x: 0x%llx ]\n", |
418 |
(int)relative_addr, (long long)idata); |
419 |
} |
420 |
} |
421 |
|
422 |
if (writeflag == MEM_READ) |
423 |
memory_writemax64(cpu, data, len, odata); |
424 |
|
425 |
return 1; |
426 |
} |
427 |
|
428 |
|
429 |
DEVINIT(footbridge) |
430 |
{ |
431 |
struct footbridge_data *d; |
432 |
uint64_t pci_addr = 0x7b000000; |
433 |
int i; |
434 |
|
435 |
d = malloc(sizeof(struct footbridge_data)); |
436 |
if (d == NULL) { |
437 |
fprintf(stderr, "out of memory\n"); |
438 |
exit(1); |
439 |
} |
440 |
memset(d, 0, sizeof(struct footbridge_data)); |
441 |
|
442 |
/* DC21285 register access: */ |
443 |
memory_device_register(devinit->machine->memory, devinit->name, |
444 |
devinit->addr, DEV_FOOTBRIDGE_LENGTH, |
445 |
dev_footbridge_access, d, DM_DEFAULT, NULL); |
446 |
|
447 |
/* ISA interrupt status/acknowledgement: */ |
448 |
memory_device_register(devinit->machine->memory, "footbridge_isa", |
449 |
0x79000000, 8, dev_footbridge_isa_access, d, DM_DEFAULT, NULL); |
450 |
|
451 |
/* The "fcom" console: */ |
452 |
d->console_handle = console_start_slave(devinit->machine, "fcom", 0); |
453 |
|
454 |
/* A PCI bus: */ |
455 |
d->pcibus = bus_pci_init( |
456 |
devinit->machine, |
457 |
devinit->irq_nr, /* PCI controller irq */ |
458 |
0x7c000000, /* PCI device io offset */ |
459 |
0x80000000, /* PCI device mem offset */ |
460 |
0x00000000, /* PCI port base */ |
461 |
0x00000000, /* PCI mem base */ |
462 |
0, /* PCI irq base: TODO */ |
463 |
0x7c000000, /* ISA port base */ |
464 |
0x80000000, /* ISA mem base */ |
465 |
32); /* ISA port base */ |
466 |
|
467 |
/* ... with some default devices for known machine types: */ |
468 |
switch (devinit->machine->machine_type) { |
469 |
case MACHINE_CATS: |
470 |
bus_pci_add(devinit->machine, d->pcibus, |
471 |
devinit->machine->memory, 0xc0, 7, 0, "ali_m1543"); |
472 |
bus_pci_add(devinit->machine, d->pcibus, |
473 |
devinit->machine->memory, 0xc0, 10, 0, "dec21143"); |
474 |
bus_pci_add(devinit->machine, d->pcibus, |
475 |
devinit->machine->memory, 0xc0, 16, 0, "ali_m5229"); |
476 |
break; |
477 |
case MACHINE_NETWINDER: |
478 |
bus_pci_add(devinit->machine, d->pcibus, |
479 |
devinit->machine->memory, 0xc0, 11, 0, "symphony_83c553"); |
480 |
bus_pci_add(devinit->machine, d->pcibus, |
481 |
devinit->machine->memory, 0xc0, 11, 1, "symphony_82c105"); |
482 |
memory_device_register(devinit->machine->memory, |
483 |
"footbridge_reset", 0x7c000338, 1, |
484 |
dev_footbridge_reset_access, d, DM_DEFAULT, NULL); |
485 |
break; |
486 |
default:fatal("footbridge: unimplemented machine type.\n"); |
487 |
exit(1); |
488 |
} |
489 |
|
490 |
/* PCI configuration space: */ |
491 |
memory_device_register(devinit->machine->memory, |
492 |
"footbridge_pci", pci_addr, 0x1000000, |
493 |
dev_footbridge_pci_access, d, DM_DEFAULT, NULL); |
494 |
|
495 |
/* Timer ticks: */ |
496 |
for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) { |
497 |
d->timer_control[i] = TIMER_MODE_PERIODIC; |
498 |
d->timer_load[i] = TIMER_MAX_VAL; |
499 |
} |
500 |
machine_add_tickfunction(devinit->machine, |
501 |
dev_footbridge_tick, d, DEV_FOOTBRIDGE_TICK_SHIFT, 0.0); |
502 |
|
503 |
devinit->return_ptr = d; |
504 |
return 1; |
505 |
} |
506 |
|