/[gxemul]/trunk/src/devices/dev_footbridge.c
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Contents of /trunk/src/devices/dev_footbridge.c

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Revision 32 - (show annotations)
Mon Oct 8 16:20:58 2007 UTC (11 years, 11 months ago) by dpavlin
File MIME type: text/plain
File size: 13580 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1421 2006/11/06 05:32:37 debug Exp $
20060816	Adding a framework for emulated/virtual timers (src/timer.c),
		using only setitimer().
		Rewriting the mc146818 to use the new timer framework.
20060817	Adding a call to gettimeofday() every now and then (once every
		second, at the moment) to resynch the timer if it drifts.
		Beginning to convert the ISA timer interrupt mechanism (8253
		and 8259) to use the new timer framework.
		Removing the -I command line option.
20060819	Adding the -I command line option again, with new semantics.
		Working on Footbridge timer interrupts; NetBSD/NetWinder and
		NetBSD/CATS now run at correct speed, but unfortunately with
		HUGE delays during bootup.
20060821	Some minor m68k updates. Adding the first instruction: nop. :)
		Minor Alpha emulation updates.
20060822	Adding a FreeBSD development specific YAMON environment
		variable ("khz") (as suggested by Bruce M. Simpson).
		Moving YAMON environment variable initialization from
		machine_evbmips.c into promemul/yamon.c, and adding some more
		variables.
		Continuing on the LCA PCI bus controller (for Alpha machines).
20060823	Continuing on the timer stuff: experimenting with MIPS count/
		compare interrupts connected to the timer framework.
20060825	Adding bogus SCSI commands 0x51 (SCSICDROM_READ_DISCINFO) and
		0x52 (SCSICDROM_READ_TRACKINFO) to the SCSI emulation layer,
		to allow NetBSD/pmax 4.0_BETA to be installed from CDROM.
		Minor updates to the LCA PCI controller.
20060827	Implementing a CHIP8 cpu mode, and a corresponding CHIP8
		machine, for fun. Disassembly support for all instructions,
		and most of the common instructions have been implemented: mvi,
		mov_imm, add_imm, jmp, rand, cls, sprite, skeq_imm, jsr,
		skne_imm, bcd, rts, ldr, str, mov, or, and, xor, add, sub,
		font, ssound, sdelay, gdelay, bogus skup/skpr, skeq, skne.
20060828	Beginning to convert the CHIP8 cpu in the CHIP8 machine to a
		(more correct) RCA 180x cpu. (Disassembly for all 1802
		instructions has been implemented, but no execution yet, and
		no 1805 extended instructions.)
20060829	Minor Alpha emulation updates.
20060830	Beginning to experiment a little with PCI IDE for SGI O2.
		Fixing the cursor key mappings for MobilePro 770 emulation.
		Fixing the LK201 warning caused by recent NetBSD/pmax.
		The MIPS R41xx standby, suspend, and hibernate instructions now
		behave like the RM52xx/MIPS32/MIPS64 wait instruction.
		Fixing dev_wdc so it calculates correct (64-bit) offsets before
		giving them to diskimage_access().
20060831	Continuing on Alpha emulation (OSF1 PALcode).
20060901	Minor Alpha updates; beginning on virtual memory pagetables.
		Removed the limit for max nr of devices (in preparation for
		allowing devices' base addresses to be changed during runtime).
		Adding a hack for MIPS [d]mfc0 select 0 (except the count
		register), so that the coproc register is simply copied.
		The MIPS suspend instruction now exits the emulator, instead
		of being treated as a wait instruction (this causes NetBSD/
		hpcmips to get correct 'halt' behavior).
		The VR41xx RTC now returns correct time.
		Connecting the VR41xx timer to the timer framework (fixed at
		128 Hz, for now).
		Continuing on SPARC emulation, adding more instructions:
		restore, ba_xcc, ble. The rectangle drawing demo works :)
		Removing the last traces of the old ENABLE_CACHE_EMULATION
		MIPS stuff (not usable with dyntrans anyway).
20060902	Splitting up src/net.c into several smaller files in its own
		subdirectory (src/net/).
20060903	Cleanup of the files in src/net/, to make them less ugly.
20060904	Continuing on the 'settings' subsystem.
		Minor progress on the SPARC emulation mode.
20060905	Cleanup of various things, and connecting the settings
		infrastructure to various subsystems (emul, machine, cpu, etc).
		Changing the lk201 mouse update routine to not rely on any
		emulated hardware framebuffer cursor coordinates, but instead
		always do (semi-usable) relative movements.
20060906	Continuing on the lk201 mouse stuff. Mouse behaviour with
		multiple framebuffers (which was working in Ultrix) is now
		semi-broken (but it still works, in a way).
		Moving the documentation about networking into its own file
		(networking.html), and refreshing it a bit. Adding an example
		of how to use ethernet frame direct-access (udp_snoop).
20060907	Continuing on the settings infrastructure.
20060908	Minor updates to SH emulation: for 32-bit emulation: delay
		slots and the 'jsr @Rn' instruction. I'm putting 64-bit SH5 on
		ice, for now.
20060909-10	Implementing some more 32-bit SH instructions. Removing the
		64-bit mode completely. Enough has now been implemented to run
		the rectangle drawing demo. :-)
20060912	Adding more SH instructions.
20060916	Continuing on SH emulation (some more instructions: div0u,
		div1, rotcl/rotcr, more mov instructions, dt, braf, sets, sett,
		tst_imm, dmuls.l, subc, ldc_rm_vbr, movt, clrt, clrs, clrmac).
		Continuing on the settings subsystem (beginning on reading/
		writing settings, removing bugs, and connecting more cpus to
		the framework).
20060919	More work on SH emulation; adding an ldc banked instruction,
		and attaching a 640x480 framebuffer to the Dreamcast machine
		mode (NetBSD/dreamcast prints the NetBSD copyright banner :-),
		and then panics).
20060920	Continuing on the settings subsystem.
20060921	Fixing the Footbridge timer stuff so that NetBSD/cats and
		NetBSD/netwinder boot up without the delays.
20060922	Temporarily hardcoding MIPS timer interrupt to 100 Hz. With
		'wait' support disabled, NetBSD/malta and Linux/malta run at
		correct speed.
20060923	Connecting dev_gt to the timer framework, so that NetBSD/cobalt
		runs at correct speed.
		Moving SH4-specific memory mapped registers into its own
		device (dev_sh4.c).
		Running with -N now prints "idling" instead of bogus nr of
		instrs/second (which isn't valid anyway) while idling.
20060924	Algor emulation should now run at correct speed.
		Adding disassembly support for some MIPS64 revision 2
		instructions: ext, dext, dextm, dextu.
20060926	The timer framework now works also when the MIPS wait
		instruction is used.
20060928	Re-implementing checks for coprocessor availability for MIPS
		cop0 instructions. (Thanks to Carl van Schaik for noticing the
		lack of cop0 availability checks.)
20060929	Implementing an instruction combination hack which treats
		NetBSD/pmax' idle loop as a wait-like instruction.
20060930	The ENTRYHI_R_MASK was missing in (at least) memory_mips_v2p.c,
		causing TLB lookups to sometimes succeed when they should have
		failed. (A big thank you to Juli Mallett for noticing the
		problem.)
		Adding disassembly support for more MIPS64 revision 2 opcodes
		(seb, seh, wsbh, jalr.hb, jr.hb, synci, ins, dins, dinsu,
		dinsm, dsbh, dshd, ror, dror, rorv, drorv, dror32). Also
		implementing seb, seh, dsbh, dshd, and wsbh.
		Implementing an instruction combination hack for Linux/pmax'
		idle loop, similar to the NetBSD/pmax case.
20061001	Changing the NetBSD/sgimips install instructions to extract
		files from an iso image, instead of downloading them via ftp.
20061002	More-than-31-bit userland addresses in memory_mips_v2p.c were
		not actually working; applying a fix from Carl van Schaik to
		enable them to work + making some other updates (adding kuseg
		support).
		Fixing hpcmips (vr41xx) timer initialization.
		Experimenting with O(n)->O(1) reduction in the MIPS TLB lookup
		loop. Seems to work both for R3000 and non-R3000.
20061003	Continuing a little on SH emulation (adding more control
		registers; mini-cleanup of memory_sh.c).
20061004	Beginning on a dev_rtc, a clock/timer device for the test
		machines; also adding a demo, and some documentation.
		Fixing a bug in SH "mov.w @(disp,pc),Rn" (the result wasn't
		sign-extended), and adding the addc and ldtlb instructions.
20061005	Contining on SH emulation: virtual to physical address
		translation, and a skeleton exception mechanism.
20061006	Adding more SH instructions (various loads and stores, rte,
		negc, muls.w, various privileged register-move instructions).
20061007	More SH instructions: various move instructions, trapa, div0s,
		float, fdiv, ftrc.
		Continuing on dev_rtc; removing the rtc demo.
20061008	Adding a dummy Dreamcast PROM module. (Homebrew Dreamcast
		programs using KOS libs need this.)
		Adding more SH instructions: "stc vbr,rn", rotl, rotr, fsca,
		fmul, fadd, various floating-point moves, etc. A 256-byte
		demo for Dreamcast runs :-)
20061012	Adding the SH "lds Rm,pr" and bsr instructions.
20061013	More SH instructions: "sts fpscr,rn", tas.b, and some more
		floating point instructions, cmp/str, and more moves.
		Adding a dummy dev_pvr (Dreamcast graphics controller).
20061014	Generalizing the expression evaluator (used in the built-in
		debugger) to support parentheses and +-*/%^&|.
20061015	Removing the experimental tlb index hint code in
		mips_memory_v2p.c, since it didn't really have any effect.
20061017	Minor SH updates; adding the "sts pr,Rn", fcmp/gt, fneg,
		frchg, and some other instructions. Fixing missing sign-
		extension in an 8-bit load instruction.
20061019	Adding a simple dev_dreamcast_rtc.
		Implementing memory-mapped access to the SH ITLB/UTLB arrays.
20061021	Continuing on various SH and Dreamcast things: sh4 timers,
		debug messages for dev_pvr, fixing some virtual address
		translation bugs, adding the bsrf instruction.
		The NetBSD/dreamcast GENERIC_MD kernel now reaches userland :)
		Adding a dummy dev_dreamcast_asic.c (not really useful yet).
		Implementing simple support for Store Queues.
		Beginning on the PVR Tile Accelerator.
20061022	Generalizing the PVR framebuffer to support off-screen drawing,
		multiple bit-depths, etc. (A small speed penalty, but most
		likely worth it.)
		Adding more SH instructions (mulu.w, fcmp/eq, fsub, fmac,
		fschg, and some more); correcting bugs in "fsca" and "float".
20061024	Adding the SH ftrv (matrix * vector) instruction. Marcus
		Comstedt's "tatest" example runs :) (wireframe only).
		Correcting disassembly for SH floating point instructions that
		use the xd* registers.
		Adding the SH fsts instruction.
		In memory_device_dyntrans_access(), only the currently used
		range is now invalidated, and not the entire device range.
20061025	Adding a dummy AVR32 cpu mode skeleton.
20061026	Various Dreamcast updates; beginning on a Maple bus controller.
20061027	Continuing on the Maple bus. A bogus Controller, Keyboard, and
		Mouse can now be detected by NetBSD and KOS homebrew programs.
		Cleaning up the SH4 Timer Management Unit, and beginning on
		SH4 interrupts.
		Implementing the Dreamcast SYSASIC.
20061028	Continuing on the SYSASIC.
		Adding the SH fsqrt instruction.
		memory_sh.c now actually scans the ITLB.
		Fixing a bug in dev_sh4.c, related to associative writes into
		the memory-mapped UTLB array. NetBSD/dreamcast now reaches
		userland stably, and prints the "Terminal type?" message :-]
		Implementing enough of the Dreamcast keyboard to make NetBSD
		accept it for input.
		Enabling SuperH for stable (non-development) builds.
		Adding NetBSD/dreamcast to the documentation, although it
		doesn't support root-on-nfs yet.
20061029	Changing usleep(1) calls in the debugger to to usleep(10000)
		(according to Brian Foley, this makes GXemul run better on
		MacOS X).
		Making the Maple "Controller" do something (enough to barely
		interact with dcircus.elf).
20061030-31	Some progress on the PVR. More test programs start running (but
		with strange output).
		Various other SH4-related updates.
20061102	Various Dreamcast and SH4 updates; more KOS demos run now.
20061104	Adding a skeleton dev_mb8696x.c (the Dreamcast's LAN adapter).
20061105	Continuing on the MB8696x; NetBSD/dreamcast detects it as mbe0.
		Testing for the release.

==============  RELEASE 0.4.3  ==============


1 /*
2 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_footbridge.c,v 1.48 2006/09/30 10:09:19 debug Exp $
29 *
30 * Footbridge. Used in Netwinder and Cats.
31 *
32 * TODO:
33 * o) Add actual support for the fcom serial port.
34 * o) FIQs.
35 * o) Pretty much everything else as well :) (This entire thing
36 * is a quick hack to work primarily with NetBSD and OpenBSD
37 * as a guest OS.)
38 */
39
40 #include <stdio.h>
41 #include <stdlib.h>
42 #include <string.h>
43
44 #include "bus_pci.h"
45 #include "console.h"
46 #include "cpu.h"
47 #include "device.h"
48 #include "devices.h"
49 #include "machine.h"
50 #include "memory.h"
51 #include "misc.h"
52 #include "timer.h"
53
54
55 #include "dc21285reg.h"
56
57 #define DEV_FOOTBRIDGE_TICK_SHIFT 14
58 #define DEV_FOOTBRIDGE_LENGTH 0x400
59
60
61 static void timer_tick0(struct timer *t, void *extra)
62 { ((struct footbridge_data *)extra)->pending_timer_interrupts[0] ++; }
63 static void timer_tick1(struct timer *t, void *extra)
64 { ((struct footbridge_data *)extra)->pending_timer_interrupts[1] ++; }
65 static void timer_tick2(struct timer *t, void *extra)
66 { ((struct footbridge_data *)extra)->pending_timer_interrupts[2] ++; }
67 static void timer_tick3(struct timer *t, void *extra)
68 { ((struct footbridge_data *)extra)->pending_timer_interrupts[3] ++; }
69
70
71 static void reload_timer_value(struct cpu *cpu, struct footbridge_data *d,
72 int timer_nr)
73 {
74 double freq = (double)cpu->machine->emulated_hz;
75 int cycles = d->timer_load[timer_nr];
76
77 if (d->timer_control[timer_nr] & TIMER_FCLK_16)
78 cycles <<= 4;
79 else if (d->timer_control[timer_nr] & TIMER_FCLK_256)
80 cycles <<= 8;
81 freq /= (double)cycles;
82
83 d->timer_value[timer_nr] = d->timer_load[timer_nr];
84 d->timer_tick_countdown[timer_nr] = 1;
85
86 /* printf("%i: %i -> %f Hz\n", timer_nr,
87 d->timer_load[timer_nr], freq); */
88
89 if (d->timer[timer_nr] == NULL) {
90 switch (timer_nr) {
91 case 0: d->timer[0] = timer_add(freq, timer_tick0, d); break;
92 case 1: d->timer[1] = timer_add(freq, timer_tick1, d); break;
93 case 2: d->timer[2] = timer_add(freq, timer_tick2, d); break;
94 case 3: d->timer[3] = timer_add(freq, timer_tick3, d); break;
95 }
96 } else {
97 timer_update_frequency(d->timer[timer_nr], freq);
98 }
99 }
100
101
102 /*
103 * dev_footbridge_tick():
104 *
105 * The 4 footbridge timers should decrease and cause interrupts. Periodic
106 * interrupts restart as soon as they are acknowledged, non-periodic
107 * interrupts need to be "reloaded" to restart.
108 *
109 * TODO: Hm. I thought I had solved this, but it didn't quite work.
110 * This needs to be re-checked against documentation, sometime.
111 */
112 void dev_footbridge_tick(struct cpu *cpu, void *extra)
113 {
114 int i;
115 struct footbridge_data *d = (struct footbridge_data *) extra;
116
117 for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) {
118 if (d->timer_control[i] & TIMER_ENABLE) {
119 if (d->pending_timer_interrupts[i] > 0) {
120 d->timer_value[i] = random() % d->timer_load[i];
121 cpu_interrupt(cpu, IRQ_TIMER_1 + i);
122 }
123 }
124 }
125 }
126
127
128 /*
129 * dev_footbridge_isa_access():
130 *
131 * Reading the byte at 0x79000000 is a quicker way to figure out which ISA
132 * interrupt has occurred (and acknowledging it at the same time), than
133 * dealing with the legacy 0x20/0xa0 ISA ports.
134 */
135 DEVICE_ACCESS(footbridge_isa)
136 {
137 /* struct footbridge_data *d = extra; */
138 uint64_t idata = 0, odata = 0;
139 int x;
140
141 if (writeflag == MEM_WRITE) {
142 idata = memory_readmax64(cpu, data, len);
143 fatal("[ footbridge_isa: WARNING/TODO: write! ]\n");
144 }
145
146 x = cpu->machine->isa_pic_data.last_int;
147 if (x == 0)
148 cpu_interrupt_ack(cpu, 32 + x);
149
150 if (x < 8)
151 odata = cpu->machine->isa_pic_data.pic1->irq_base + x;
152 else
153 odata = cpu->machine->isa_pic_data.pic2->irq_base + x - 8;
154
155 if (writeflag == MEM_READ)
156 memory_writemax64(cpu, data, len, odata);
157
158 return 1;
159 }
160
161
162 /*
163 * Reset pin at ISA port 0x338, at least in the NetWinder:
164 *
165 * TODO: NOT WORKING YET!
166 */
167 DEVICE_ACCESS(footbridge_reset)
168 {
169 uint64_t idata = 0;
170
171 if (writeflag == MEM_WRITE) {
172 idata = memory_readmax64(cpu, data, len);
173 if (idata & 0x40) {
174 debug("[ footbridge_reset: GP16: Halting. ]\n");
175 cpu->running = 0;
176 exit(1);
177 }
178 }
179
180 return 1;
181 }
182
183
184 /*
185 * dev_footbridge_pci_access():
186 *
187 * The Footbridge PCI configuration space is implemented as a direct memory
188 * space (i.e. not one port for addr and one port for data). This function
189 * translates that into bus_pci calls.
190 */
191 DEVICE_ACCESS(footbridge_pci)
192 {
193 struct footbridge_data *d = extra;
194 uint64_t idata = 0, odata = 0;
195 int bus, dev, func, reg;
196
197 if (writeflag == MEM_WRITE)
198 idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN);
199
200 /* Decompose the (direct) address into its components: */
201 bus_pci_decompose_1(relative_addr, &bus, &dev, &func, &reg);
202 bus_pci_setaddr(cpu, d->pcibus, bus, dev, func, reg);
203
204 if (bus == 255) {
205 fatal("[ footbridge DEBUG ERROR: bus 255 unlikely,"
206 " pc (might not be updated) = 0x%08x ]\n", (int)cpu->pc);
207 exit(1);
208 }
209
210 debug("[ footbridge pci: %s bus %i, device %i, function %i, register "
211 "%i ]\n", writeflag == MEM_READ? "read from" : "write to", bus,
212 dev, func, reg);
213
214 bus_pci_data_access(cpu, d->pcibus, writeflag == MEM_READ?
215 &odata : &idata, len, writeflag);
216
217 if (writeflag == MEM_READ)
218 memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata);
219
220 return 1;
221 }
222
223
224 /*
225 * dev_footbridge_access():
226 *
227 * The DC21285 registers.
228 */
229 DEVICE_ACCESS(footbridge)
230 {
231 struct footbridge_data *d = extra;
232 uint64_t idata = 0, odata = 0;
233 int timer_nr = 0;
234
235 if (writeflag == MEM_WRITE)
236 idata = memory_readmax64(cpu, data, len);
237
238 if (relative_addr >= TIMER_1_LOAD && relative_addr <= TIMER_4_CLEAR) {
239 timer_nr = (relative_addr >> 5) & (N_FOOTBRIDGE_TIMERS - 1);
240 relative_addr &= ~0x060;
241 }
242
243 switch (relative_addr) {
244
245 case VENDOR_ID:
246 odata = 0x1011; /* DC21285_VENDOR_ID */
247 break;
248
249 case DEVICE_ID:
250 odata = 0x1065; /* DC21285_DEVICE_ID */
251 break;
252
253 case 0x04:
254 case 0x0c:
255 case 0x10:
256 case 0x14:
257 case 0x18:
258 /* TODO. Written to by Linux. */
259 break;
260
261 case REVISION:
262 odata = 3; /* footbridge revision number */
263 break;
264
265 case PCI_ADDRESS_EXTENSION:
266 /* TODO: Written to by Linux. */
267 if (writeflag == MEM_WRITE && idata != 0)
268 fatal("[ footbridge: TODO: write to PCI_ADDRESS_"
269 "EXTENSION: 0x%llx ]\n", (long long)idata);
270 break;
271
272 case SA_CONTROL:
273 /* Read by Linux: */
274 odata = PCI_CENTRAL_FUNCTION;
275 break;
276
277 case UART_DATA:
278 if (writeflag == MEM_WRITE)
279 console_putchar(d->console_handle, idata);
280 break;
281
282 case UART_RX_STAT:
283 /* TODO */
284 odata = 0;
285 break;
286
287 case UART_FLAGS:
288 odata = UART_TX_EMPTY;
289 break;
290
291 case IRQ_STATUS:
292 if (writeflag == MEM_READ)
293 odata = d->irq_status & d->irq_enable;
294 else {
295 fatal("[ WARNING: footbridge write to irq status? ]\n");
296 exit(1);
297 }
298 break;
299
300 case IRQ_RAW_STATUS:
301 if (writeflag == MEM_READ)
302 odata = d->irq_status;
303 else {
304 fatal("[ footbridge write to irq_raw_status ]\n");
305 exit(1);
306 }
307 break;
308
309 case IRQ_ENABLE_SET:
310 if (writeflag == MEM_WRITE) {
311 d->irq_enable |= idata;
312 cpu_interrupt(cpu, 64);
313 } else {
314 odata = d->irq_enable;
315 fatal("[ WARNING: footbridge read from "
316 "ENABLE SET? ]\n");
317 exit(1);
318 }
319 break;
320
321 case IRQ_ENABLE_CLEAR:
322 if (writeflag == MEM_WRITE) {
323 d->irq_enable &= ~idata;
324 cpu_interrupt(cpu, 64);
325 } else {
326 odata = d->irq_enable;
327 fatal("[ WARNING: footbridge read from "
328 "ENABLE CLEAR? ]\n");
329 exit(1);
330 }
331 break;
332
333 case FIQ_STATUS:
334 if (writeflag == MEM_READ)
335 odata = d->fiq_status & d->fiq_enable;
336 else {
337 fatal("[ WARNING: footbridge write to fiq status? ]\n");
338 exit(1);
339 }
340 break;
341
342 case FIQ_RAW_STATUS:
343 if (writeflag == MEM_READ)
344 odata = d->fiq_status;
345 else {
346 fatal("[ footbridge write to fiq_raw_status ]\n");
347 exit(1);
348 }
349 break;
350
351 case FIQ_ENABLE_SET:
352 if (writeflag == MEM_WRITE)
353 d->fiq_enable |= idata;
354 break;
355
356 case FIQ_ENABLE_CLEAR:
357 if (writeflag == MEM_WRITE)
358 d->fiq_enable &= ~idata;
359 break;
360
361 case TIMER_1_LOAD:
362 if (writeflag == MEM_READ)
363 odata = d->timer_load[timer_nr];
364 else {
365 d->timer_load[timer_nr] = idata & TIMER_MAX_VAL;
366 reload_timer_value(cpu, d, timer_nr);
367 /* debug("[ footbridge: timer %i (1-based), "
368 "value %i ]\n", timer_nr + 1,
369 (int)d->timer_value[timer_nr]); */
370 cpu_interrupt_ack(cpu, IRQ_TIMER_1 + timer_nr);
371 }
372 break;
373
374 case TIMER_1_VALUE:
375 if (writeflag == MEM_READ)
376 odata = d->timer_value[timer_nr];
377 else
378 d->timer_value[timer_nr] = idata & TIMER_MAX_VAL;
379 break;
380
381 case TIMER_1_CONTROL:
382 if (writeflag == MEM_READ)
383 odata = d->timer_control[timer_nr];
384 else {
385 d->timer_control[timer_nr] = idata;
386 if (idata & TIMER_FCLK_16 &&
387 idata & TIMER_FCLK_256) {
388 fatal("TODO: footbridge timer: "
389 "both 16 and 256?\n");
390 exit(1);
391 }
392 if (idata & TIMER_ENABLE) {
393 reload_timer_value(cpu, d, timer_nr);
394 } else {
395 d->pending_timer_interrupts[timer_nr] = 0;
396 }
397 cpu_interrupt_ack(cpu, IRQ_TIMER_1 + timer_nr);
398 }
399 break;
400
401 case TIMER_1_CLEAR:
402 if (d->timer_control[timer_nr] & TIMER_MODE_PERIODIC) {
403 reload_timer_value(cpu, d, timer_nr);
404 }
405
406 if (d->pending_timer_interrupts[timer_nr] > 0) {
407 d->pending_timer_interrupts[timer_nr] --;
408 }
409
410 cpu_interrupt_ack(cpu, IRQ_TIMER_1 + timer_nr);
411 break;
412
413 default:if (writeflag == MEM_READ) {
414 fatal("[ footbridge: read from 0x%x ]\n",
415 (int)relative_addr);
416 } else {
417 fatal("[ footbridge: write to 0x%x: 0x%llx ]\n",
418 (int)relative_addr, (long long)idata);
419 }
420 }
421
422 if (writeflag == MEM_READ)
423 memory_writemax64(cpu, data, len, odata);
424
425 return 1;
426 }
427
428
429 DEVINIT(footbridge)
430 {
431 struct footbridge_data *d;
432 uint64_t pci_addr = 0x7b000000;
433 int i;
434
435 d = malloc(sizeof(struct footbridge_data));
436 if (d == NULL) {
437 fprintf(stderr, "out of memory\n");
438 exit(1);
439 }
440 memset(d, 0, sizeof(struct footbridge_data));
441
442 /* DC21285 register access: */
443 memory_device_register(devinit->machine->memory, devinit->name,
444 devinit->addr, DEV_FOOTBRIDGE_LENGTH,
445 dev_footbridge_access, d, DM_DEFAULT, NULL);
446
447 /* ISA interrupt status/acknowledgement: */
448 memory_device_register(devinit->machine->memory, "footbridge_isa",
449 0x79000000, 8, dev_footbridge_isa_access, d, DM_DEFAULT, NULL);
450
451 /* The "fcom" console: */
452 d->console_handle = console_start_slave(devinit->machine, "fcom", 0);
453
454 /* A PCI bus: */
455 d->pcibus = bus_pci_init(
456 devinit->machine,
457 devinit->irq_nr, /* PCI controller irq */
458 0x7c000000, /* PCI device io offset */
459 0x80000000, /* PCI device mem offset */
460 0x00000000, /* PCI port base */
461 0x00000000, /* PCI mem base */
462 0, /* PCI irq base: TODO */
463 0x7c000000, /* ISA port base */
464 0x80000000, /* ISA mem base */
465 32); /* ISA port base */
466
467 /* ... with some default devices for known machine types: */
468 switch (devinit->machine->machine_type) {
469 case MACHINE_CATS:
470 bus_pci_add(devinit->machine, d->pcibus,
471 devinit->machine->memory, 0xc0, 7, 0, "ali_m1543");
472 bus_pci_add(devinit->machine, d->pcibus,
473 devinit->machine->memory, 0xc0, 10, 0, "dec21143");
474 bus_pci_add(devinit->machine, d->pcibus,
475 devinit->machine->memory, 0xc0, 16, 0, "ali_m5229");
476 break;
477 case MACHINE_NETWINDER:
478 bus_pci_add(devinit->machine, d->pcibus,
479 devinit->machine->memory, 0xc0, 11, 0, "symphony_83c553");
480 bus_pci_add(devinit->machine, d->pcibus,
481 devinit->machine->memory, 0xc0, 11, 1, "symphony_82c105");
482 memory_device_register(devinit->machine->memory,
483 "footbridge_reset", 0x7c000338, 1,
484 dev_footbridge_reset_access, d, DM_DEFAULT, NULL);
485 break;
486 default:fatal("footbridge: unimplemented machine type.\n");
487 exit(1);
488 }
489
490 /* PCI configuration space: */
491 memory_device_register(devinit->machine->memory,
492 "footbridge_pci", pci_addr, 0x1000000,
493 dev_footbridge_pci_access, d, DM_DEFAULT, NULL);
494
495 /* Timer ticks: */
496 for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) {
497 d->timer_control[i] = TIMER_MODE_PERIODIC;
498 d->timer_load[i] = TIMER_MAX_VAL;
499 }
500 machine_add_tickfunction(devinit->machine,
501 dev_footbridge_tick, d, DEV_FOOTBRIDGE_TICK_SHIFT, 0.0);
502
503 devinit->return_ptr = d;
504 return 1;
505 }
506

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